JP2001177096A - Vertical semiconductor device, and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce variations in electrical characteristics, the cracking and chipping of a semiconductor substrate, or the like in the thin, vertical semiconductor device of a semiconductor substrate. SOLUTION: A sufficiently thick metal thin film is deposited on a surface side including a MOS structure part, or a sufficiently thick photo resist is applied, the surface is polished for flattering, and then the other surface side is polished, thus machining a semiconductor substrate to desired thickness.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vertical power semiconductor device used for a power converter or the like, and more particularly to a method of manufacturing the same.

[0002]

2. Description of the Related Art A power semiconductor device for controlling a large current is a so-called vertical type of a type in which electrodes are provided on both main surfaces of a semiconductor substrate and current flows in the thickness direction of the semiconductor substrate in order to increase the utilization rate of the semiconductor substrate. Type semiconductor device. In recent years, a power semiconductor device having a control electrode structure (also referred to as a gate structure) made of a metal-oxide-semiconductor (MOS) such as an insulated gate bipolar transistor (hereinafter referred to as an IGBT) having a withstand voltage of 600 to 1200 V operates. In order to reduce the energy loss at the time and reduce the wafer cost, a technique of using a floating zone (hereinafter, referred to as FZ) substrate which is cheaper than an epitaxial substrate and further reducing the thickness of the semiconductor substrate has been developed.

If the thickness of the semiconductor substrate is reduced from the beginning of the wafer process, for example, to 150 μm or less, the semiconductor substrate is easily damaged during the wafer process. In order to avoid such a situation, usually, the MOS gate structure and all the main electrodes on the side are formed using a somewhat thick wafer, and then the other main surface of the semiconductor substrate is mechanically polished at the last stage of the wafer process. In some cases, a method of forming the electrode on the back surface side after processing to a desired thickness by adding chemical etching sometimes is employed.

[0004] Taking a non-punch through (hereinafter referred to as NPT) type IGBT as an example, a general manufacturing method thereof will be described below. 3A and 3B are cross-sectional views in the order of steps according to a conventional method of manufacturing an IGBT. FIG. 3A shows that after a MOS gate structure is formed on one main surface (emitter side, hereinafter referred to as a front side) of a semiconductor substrate, a channel forming region 13 is formed.
FIG. 2 is a cross-sectional view of the IGBT in which an emitter region 14 is formed and a metal thin film 3 serving as an emitter electrode is deposited.

The MOS gate structure formed on the semiconductor substrate 1 is composed of a gate oxide film 5, a gate electrode layer 6 made of a conductive polycrystalline silicon film, and a gate electrode layer 6 and a metal thin film 3 serving as an emitter electrode. An insulating interlayer 2 made of, for example, phosphorus silicate glass (hereinafter referred to as PSG) to be insulated.
The gate oxide film 5 has a thickness of usually several tens nm,
Since it is sufficiently thinner than the gate electrode layer 6 and the interlayer insulating film 2 of about μm, the step between the MOS structure and the surface of the semiconductor substrate is
It becomes almost equal to the sum of the thicknesses of the polycrystalline silicon film 6 and the interlayer insulating film 2. The metal thin film 3 is formed, for example, by sputtering aluminum containing a small amount of silicon. The thickness is 3 ~
5 μm. In addition, as shown in the figure, it is often extended on a MOS gate structure. Then, a step between the MOS gate structure and the surface of the semiconductor substrate remains as it is on the surface of the metal thin film 3 as it is.

After that, the other main surface side (collector side, hereinafter referred to as back side) of the semiconductor substrate 1 is mechanically polished. When the back surface is polished in this state, the portion with the MOS gate structure is pressed more strongly against the grindstone than the portion without the MOS gate structure, resulting in a difference in the polishing rate. As a result, a step on the back surface reflects the surface structure to some extent. The image is transferred (FIG. 2B). Reference numeral 7 denotes a semiconductor substrate after back polishing. At this time, a protective seal 4 or the like may be attached to the front surface including the MOS gate structure. Further, in order to remove the damaged layer by polishing, the back surface is mechanically polished and then chemically etched, but the step transferred to the back surface remains. Thereafter, acceptor-type impurities are ion-implanted and activated on the back surface, and a collector electrode is formed by vapor deposition or the like.

[0007]

As described above, as described above, MOS
In a controlled device, when processing to the desired thickness, MOS
After forming the gate structure, the back surface of the semiconductor substrate is mechanically polished. At this time, the manner in which the stress is applied is partially different depending on the structure of the front surface, so that the polishing rate is uneven and the step is transferred to the back surface.

[0008] As the thickness of the polished wafer becomes thinner, the influence thereof becomes larger. As a result, the electrical characteristics of the manufactured device vary, and defects such as cracking or chipping of the wafer during polishing occur. There is. In view of this problem, an object of the present invention is to provide a method of manufacturing a semiconductor device in which the thickness of a semiconductor substrate is thin and uniform, the electrical characteristics of the device do not vary, and the wafer does not crack or chip. It is in.

[0009]

In order to solve the above-mentioned problems, the present invention provides a semiconductor substrate having a first electrode and a control electrode structure on a first main surface and a second electrode on a second main surface. In the method of manufacturing a vertical semiconductor device having, after forming a control electrode and a first electrode, once the surface of the first main surface side is once flattened, then the second main surface side of the semiconductor substrate is mechanically or A second electrode is formed by chemical polishing to a desired substrate thickness.

In this case, the first main surface side is first flattened with reference to the second main surface of the smooth semiconductor substrate, and then the flattened first main surface side is used as a reference. As a reference, the second main surface side is flattened, so that no irregularities remain on the second main surface side, and the second main surface side becomes smooth. In particular, after a metal thin film serving as a first main electrode, which is sufficiently thicker than the step between the control electrode structure and the semiconductor substrate surface of the first main surface, is formed on the first main surface, the surface of the metal thin film is mechanically If it is polished or chemically polished and flattened, and then the second main surface side is polished, the thickness of the metal thin film that becomes the first main electrode and the process of polishing the surface layer only increase, Can be easily implemented.

After forming the metal thin film serving as the first main electrode, a coating film thicker than the step between the control electrode structure and the semiconductor substrate surface on the first main surface is formed on the first main surface. The surface of the coating film may be mechanically or chemically polished and flattened, and then the second main surface side may be polished. Even in such a case, since the first main surface side is once flattened, and then the second main surface is polished based on the first main surface side, no irregularities remain on the second main surface.

As the surface film, a photoresist can be used. Photoresist is a material that is frequently used in semiconductor processes and is a material that is used to handling,
And it has appropriate hardness. Furthermore, the second main surface side of the semiconductor substrate is mechanically or chemically polished, and impurities are introduced into the surface layer, and then the second electrode is formed.

After the second main surface of the semiconductor substrate is polished to a predetermined thickness and then impurities suitable for forming an electrode on the second main surface are introduced, stable contact can be obtained. As a vertical semiconductor device, in a vertical semiconductor device having a first electrode and a control electrode structure on a first main surface of a semiconductor substrate and a second electrode on a second main surface, the first electrode is It is assumed that the electrode extends on the control electrode structure and has a polished flat surface.

In such a semiconductor device, since the second main surface has no irregularities affected by the first main surface side, there are few wafer cracks and chips during polishing, and the electrical characteristics of the manufactured device are small. Characteristics have less variation. In particular, in a vertical semiconductor device having a control electrode structure composed of a metal-insulating film-semiconductor substrate (MOS), a step due to the control electrode structure is inevitable, but since the first main surface side is smoothed, The problem is overcome.

Furthermore, a semiconductor substrate having a thickness of 150 μm or less is susceptible to slight irregularities and is liable to break, but even a semiconductor device having such a thin substrate is unlikely to break.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. [Embodiment 1] FIGS. 1A to 1C are sectional views in the order of steps according to the manufacturing method of the present invention. FIG. 1A shows an example in which one main surface (emitter side, hereinafter referred to as a front side) of a semiconductor substrate has an MO.
IG after forming S gate structure and depositing metal thin film 3
It is sectional drawing of BT. For example, IGB of 1200V class
In the case of T, the thickness of the semiconductor substrate is 250 μm.

After an impurity is introduced into the semiconductor substrate 1 to form a junction structure, a MOS gate structure including a gate oxide film 5, a gate electrode layer 6 made of a conductive polycrystalline silicon film, and an interlayer insulating film 2 of PSG is provided. Then, a metal thin film 8 serving as an emitter electrode is formed thereon. For example, the gate oxide film 5 has a thickness of 80 nm, and the gate electrode layer 6 and the interlayer insulating film 2 each have a thickness of about 1 μm. Thus, the gate oxide film 5
Is sufficiently thinner than the gate electrode layer 6 and the interlayer insulating film 2, the step between the MOS structure and the surface of the semiconductor substrate is substantially equal to the total thickness of the polycrystalline silicon film 6 and the interlayer insulating film 2. The thickness of the metal thin film 8 is initially 10 μm.

The difference from the conventional method of FIG. 3 is that the metal thin film 3 is deposited sufficiently thicker than the step of the MOS structure. Next, the thick metal thin film 8 is polished by about 4 μm using an abrasive containing about 0.05 μm diamond or alumina particles to flatten the surface [FIG. 1 (b)]. 9 is a metal thin film whose surface is flattened. Thus, the surface including the MOS structure can be flattened. If the initial thickness of the metal thin film 8 is smaller than the step of the MOS structure, it is natural that complete flattening cannot be performed. It is desirable that the thickness of the metal thin film 8 be at least twice as large as the step of the MOS structure because the larger the cutting allowance is, the easier the process is.

Further, the back surface of the semiconductor substrate 1 is polished by mechanical polishing to a thickness of 150 μm (FIG. 1C). At this time, since the reference is the flattened front side, the back side can be polished flat without being affected by the step of the MOS structure. Reference numeral 10 denotes a semiconductor substrate whose back surface is polished. Thereafter, as in the conventional case, ion implantation and activation of acceptor-type impurities are performed on the back surface, and a collector electrode is formed by vapor deposition or the like.

By adopting such a manufacturing method, not only the variance in characteristics based on the difference in thickness observed in the conventional IGBT but also the cracking and chipping of the wafer are eliminated, and furthermore, it is reduced to about 100 μm. It became possible to make it thinner. [Embodiment 2] FIGS. 2A to 2C are cross-sectional views in the order of steps according to another manufacturing method of the present invention.

After all the structures on the front side including the MOS structure are formed in the same manner as in the ordinary process, a photoresist 11 having a thickness sufficiently larger than the step between the MOS structure and the semiconductor substrate, for example, a thickness of 5 μm is applied. [FIG. 2 (a)]. It is desirable that the thickness of the photoresist 11 be at least twice as large as the step between the MOS structure and the surface of the semiconductor substrate for the above-described reason.

The surface side of the photoresist 11 is 3 to 4 μm
It is polished and flattened [FIG. Reference numeral 12 denotes a photoresist whose surface is flattened. As in the first embodiment, the back surface of the semiconductor substrate 1 is polished by mechanical polishing to a thickness of 150 mm.
μm [(c) in the figure]. Reference numeral 10 denotes a semiconductor substrate having a flat back surface. After polishing the back side, the photoresist on the front side is peeled off, ion implantation and activation of acceptor type impurities are performed on the back side, and a collector electrode is formed by vapor deposition or the like.

According to such a manufacturing method, the same effect as the method of the first embodiment was obtained. Further, the coating film used as the polishing allowance on the front side is not limited to the photoresist, but may be a polyimide resin film or the like.

[0024]

As described above, according to the present invention, after forming the control electrode and the first electrode, the surface on the first main surface side is once flattened, and then the second main surface of the semiconductor substrate is formed. The surface side is mechanically or chemically polished to a desired substrate thickness, and the second electrode is formed, whereby the surface shape on the back side can be flattened, and variations in electrical characteristics and wafer Cracks and chips can be reduced.

In order to obtain a smooth surface, a metal thin film serving as the first main electrode or a coating film such as a photoresist, which is sufficiently thicker than a step between the control electrode structure and the semiconductor substrate surface of the first main surface, is used. This is an extremely useful invention that enables a power semiconductor device having a control electrode having a MOS structure with low loss, in particular.

[Brief description of the drawings]

FIGS. 1A to 1C are cross-sectional views in the order of main steps for explaining a method of manufacturing an IGBT according to the present invention.

FIGS. 2A to 2C are cross-sectional views in the main order of steps for explaining another manufacturing method according to the present invention.

FIGS. 3A to 3C are cross-sectional views in the order of steps of a conventional method for manufacturing an IGBT.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Interlayer insulating film 3 Metal thin film 4 Protective seal 5 Gate oxide film 6 Conductive polycrystalline silicon film 7 Backside polished semiconductor substrate 8 Thickly deposited metal thin film 9 Flattened metal thin film 10 Backside polished semiconductor substrate 11 Thickly applied photoresist 12 Planarized photoresist 13 Channel formation region 14 Emitter region

Claims (8)

[Claims] In a method for manufacturing a vertical semiconductor device having a first electrode on a first main surface of a semiconductor substrate and a control electrode structure, and a second electrode on a second main surface, the control electrode and the control electrode structure are provided. After forming one electrode, the surface on the first main surface side is once flattened, and then the second main surface side of the semiconductor substrate is mechanically or chemically polished to a desired substrate thickness. A method for manufacturing a vertical semiconductor device, comprising forming two electrodes. 2. A method according to claim 1, further comprising: forming a metal thin film on the first main surface, which is sufficiently thick compared to a step between the control electrode structure and the surface of the semiconductor substrate on the first main surface, to be the first main electrode; 2. The method of manufacturing a semiconductor device according to claim 1, wherein the surface is polished mechanically or chemically to flatten the surface, and then the second principal surface is polished. 3. After forming a metal thin film serving as a first main electrode, a coating film sufficiently thicker than a step between the control electrode structure and the semiconductor substrate surface on the first main surface is formed on the first main surface. 2. The method according to claim 1, wherein the surface of the coating film is mechanically or chemically polished to flatten the surface, and then the second main surface is polished.
The manufacturing method of the semiconductor device described in the above. 4. The method according to claim 3, wherein a photoresist is used as the coating film. 5. The semiconductor device according to claim 1, wherein the second main surface of the semiconductor substrate is mechanically or chemically polished, and impurities are introduced into the surface layer, and then the second electrode is formed. 4
The method for manufacturing a vertical semiconductor device according to any one of the above. 6. A vertical semiconductor device having a first electrode and a control electrode structure on a first main surface of a semiconductor substrate and a second electrode on a second main surface, wherein the first electrode is a control electrode. A vertical semiconductor device extending on a structure and having a polished flat surface. 7. The vertical semiconductor device according to claim 6, having a control electrode structure composed of a metal-insulating film-semiconductor substrate (MOS). 8. The vertical semiconductor device according to claim 6, wherein the thickness of the semiconductor substrate is 150 μm or less.