JP2006024673A - Manufacturing method for semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a process in which the warp or the like of a semiconductor substrate caused by stress by an insulating film or the like deposited on a substrate surface is prevented and the cracking and breaking of the substrate are reduced when the rear of the substrate is polished and worked. <P>SOLUTION: A pnp bipolar transistor is formed on the p<SP>+</SP>-type silicon substrate 1, and an opening for a base-contact diffusion is formed to a silicon oxide film 6 on the silicon substrate 1. P (phosphorus) as an n-type impurity source is diffused at 920°C, and a base-contact diffusion region 5 is formed. A PSG film 7 as a passivation film is formed on the whole surface of the silicon substrate 1 by a CVD method, and the PSG film is fined by a heat treatment at 800°C. The silicon oxide film 6 is etched, and base and emitter contact windows 11 are formed. A metallic film 12 is evaporated and formed on the silicon substrate 1, a polishing is conducted from the rear of the substrate 1, and the substrate is thinned. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a semiconductor device capable of reducing processing cracks when a back surface is polished by grinding or the like in a process of forming a transistor on a semiconductor substrate.

  An example of a structure diagram of a conventional PNP transistor is shown in FIG. 3, and an explanatory diagram of the manufacturing process is shown in FIGS. 4 and 5 (see, for example, Patent Documents 1 and 2).

In FIG. 3, the PNP transistor is formed on a P ⁺ type silicon substrate 1, and includes a P ⁻ type epitaxial layer serving as a collector region 2, an N type diffusion layer serving as a base region 3, a P type diffusion layer serving as an emitter region 4, The base contact region 5 includes an N ⁺ -type diffusion layer, a silicon oxide film 6, a PSG passivation film 7, an emitter electrode 8, a base electrode 9, and a collector electrode 10.

  This PNP transistor is manufactured by the following process.

A P ⁻ type epitaxial layer to be the collector region 2 is formed on the P ⁺ type silicon substrate 1, and an N type diffusion layer to be the base region 3 is formed in the collector region 2. After the silicon oxide film 6 is formed on the silicon substrate 1, an emitter region forming opening is formed in a region on the base region 3 in the silicon oxide film 6.

A boron nitride plate serving as an emitter P-type impurity source is disposed in the vicinity of the silicon substrate 1 subjected to the above-described processing, and a high temperature treatment at 1050 ° C. is performed in an O ₂ / N ₂ atmosphere, so that the silicon substrate is opened from the opening. Boron is diffused into 1 to form a shallow emitter diffusion region 4 having a depth of about 2 μm. At this time, a part of the surface of the silicon oxide film 6 and a portion of the emitter diffusion region 4 where the substrate surface is exposed become the silicon nitride film 13 containing boron (FIG. 4A).

Next, the silicon substrate 1 is heat-treated at 1150 ° C. in an N ₂ atmosphere to form a deep emitter region 4 ′ having a depth of about 6 μm (FIG. 4B).

  An opening for base contact diffusion is formed in the silicon oxide film 6 on the silicon substrate 1, and P (phosphorus) of an N-type impurity source is diffused at 920 ° C. to form a base contact diffusion region 5 (FIG. 4C). ). A silicon oxide film (hereinafter referred to as a PSG film) 7 doped with P (phosphorus) serving as a passivation film is formed on the entire surface of the silicon substrate 1 by CVD, and the PSG film is densified by heat treatment at 800 ° C. (FIG. 5 (d)).

Next, a base and emitter contact window 11 is formed (FIG. 5E), and an emitter electrode 8 and a base electrode 9 are formed (FIG. 5F). Polishing is performed from the back surface of the P-type semiconductor substrate 1, and then the collector electrode 10 is formed on the back surface of the semiconductor substrate to complete the semiconductor substrate on which the PNP transistor is formed.
JP-A-53-123673 Japanese Patent Laid-Open No. Sho 62-154737

  When a transistor operates, it generates heat by itself and adversely affects its DC amplification characteristics and switching characteristics. In particular, in a power transistor, since it is desired that heat dissipation is high, it is necessary to make the semiconductor substrate on which the transistor is formed as thin as possible.

  However, as shown in FIG. 3, in order to make the semiconductor substrate on which the transistor is formed thin, the back surface of the semiconductor substrate is polished, but the semiconductor substrate is cracked due to distortion or deflection generated on the back surface of the semiconductor substrate during polishing. As a result, chipping occurs, the semiconductor substrate is damaged, and the yield and quality deteriorate.

  In order to solve the above problems, a method of manufacturing a semiconductor device according to the present invention includes a step of forming a metal film on the entire surface of a semiconductor substrate on which a semiconductor element is formed, and polishing a back surface of the semiconductor substrate covered with the metal film. And a step of thinning the semiconductor substrate.

  It is preferable that a step of patterning the metal film to form an electrode or a wiring of the semiconductor element is provided after the polishing step.

  An insulating layer or a metal layer different from the metal film is formed on the surface of the semiconductor substrate, and the stress applied to the semiconductor substrate by the insulating layer or the metal layer is relieved by forming the metal film. More preferably.

  In the present invention, by polishing the back surface of the semiconductor substrate in a state where the metal film used as the base and emitter electrodes of the transistor is deposited, distortion and deflection generated on the back surface of the semiconductor during polishing can be reduced. Breaking and chipping can be reduced, and a transistor with stable yield and quality can be formed.

  According to the present invention, even when the strength of the semiconductor substrate is reduced due to the back surface polishing, it is possible to prevent the substrate from being cracked or chipped and to improve the yield.

  FIGS. 1 and 2 are explanatory diagrams of the manufacturing process of the PNP transistor in the embodiment of the present invention.

After forming a P ⁻ type epitaxial layer to be the collector region 2 on the P ⁺ type silicon substrate 1 and an N type diffusion layer to be the base region 3 in the collector region 2, a silicon oxide film 6 is deposited. An opening for forming an emitter region is formed in the silicon oxide film 6 on the base region 3, and the silicon substrate 1 and a boron nitride plate serving as an emitter P-type impurity source are alternately arranged in a heat treatment furnace (not shown). Then, a silicon nitride film 13 containing boron and a shallow emitter diffusion region 4 having a depth of about 2 μm are formed on the surface of the substrate 1 by performing a high temperature treatment at 1050 ° C. in an O ₂ and N ₂ atmosphere (FIG. 1). (A)).

Subsequently, the silicon substrate 1 is subjected to a high-temperature treatment at 1150 ° C. in an N ₂ atmosphere to form a deep emitter region 4 ′ having a depth of about 6 μm (FIG. 1B).

  An opening for base contact diffusion is formed in the silicon oxide film 6 on the silicon substrate 1, and P (phosphorus) of an N-type impurity source is diffused at 920 ° C. to form a base contact diffusion region 5 (FIG. 1 (c) )).

  A PSG film 7 serving as a passivation film is formed on the entire surface of the silicon substrate 1 by CVD, and the PSG film is densified by heat treatment at 800 ° C. (FIG. 2D).

  Next, the silicon oxide film 6 is etched to form a base and emitter contact window 11 (FIG. 2E).

  A metal film 12 is deposited on the silicon substrate 1 and polished from the back surface of the substrate 1 to thin the substrate (FIG. 2 (f)).

  Thereafter, the metal film 12 is processed to form an emitter electrode 8 and a base electrode 9 on the surface of the silicon substrate 1, and a collector electrode 10 is formed on the back surface of the silicon substrate 1 to form a PNP transistor (FIG. 2 (g) )).

  According to the present embodiment, since the metal film is formed on the entire surface of the substrate, the stress applied to the substrate due to the steps up to that point, particularly the deposition and densification of the PSG film, can be relaxed. In this state, the backside polishing of the P-type silicon substrate 1 is performed, so that cracking and chipping of the substrate can be suppressed.

  This will be explained in a little more detail.

  A semiconductor element is formed by depositing various types of films on a semiconductor substrate and processing them. However, when the stress of the deposited film is applied to the substrate, the substrate is warped. When the substrate is sufficiently thick at several hundred μm, the amount of warpage due to film stress is small, but when the substrate is thinned to about 100 μm by performing backside polishing etc., the amount of warpage of the substrate increases and the mechanical strength of the substrate decreases greatly End up. If additional processing or conveyance of the substrate is performed in such a state, the impact causes the substrate to be cracked or chipped, resulting in a significant decrease in product yield.

  On the other hand, if the back surface polishing is performed with the total film stress formed on the substrate being small as in this embodiment, the warpage amount itself can be reduced even if the substrate is thin, and the substrate is cracked or chipped. Can be prevented. This greatly improves the product yield.

  Further, if the metal film is processed after the back surface polishing to form wirings and electrodes as in this embodiment, the process can be simplified and the cost can be reduced.

  Table 1 shows a comparison of the occurrence rate of cracks and chips in a semiconductor substrate according to the conventional method and the manufacturing method of the present invention.

  As can be seen from Table 1, according to the method of the present invention, it was found that both cracking and chipping of the substrate can be halved.

  In this embodiment, the case where the PNP transistor is formed has been described as an example. However, other semiconductor elements such as a diode or a MOS transistor may be formed.

Also, when WSi _x or W wiring is used as a wiring for connecting a transistor or the like, a tensile stress is strongly applied to the substrate, but if a film having a compressive stress such as Al is deposited and polished as it is, this embodiment There is an effect similar to the form.

  The method for manufacturing a semiconductor device of the present invention is useful as a method that can prevent cracking and chipping caused by backside polishing of a substrate and can be manufactured at low cost.

Manufacturing process explanatory drawing of the PNP transistor in embodiment of this invention Manufacturing process explanatory drawing of the PNP transistor in embodiment of this invention Cross-sectional structure of PNP transistor The figure which shows the manufacturing method of the conventional PNP transistor The figure which shows the manufacturing method of the conventional PNP transistor

Explanation of symbols

1 P ⁺ type silicon substrate 2 Collector region 3 Base region 4 Emitter region 4 'Deep emitter region 5 Base contact region 6 Silicon oxide film 7 PSG passivation film 8 Emitter electrode 9 Base electrode 10 Collector electrode 11 Contact window 12 Metal film

Claims (3)

Forming a metal film over the entire surface of the semiconductor substrate on which the semiconductor element is formed;
A method of manufacturing a semiconductor device, comprising: a step of polishing a back surface of the semiconductor substrate covered with the metal film to thin the semiconductor substrate. 2. The method for manufacturing a semiconductor device according to claim 1, further comprising a step of forming an electrode or a wiring of the semiconductor element by patterning the metal film after the polishing step. An insulating layer or a metal layer different from the metal film is formed on the surface of the semiconductor substrate,
3. The method of manufacturing a semiconductor device according to claim 1, wherein the stress applied to the semiconductor substrate by the insulating layer or the metal layer is relaxed by forming the metal film.

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