JPH0258329A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To wear the rear of a wafer uniformly by forming a voltage supply layer on the front face of the wafer, forming a low stress metal thereon, providing a strength in the wafer, flatly polishing the low stress metal layer, and then flatly polishing the rear of the wafer with the front face as a reference. CONSTITUTION:A voltage supply layer 7 is formed on a protective film 6 formed on the front face of a wafer 3. Then, a low stress metal 8 is formed, a polishing jig 5 is mounted, and the low stress alloy layer 8 on the front face of the wafer is polished with the rear of the wafer as a reference on a polishing base 4, thereby obtaining a flat face 9. With the next obtained flat low stress metal face 9 as a reference the rear 3 of the wafer is polished in a desired thickness, thereby obtaining a polished face 10. Then, the layer 8 on the front face of the wafer is wet processed, thereby obtaining a base metal 11 of a voltage supply layer 7 such as a Ti layer. Thereafter, the Ti layer 11 is removed by a dry etching method such as a reactive ion etching method 12, thereby obtaining a wafer having a desired substrate thickness.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for polishing the back surface of a wafer.

[Conventional technology]

Figure 2 is a cross-sectional view showing the conventional method of polishing the backside of a wafer.
In the figure 2, [11 is a glass plate for wafer bonding, +
21 is wax for gluing the wafer and the glass plate 111;
(3) is the wafer whose back side is being polished; (4) is the polishing table; (5) is the polishing table;
) is a polishing jig.

Next, the operation will be explained. First, the wafer (3) is attached to the glass plate 11) using wax (2) (the second
(See FIG. 1al) Next, it is attached to a polishing jig (5) and polished on a polishing table (4) (see FIG. 2, 1bl). next,
After polishing to a desired thickness, the sample is removed from the apparatus for the back surface processing step, the glass plate (1) is heated, the wax (2) is melted, and the wafer (3) is removed. Next, the wafer (3) is organically cleaned to completely remove the wax (2) remaining on the wafer surface, and the wafer (13) has a desired thickness.
get.

[Problem to be solved by the invention]

Conventional semiconductor device manufacturing methods are configured as described above, but when attaching a wafer to a glass plate with wax, polishing accuracy cannot be obtained due to the distribution of wax thickness and the speed of attaching the glass plate. There were issues such as the difficulty of automated processing since there were nine glass plates (VC).

This invention has been carefully designed to solve the above-mentioned problems, and aims to provide a method for obtaining substrate strength without using a glass plate or wax, and polishing the back surface of a wafer with good uniformity. .

[Friendly means of solving problems]

The polishing method according to the present invention forms a power supply layer on the wafer surface without using a glass plate or wax, and then forms a low-stress metal on the power supply layer using a pulse plating method to give the wafer strength and coat the low-stress metal on the wafer. Utilizing the flatness of the back surface, the low-stress metal layer on the front surface is polished flat, and then polished to a flat surface.The Ueno/back surface is then polished flat using the surface as a reference.

[Effect]

The continuous formation of a low stress metal on the wafer surface according to the second aspect of the present invention is designed to give the wafer strength, making it easier to handle the wafer, and allowing the wafer and back surface to be polished with high precision.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. No. [
In the figure, +31 is the wafer, (6) is the protective film formed on the surface, (7) is the friendly power supply layer formed on the protective film (6), (
The 8th one is formed by pulse plating and is a low-strength metal.

(9) is the surface of the polished A7'C wafer, αq is the back surface of the polished wafer, αυ is the nine T1 layer that appears after removing the upper power supply layer (7), and (6) is the reactivity of removing the Ti layer θυ. This is ion etching.

Next, the operation of this invention will be explained. First, the wafer (
The protective film (6) formed on the surface of 3), for example, Si
N or 5iOJ:, an @electrolayer (η, for example, Ti/Au is formed using spatter (see Fig. 1 fhl).
.

Next, a low conductive layer (low conductive layer) is formed on the power supply layer (2).
8) For example, pulse plating method? A low stress metal is used to form the entire structure (see FIG. 1). Next, the polishing jig (5)
The low stress alloy layer (8) on the wafer surface is placed on the polishing table (4) with the back surface of the wafer as a reference. Polished, flat surface (9)? (See Figure 1 1dl, tel). Next, obtain nine flat low stress metal surfaces (9) all criteria? Then, the back surface (3) of the wafer is polished to a desired thickness to obtain a polished surface GO (see FIG. 1 If l, igl).
. Next, a low stress metal layer (Au) on the surface of the evaporator
(8) Wet treatment, for example, immersion in a mixed solution of borosilicate and potassium, and removal to obtain a base metal αυ of the power supply layer (7), for example a Ti layer (see FIG. 1 fhl). Next, a dry etching method, for example, a reactive ion etching method (2
), the Ti layer θυ is removed, and a U/S having a desired substrate thickness is obtained (see FIG. 1 [i 1. lj l)].

2. In the above embodiments, only gallium arsenide wafers are explained, but the wafers may be Si, InP, AAA wafers, etc., and the same effects as in the above embodiments can be obtained.

〔Effect of the invention〕

As described above, according to the present invention, the wax used in the wafer bonding process is substituted with a low-stress metal by pulse plating fi:, which enables highly accurate polishing and improved yields. There is an effect.

[Brief explanation of the drawing]

1al to 1j) are side views of each step of a method for manufacturing a semiconductor device showing an embodiment of the present invention, and FIG. 2 1a1. l
Is BL the conventional polishing method for the back side of semiconductor wafers? FIG. In Figure 2, 11)...Glass plate, +21...Wax, (3)...Wafer, 14)...Polishing table, 15)
...polishing jig, (6)...protective film, (7)...I@
Electrical layer, (8)...Low stress metal, +01...Polished wafer surface, (10...Polished wafer backside,
0])...Ti layer which is the base metal of the power supply layer, o2...
Reactive ion etching. 2. In the figures, the same symbols indicate the same or equivalent parts.

Claims (1)

[Claims] A process of forming a sputtered layer (for example, a Ti/Au layer) on a protective film on the surface in the manufacturing process of a compound semiconductor, such as a gallium arsenide IC, and a plating method that allows a low-stress alloy to be applied to the sputtered layer to easily fill the recesses. , for example, a process in which the formed metal is polished using a flat surface on the backside of the wafer as a reference, and a process in which the backside of the wafer is precisely polished based on the flatly polished metal surface. A method for manufacturing a semiconductor device, comprising: