JPS63312645A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS63312645A
JPS63312645A JP14934887A JP14934887A JPS63312645A JP S63312645 A JPS63312645 A JP S63312645A JP 14934887 A JP14934887 A JP 14934887A JP 14934887 A JP14934887 A JP 14934887A JP S63312645 A JPS63312645 A JP S63312645A
Authority
JP
Japan
Prior art keywords
mesa
etching
dry etching
wet etching
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14934887A
Other languages
Japanese (ja)
Inventor
Hiroaki Mukohara
向原 広章
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP14934887A priority Critical patent/JPS63312645A/en
Publication of JPS63312645A publication Critical patent/JPS63312645A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To prevent a passivation film from being stepwisely cut by providing the step of finishing to form a smooth shape by etching the end of a step by using the step of accurately removing it except a mesa region by a dry etching method and a wet etching method. CONSTITUTION:A semiconductor substrate 1 is covered with a photoresist 2, and patterned to expose the substrate 1 in a window 2' state in a region for surrounding a mesa forming region. Thereafter, the substrate 1 is selectively etched by dry etching to form a mesa groove 3. Subsequent to the dry etching, a wet etching is conducted. The corners of a mesa groove 4 are rounded by the wet etching.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法、特に半導体装置のメサ
構造を形成する方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming a mesa structure of a semiconductor device.

〔従来の技術〕[Conventional technology]

従来、この種のメサ構造を形成する方法としては半導体
基板にフォトレジスト工程でメサを形成すべき領域を7
オトレジストの溝で囲むように7オトレジストを形成し
、しかるのち半導体基板のフォトレジストの溝に露出す
る部分をウェット法によりエツチングし、もってメサ構
造を形成していた。
Conventionally, the method for forming this type of mesa structure is to use a photoresist process to form seven areas on a semiconductor substrate.
Seven photoresists were formed so as to be surrounded by photoresist grooves, and then the portions of the semiconductor substrate exposed to the photoresist grooves were etched by a wet method, thereby forming a mesa structure.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

覆 上述した従来の方法は被原材として有機物質であるフォ
トレジストを使用している。このため、ウェットエツチ
ングをおこなう場合、フォトレジストがエッチャントに
対し十分な耐性を有していない。すなわち、はとんどの
エッチャントは発熱反応をするため、フォトレジストの
半導体基板との密着性も悪くなり、メサ溝が広くなった
りその形状がくずれたシして所望するメサ構造を得るこ
とが困難で6つな。
The conventional method described above uses photoresist, which is an organic material, as the substrate material. For this reason, when performing wet etching, the photoresist does not have sufficient resistance to the etchant. In other words, most etchants cause an exothermic reaction, which deteriorates the adhesion of the photoresist to the semiconductor substrate, making it difficult to obtain the desired mesa structure as the mesa groove becomes wider or its shape is distorted. That's six.

父上記欠点を解決する手段として各種ワックスは優れて
はいるが、溝を精度良く作ることができず、8度の点で
劣り、やはり所望の形状を得ることが困難でめった。
Although various waxes are excellent as a means of solving the above-mentioned drawbacks, they are difficult to form grooves with high precision and are inferior in terms of 8 degrees, making it difficult to obtain the desired shape.

上述し之従来技術の方法では耐邦品・耐熱又は精度が欠
点として存在するため特性不良歩留低下の要因となる。
The above-mentioned conventional methods have drawbacks such as durability, heat resistance, or accuracy, which causes poor characteristics and reduced yield.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の目的は上記欠点を除去し、メサ構造を高精度【
てかつその後の工程においても不具合が発生しない様器
てメサ構造の製造方法を提供することにある。
The purpose of the present invention is to eliminate the above drawbacks and improve the mesa structure with high precision.
It is an object of the present invention to provide a method for manufacturing a mesa structure in which problems do not occur even in subsequent steps.

すなわち、本発明によればドライエツチング法を用い、
所望するメサ領域以外を高精度(で除去する工程と、し
かるのちウェットエツチング法を用瑞 い、特に段部の減部をエツチングしてなめらかな形状に
仕上げる工程とを有している。本発明によれば、半導体
基板のメサ溝を作るためのエツチングをドライエツチン
グ法で実施する之め、エツチングマスク材として通常の
フォトレジストが使用でき、かつその後ウェットエツチ
ングで仕上げをおこなうため、メサ部の形状がなめらか
となりその後のパッシベーレ璽ン膜形成等に訃いては段
切れ等が防がれる。
That is, according to the present invention, using a dry etching method,
The process includes a process of removing areas other than the desired mesa area with high precision, and then a process of etching the reduced part of the stepped part in particular using a wet etching method to finish it into a smooth shape.The present invention According to the authors, since etching to create mesa grooves in semiconductor substrates is carried out by dry etching, ordinary photoresist can be used as the etching mask material, and since the finishing is done by wet etching afterwards, the shape of the mesa part can be easily adjusted. This makes the surface smooth and prevents breakage, etc. due to subsequent formation of a passibele film.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図(a)乃至(d)は本発明の一実施例の断面図で
あ!り(a)は完成された断面図を示す。まず、第1図
域を囲む領域に窓2I状(−半導体基板1を蕗出する。
FIGS. 1(a) to 1(d) are cross-sectional views of one embodiment of the present invention! (a) shows the completed cross-sectional view. First, a semiconductor substrate 1 is formed in the shape of a window 2I in an area surrounding the area shown in FIG.

しかるのち、ドライエツチングにより半導体基板1を選
択的にエツチングしてメサ溝3を作る(第1図(C))
。次に、第1図(d)に示すように、ドライエツチング
に連続してウェットエツチングを実施する。(第1図(
d))。このウェットエツチングによりメサ溝4の角部
は丸くなる。
After that, the semiconductor substrate 1 is selectively etched by dry etching to form a mesa groove 3 (FIG. 1(C)).
. Next, as shown in FIG. 1(d), wet etching is performed following dry etching. (Figure 1 (
d)). By this wet etching, the corners of the mesa groove 4 are rounded.

以上の工程を実施すること(Cより半導体基板はシャー
プなエツチング溝が形成されかつ形状がなめらかになる
By carrying out the above steps (C), sharp etching grooves are formed in the semiconductor substrate and the shape becomes smooth.

本発明の他の実施例によれば、第1図(b)に示すよう
に半導体基板1に所望のメタルマスク上させる。次にプ
ロテクトワックスを加熱し液状になったものをこのメタ
ルマスク上から基板に噴霧する。次にホットプレート(
200℃)上に基板を置きワックスを溶かし強局な“7
スク2とする。しかるのち第1図(C1に示すようにド
ライエツチングで半導体基板1をエツチングでる。この
ドライエツチングはシリコンの場合CF4等のガスで実
施する。
According to another embodiment of the present invention, a desired metal mask is placed on the semiconductor substrate 1, as shown in FIG. 1(b). Next, the protect wax is heated and turned into a liquid, which is then sprayed onto the substrate from above the metal mask. Next, the hot plate (
Place the board on top (200℃) and melt the wax using a strong
Let's call it 2. Thereafter, as shown in FIG. 1 (C1), the semiconductor substrate 1 is etched by dry etching. In the case of silicon, this dry etching is performed using a gas such as CF4.

ドライエツチングに連続し−〔ウェットエツチング(本
方法の場合は硝酸・ヨウ素・氷酢酸の混合液使用)をお
こない半導体基板1をエツチングし、エツチング溝4を
形成する。その後ワックスのマスク2をトリクレン等の
有機溶剤で除去し、第1図(a)のようにメサ構造を形
成する。
Following dry etching, wet etching (using a mixed solution of nitric acid, iodine and glacial acetic acid in this method) is performed to etch the semiconductor substrate 1 and form etching grooves 4. Thereafter, the wax mask 2 is removed using an organic solvent such as trichlene to form a mesa structure as shown in FIG. 1(a).

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明はメサ領域を高精度にかつ
形状をなめらかに形成することにより歩留向上さらに電
層不良の低減を可能ならしめる効果がある。
As described above, the present invention has the effect of improving yield and reducing electrical layer defects by forming a mesa region with high precision and a smooth shape.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)乃至(d)は本発明の実施例による製造方
法を説明するために示した各製造工程の断面図である。 1・・・・・・半導体基板、2・・・・・・フォトレジ
ス1−orプロテクトワックス 2+・・・・・・フォ
トレジストの選択窓、3・・・・・・メサ溝、4・・・
・・・ウェットエツチング後のメサ溝。 。
FIGS. 1(a) to 1(d) are cross-sectional views of each manufacturing process shown to explain a manufacturing method according to an embodiment of the present invention. 1...Semiconductor substrate, 2...Photoresist 1-or protection wax 2+...Photoresist selection window, 3...Mesa groove, 4...・
...Mesa groove after wet etching. .

Claims (1)

【特許請求の範囲】[Claims] 半導体基板にメサ溝部をドライエッチング法で形成し、
その後ウェット法を用い仕上げることを特徴とする半導
体装置の製造方法。
A mesa groove is formed on a semiconductor substrate using a dry etching method,
1. A method for manufacturing a semiconductor device, characterized in that finishing is then performed using a wet method.
JP14934887A 1987-06-15 1987-06-15 Manufacture of semiconductor device Pending JPS63312645A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14934887A JPS63312645A (en) 1987-06-15 1987-06-15 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14934887A JPS63312645A (en) 1987-06-15 1987-06-15 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS63312645A true JPS63312645A (en) 1988-12-21

Family

ID=15473156

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14934887A Pending JPS63312645A (en) 1987-06-15 1987-06-15 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS63312645A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100350589C (en) * 2005-01-18 2007-11-21 旺宏电子股份有限公司 Shallow trench isolation method forming round corners by cleaning
JP2014192500A (en) * 2013-03-28 2014-10-06 Shindengen Electric Mfg Co Ltd Method of manufacturing mesa type semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100350589C (en) * 2005-01-18 2007-11-21 旺宏电子股份有限公司 Shallow trench isolation method forming round corners by cleaning
JP2014192500A (en) * 2013-03-28 2014-10-06 Shindengen Electric Mfg Co Ltd Method of manufacturing mesa type semiconductor device

Similar Documents

Publication Publication Date Title
JPS63312645A (en) Manufacture of semiconductor device
JPS5914889B2 (en) Manufacturing method of semiconductor device
US3953266A (en) Process for fabricating a semiconductor device
JPS5910059B2 (en) Manufacturing method for semiconductor devices
JPS6251228A (en) Manufacture of gallium-arsenide monolithic microwave integrated circuit
JPS63117428A (en) Manufacture of semiconductor device
JP3018345B2 (en) Method for manufacturing semiconductor device
JPS63104339A (en) Manufacture of semiconductor device
JPH0220043A (en) Manufacture of semiconductor device
JPS5845810B2 (en) Pattern formation method
KR960013140B1 (en) Fabricating method of semiconductor device
JPH0194623A (en) Manufacture of semiconductor device with multilayer interconnection
JPH0497523A (en) Manufacture of semiconductor device
JPH08186115A (en) Method for metal film forming
JP2001068545A (en) Manufacture of semiconductor device
JPH01108726A (en) Manufacture of semiconductor device
JPS61288426A (en) Taper etching method for aluminum film
JPS6279625A (en) Manufacture of semiconductor device
JPS60218848A (en) Method of etching crystal substrate
JPS61113237A (en) Method for etching polysilicon
JPS6329950A (en) Forming method for metallic wiring pattern of semiconductor device
JPH04179124A (en) Manufacture of semiconductor device
JPH0638408B2 (en) Method for manufacturing semiconductor device
JPS6127638A (en) Thin film processing method
JPS5893330A (en) Manufacture of semiconductor device