JPS6329950A - Forming method for metallic wiring pattern of semiconductor device - Google Patents

Forming method for metallic wiring pattern of semiconductor device

Info

Publication number
JPS6329950A
JPS6329950A JP17447986A JP17447986A JPS6329950A JP S6329950 A JPS6329950 A JP S6329950A JP 17447986 A JP17447986 A JP 17447986A JP 17447986 A JP17447986 A JP 17447986A JP S6329950 A JPS6329950 A JP S6329950A
Authority
JP
Japan
Prior art keywords
temperature
etching
etchant
wiring pattern
etching solution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17447986A
Other languages
Japanese (ja)
Inventor
Takaaki Kobayashi
孝彰 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP17447986A priority Critical patent/JPS6329950A/en
Publication of JPS6329950A publication Critical patent/JPS6329950A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To reduce the depth of side etching from the boundary of the outer edge of a photo-resist mask, and to form a metallic wiring having high precision by dividing the temperature of an etchant into high and low values, parting a process into two stages and etching a metallic film. CONSTITUTION:The temperature of an etchant is divided into high and low values, a process is parted into two stages, and the upper layer of a metallic film 2 is etched only by a proper quantity by the etchant held at the high temperature as a first process (a, b). The residual metallic film 2 is all removed by the etchant kept at the low temperature as a second process (c, d). The metallic film 2 consists of an aluminum film, the etchant mainly comprises phosphoric acid, and a range of approximately 50-60 deg. is used as the high temperature and a range of approximately 20-30 deg. as the low temperature. Accordingly, the depth of side etching 4 from the boundary of the outer edge of a photo-resist mask can be reduced, thus shaping a metallic wiring having high precision. Several dozen wafers can be treated simultaneously, thus acquiring high productive efficiency.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置の製造方法に係り、特に金属配線
パターンの形成に関する。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to the formation of a metal wiring pattern.

〔従来の技術〕[Conventional technology]

従来、半導体装置の金属配線パターン形底法は、半導体
基板上に被層され之金@金、ホトレシストハターン等を
マスクに用いて、ある一定の?&温に保持したエツチン
グ液に半導体基板全浸漬し、1[K丁べての金PAm全
エツチングすることにより金属配線パターンを形成して
いた。
Conventionally, in the metal wiring pattern forming method for semiconductor devices, a metal wiring pattern is coated on a semiconductor substrate using a mask such as gold or photoresist pattern. A metal wiring pattern was formed by completely immersing the semiconductor substrate in an etching solution kept at a temperature of 100°C and etching all of the gold PAm.

〔発明が解決しようとする間、照点〕[The point of view while the invention is trying to solve]

上述した従来の金属配線パターン形底法は、比較的高温
に保たれたエツチング族で1度シ′ζ丁べての金my−
+エツチングするため、レジストと金属膜表面との@層
性が劣化しサイドエッチが発生しゃすくな)パターニン
グ梢芙が著しく低下するとともに化学反応によシ発生す
る気泡寺にニジパターン端部に不整が生じ配#断崗をま
ねく一因ともなる欠点がめった。
In the conventional metal wiring pattern bottom method described above, the entire metal wiring pattern is etched once in an etching process kept at a relatively high temperature.
+Due to etching, the layer quality between the resist and the metal film surface deteriorates and side etching is likely to occur.) Patterning ridges are significantly reduced, and irregularities occur at the edges of the pattern due to bubbles caused by chemical reactions. There were very few defects that could lead to failure.

本発明の目的は、上記の欠点を除去して、工ツチングの
方法を改良した金属配線パターン形成法を提供すること
にある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a metal wiring pattern forming method that eliminates the above-mentioned drawbacks and improves the processing method.

〔問題を解決するための手段〕[Means to solve the problem]

不発明においてはエツチング液の温度を高低に分け、工
程を2段階とし、第1工程として高温に保持し之エツチ
ング液によシ金S換の上層全適蟲量エツチングし、第2
工程として低温に保持したエツチング液に工υ残りの金
属膜をすべて除去するようにしたものである。
In the present invention, the temperature of the etching liquid is divided into high and low, and the process is performed in two stages.The first step is to maintain the temperature at a high temperature and etch the entire upper layer of the etching liquid in an appropriate amount.
The process uses an etching solution kept at a low temperature to remove all remaining metal film.

〔実 施 例〕〔Example〕

以下、図面を参照して、本発明の一実施例につき説明す
る。第1図は、アルミニウム配線形成に不発明全適用し
た@曾の断面図ケ工程順に示したものである。先ず、第
1図(、)に示す:うに、素子を形成した半導体基板1
上に全面Vこ蒸着法ま之はスパッタ法でアルミニウム換
2全形成しfc故、ホトレジスト漱全塗布し、パターニ
ングしてホトレジストマスク3を形成する。
Hereinafter, one embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a sectional view showing the process order of the invention fully applied to aluminum wiring formation. First, as shown in Figure 1 (,): a semiconductor substrate 1 on which elements are formed;
On the entire surface, an aluminum layer 2 is formed using a sputtering method, and then a photoresist is completely coated and patterned to form a photoresist mask 3.

矢に第1工程としてほぼ50゜〜60°に保たれたりん
酸?基本VcA曾しtアルミニウムエツチング漱に、半
導体基板1全浸漬し、ホトレジストマスク6によジ、ア
ルミニウム膜2金所定の厚さだけ上層部分のみエツチン
グする。第1図(b)がエツチング状態を示すもので、
ホトレジストマスク3とアルミニウム膜2との外縁境界
より、エツチングが進み、図示のようにサイドエツチン
グ部4が生ずる。これに対し従来の方法では、−度に金
属膜をエツチングするので、同一の膜厚のアルミニウム
膜に対し、同一条件でエツチングすると第2図に示すよ
うにサイドエツチング部イは深く形成される。エツチン
グ液温が高温であると、ホトレジストマスク3とアルミ
ニウム族2との密着力が低下し、エツチングが等1的に
進行するので、サイドエツチング部4,4′の深さく横
方向の寸法)はエツチングされた膜厚程区になる。した
がって第2図のサイドエツチング部4′は極めて深くな
るが5本発明ではサイドエツチング部4は浅くとどめる
ことができる。
Phosphoric acid kept at approximately 50° to 60° as the first step to the arrow? The entire semiconductor substrate 1 is immersed in basic VcA t aluminum etching solution, the photoresist mask 6 is used, and only the upper layer of the aluminum film 2 is etched to a predetermined thickness. Figure 1(b) shows the etching state.
Etching progresses from the outer edge boundary between the photoresist mask 3 and the aluminum film 2, and side etching portions 4 are formed as shown in the figure. On the other hand, in the conventional method, the metal film is etched one step at a time, so when an aluminum film of the same thickness is etched under the same conditions, the side etched portions A are formed deeply as shown in FIG. If the temperature of the etching solution is high, the adhesion between the photoresist mask 3 and the aluminum group 2 will decrease, and the etching will progress uniformly, so the depth and lateral dimensions of the side etched portions 4 and 4' will be reduced. The thickness of the etched film varies. Therefore, the side etching portion 4' in FIG. 2 is extremely deep, but in the present invention, the side etching portion 4 can be kept shallow.

次に第2工程として、液温をほぼ20゜〜30’Cにな
し、同一エツチング液に浸漬し、第1図(c)に示すよ
うにホトレジストマスク3で保護され九領域をのぞきす
べてアルミニウム膜2を除去し、金属配線5t−形成す
る。このときは、エツチング液が低温であるため、ホト
レジストマスク3とアルミニウム2との密着力が低下せ
ず、サイドエツチングの進行は少なく、サイドエツチン
グ部4(1)の深さはサイドエツチング部4の深さより
僅かに大きくなるだけである。
Next, in the second step, the solution temperature is set to approximately 20° to 30'C, the etching solution is immersed in the same etching solution, and as shown in FIG. 2 is removed and metal wiring 5t- is formed. At this time, since the etching solution is at a low temperature, the adhesion between the photoresist mask 3 and the aluminum 2 does not deteriorate, the progress of side etching is small, and the depth of the side etched portion 4 (1) is reduced to that of the side etched portion 4. It is only slightly larger than the depth.

エツチング終了後、第1図(d)に示すようにホトレジ
ストマスク3を通常の方法で除去する。
After etching is completed, the photoresist mask 3 is removed by a conventional method as shown in FIG. 1(d).

〔発明の効果〕〔Effect of the invention〕

以上、説明し念ようンこ、本発明VCよれはホトレジス
トマスクの外脈境界からのサイドエツチングの深さが小
さくできるので、梢度の良い金稽配線全形成することが
できる。従来の工程では、1キヤリアあた9ウ工−ハ枚
数を大きくすると歩留が急激におちるので枚数を減小し
てい乏が、本発明に1少、数10枚のクエーハと同時に
処理することができ、高い生産効率が得られる。
As explained above, in the VC twist of the present invention, the depth of side etching from the boundary of the outer vein of the photoresist mask can be reduced, so that the entire metal wiring can be formed with a good degree of edge. In the conventional process, 9 wafers are processed per carrier.If the number of wafers is increased, the yield drops rapidly, so the number of wafers is reduced, but in the present invention, it is possible to process at least one or several dozen wafers at the same time. can be achieved, resulting in high production efficiency.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一笑施し1jの工程金示す断面図、第
2図は比較のための従来例の断面図でおる。 1・・・半導体基板   2・・・アルミニウム膜、6
・・・ホトレジストマスク%  4,4(1λ4′・・
・サイドエツチング部、5・・・金属配線。
FIG. 1 is a cross-sectional view showing the process of the present invention, and FIG. 2 is a cross-sectional view of a conventional example for comparison. 1... Semiconductor substrate 2... Aluminum film, 6
... Photoresist mask% 4,4 (1λ4'...
・Side etching part, 5...metal wiring.

Claims (2)

【特許請求の範囲】[Claims] (1)ホトレジストをマスクとしてエッチング液によつ
て金属膜をパターニングし、配線形成を行なう工程にお
いて、エッチング液の温度を高低に分け、工程に2段階
とし、第1工程として高温に保持したエッチング液によ
り金属膜の上層を適当量エッチングし、第2工程として
低温に保持したエッチング液により残りの金属膜をすべ
て除去することを特徴とする半導体装置の金属配線パタ
ーン形成法。
(1) In the process of patterning a metal film with an etching solution using a photoresist as a mask to form wiring, the temperature of the etching solution is divided into high and low temperatures, and the process is divided into two stages.The first step is the etching solution kept at a high temperature. A method for forming a metal wiring pattern for a semiconductor device, characterized in that the upper layer of the metal film is etched by an appropriate amount by etching, and as a second step, the remaining metal film is completely removed using an etching solution kept at a low temperature.
(2)前記第1項における、金属膜がアルミニウム膜で
あつて、エッチング液はりん酸を主成分とし、高温とし
てほぼ50゜〜60゜、低温としてほぼ20゜〜30゜
の範囲としたものであることを特徴とする特許請求の範
囲第1項記載の金属配線パターン形成法。
(2) In the above item 1, the metal film is an aluminum film, the etching solution is mainly composed of phosphoric acid, and the temperature is approximately 50° to 60° as a high temperature and approximately 20° to 30° as a low temperature. A metal wiring pattern forming method according to claim 1, characterized in that:
JP17447986A 1986-07-23 1986-07-23 Forming method for metallic wiring pattern of semiconductor device Pending JPS6329950A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17447986A JPS6329950A (en) 1986-07-23 1986-07-23 Forming method for metallic wiring pattern of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17447986A JPS6329950A (en) 1986-07-23 1986-07-23 Forming method for metallic wiring pattern of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6329950A true JPS6329950A (en) 1988-02-08

Family

ID=15979199

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17447986A Pending JPS6329950A (en) 1986-07-23 1986-07-23 Forming method for metallic wiring pattern of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6329950A (en)

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