JPS5823437A - Impurity introduction method in semiconductor device - Google Patents
Impurity introduction method in semiconductor deviceInfo
- Publication number
- JPS5823437A JPS5823437A JP12322281A JP12322281A JPS5823437A JP S5823437 A JPS5823437 A JP S5823437A JP 12322281 A JP12322281 A JP 12322281A JP 12322281 A JP12322281 A JP 12322281A JP S5823437 A JPS5823437 A JP S5823437A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- drive
- impurity
- diffusion
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 31
- 239000012535 impurity Substances 0.000 title claims abstract description 28
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 238000009792 diffusion process Methods 0.000 abstract description 17
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052796 boron Inorganic materials 0.000 abstract description 4
- 238000005530 etching Methods 0.000 abstract description 3
- 239000012298 atmosphere Substances 0.000 abstract description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 2
- 238000010438 heat treatment Methods 0.000 abstract description 2
- 229910052760 oxygen Inorganic materials 0.000 abstract description 2
- 239000001301 oxygen Substances 0.000 abstract description 2
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 239000002184 metal Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000008267 milk Substances 0.000 description 1
- 210000004080 milk Anatomy 0.000 description 1
- 235000013336 milk Nutrition 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
- H01L21/2251—Diffusion into or out of group IV semiconductors
- H01L21/2252—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体装置における不純物導入方法に関し、特
に２ステツプ拡散法による不純物導入方法に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for introducing impurities into a semiconductor device, and particularly to a method for introducing impurities by a two-step diffusion method.
いわゆる２ステツプ拡散による不純物導入法は第１図Ｋ
ｌ 、 （Ｂ）に示す如き方法である。すなわち、先ず
半導体基板ｌの一主面上に不純物源となるべき不純物２
を選択的に付着導入しくプレデポジ、ノド）て体）に示
す如き構造とする。尚、３は選択拡散のための不純物拡
散用マスクである酸化膜を示す。次に、付着した不純物
２を更に深く基板１内に再分布させるべくいわゆるドラ
イブイン工程が行われて（Ｂ）に示す如き構造となり、
所望の濃度を有する不純物領域２′が形成されることに
なる。The impurity introduction method by so-called two-step diffusion is shown in Figure 1K.
This is the method shown in (B). That is, first, an impurity 2 to be an impurity source is placed on one main surface of the semiconductor substrate l.
In order to selectively adhere and introduce the material, a pre-deposited structure is formed as shown in the figure. Note that 3 indicates an oxide film which is an impurity diffusion mask for selective diffusion. Next, a so-called drive-in process is performed to redistribute the attached impurities 2 deeper into the substrate 1, resulting in a structure as shown in (B).
An impurity region 2' having a desired concentration is formed.
このドライブイン工程においては、図（Ｂ）に示す如く
薄い酸化膜３′が形成されることになり、結果として半
導体基板１０表面における酸化膜の膜厚に差を生じて段
差の原因となる。よって酸化膜３．３′上に金属配線層
４を付着する場合には、当該段差部において断線の危険
が生じて歩留りの著しい低下を招来している。In this drive-in process, a thin oxide film 3' is formed as shown in Figure (B), resulting in a difference in the thickness of the oxide film on the surface of the semiconductor substrate 10, causing a step. Therefore, when the metal wiring layer 4 is deposited on the oxide film 3.3', there is a risk of wire breakage at the stepped portion, resulting in a significant decrease in yield.
本発明の目的は酸化膜の段差をなくして金属配線層の断
線の危険をなくし歩留りの向上を図るようにした２ステ
ツプ拡散法による不純物導入方法を提供することである
。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for introducing impurities using a two-step diffusion method, which eliminates the step difference in the oxide film, eliminates the risk of disconnection in the metal wiring layer, and improves the yield.
本発明による半導体装置の不純物導入方法は、２ステツ
プ拡散法におけるドライブ工程を少くとも２回の工程に
分離し、そのうち最初の工程を除く残余の工程における
少くとも１回はその前工程において生じた半導体基板表
面の酸化膜を全て除去するようにしたことを特徴として
いる。In the method for introducing impurities into a semiconductor device according to the present invention, the drive process in the two-step diffusion method is separated into at least two processes, and at least one of the remaining processes excluding the first process occurs in the preceding process. The feature is that all the oxide film on the surface of the semiconductor substrate is removed.
以下に図面によシ本発明を説明する。The present invention will be explained below with reference to the drawings.
第２図は本発明の詳細な説明する工程順の各断面図であ
り、２ステツプ拡散におけるドライブイン工程を２回に
分けて行う場合のレリである。先ず、体）に示すように
半導体基板１の一主面上に選択的に開口を穿った拡散用
マスクとしての酸化膜３を被着形成し、例えば不純物源
となるボロンを１×１０ＺｃｒＩなる濃度で付着導入す
る。この時の拡散温度は１，１００℃である。こうして
ボロンの不純物層２が形成されていわゆるプレデポジシ
ョン工程がなされる。次に、第１回目の再分布のための
ドライブイン工程が、１，１５０’Ｃのドライ酸素雰囲
気中で約１００分間なされ、やや深い不純物の拡散が行
われて、（Ｂ）に示す構造となる。７がこの第１回目の
ドライブイン工程にょシ形成された不純物領域であシ、
３′は同じくこのドライブイン工程によシ生じた酸化膜
である。FIG. 2 is a cross-sectional view of the process sequence for explaining the present invention in detail, and shows a case where the drive-in process in two-step diffusion is performed in two steps. First, as shown in Figure 1, an oxide film 3 as a diffusion mask with selective openings is deposited on one main surface of the semiconductor substrate 1, and boron, which will serve as an impurity source, is deposited at a concentration of 1 x 10 ZcrI. Introduce the adhesive. The diffusion temperature at this time is 1,100°C. In this way, a boron impurity layer 2 is formed and a so-called pre-deposition process is performed. Next, a first drive-in process for redistribution is performed for about 100 minutes in a dry oxygen atmosphere at 1,150'C to perform a somewhat deep diffusion of impurities, resulting in the structure shown in (B). Become. 7 is the impurity region formed in this first drive-in process,
3' is an oxide film also produced by this drive-in process.
第１回目のドライブイン工程においては、拡散マスクで
ある酸化膜３の全面エツチングによる除去は行わない。In the first drive-in step, the entire surface of the oxide film 3 serving as a diffusion mask is not removed by etching.
これは、この時点におけるボロン不・細物濃度が高いた
めに不純物の不要な拡散が生じて基板表面がＰ型になる
のを、当該酸化膜３により防止するためである。This is because the oxide film 3 prevents the substrate surface from becoming P-type due to unnecessary diffusion of impurities due to the high concentration of boron impurities at this point.
次に、第２回目のドライブイン工程に入るわけであるが
、この工程前に（Ｃ）に示すようにすべての酸化膜３．
３”ｉエツチングして除去し、しかる後に１，１５０℃
の水蒸気中で加分間のドライブイン処理が行われ所望の
深さを有する不純物領域２が形成される。ｒはこの第２
回目のドライブインによる熱処理によって生じた酸化膜
であり、４は金属配線層を示す。Next, the second drive-in process begins, but before this process, all the oxide films 3.
3"i etching and removal, then 1,150℃
A drive-in process for addition is performed in water vapor to form impurity regions 2 having a desired depth. r is this second
This is an oxide film produced by the second drive-in heat treatment, and 4 indicates a metal wiring layer.
こうすることによシ、基板表面の配化膜の断差をなくす
ことが可能となってその上に被着される金属層の断線は
生じなくなる。尚、上記においては、ドライブイン工程
を２回に分けて第２回目のドライブイン工程前に生じた
酸化膜をすべそ除去するようにしたが、３回以上に分け
て第２回目以後のドライブイン工程における少くとも１
回はその前工程において生じた基板表面の酸化膜を全て
除去するようにしてもよい。By doing so, it becomes possible to eliminate the difference in the alignment film on the surface of the substrate, and the metal layer deposited thereon will not be disconnected. In the above, the drive-in process was divided into two steps to remove the oxide film formed before the second drive-in process, but the drive-in process after the second drive-in process was divided into three or more steps. At least 1 in the in-process
In this step, the oxide film formed on the surface of the substrate in the previous step may be completely removed.
叙上のように、本発明によれば２ステツプ拡散法におけ
る半導体基板表面における酸化膜の段差を極力なくすこ
とができるので、配線の断線による歩留りの低下を防止
することが可能となる。As described above, according to the present invention, it is possible to eliminate as much as possible the level difference in the oxide film on the surface of the semiconductor substrate in the two-step diffusion method, thereby making it possible to prevent a decrease in yield due to disconnection of wiring.
第１図は従来の２ステツプ拡散法を示す図、第２図は本
発明の実施例の製造工程順の各断面図である。
主要部分の符号の説明
１・・・・・・・・・半導体基板
２．２’、２“・・・・・・・・・不純物層３．３’、
！・・・・・・・・・酸化膜出願人 バイオラア株式
会社
代理人 弁理士 藤 村 元 産
乳／図
観２図FIG. 1 is a diagram showing a conventional two-step diffusion method, and FIG. 2 is a cross-sectional view of the manufacturing process according to an embodiment of the present invention. Explanation of symbols of main parts 1... Semiconductor substrate 2.2', 2''... Impurity layer 3.3',
!・・・・・・・・・Oxide film applicant Biolaa Co., Ltd. Agent Patent attorney Hajime Fujimura Milk production/Illustration 2
Claims (1)
の半導体基板内へ前記不純物の再分布をなすようにした
不純物導入方法であって、前記不純物の再分布のための
ドライブイン工程を少くとも２回の工程に分離し、その
うち最初の工程を除く残余の工程における少くとも１回
はその前工程において生じた半導体基板表面の酸化膜を
全て除去するようにしたことを特徴とする不純物導入方
法。An impurity introduction method that selectively adheres and introduces impurities onto one main surface of a semiconductor substrate and then redistributes the impurities into the semiconductor substrate, the method comprising a drive-in step for redistributing the impurities. An impurity that is separated into at least two steps, in which at least one of the remaining steps excluding the first step removes all the oxide film on the surface of the semiconductor substrate formed in the previous step. How to introduce it.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12322281A JPS5823437A (en) | 1981-08-06 | 1981-08-06 | Impurity introduction method in semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12322281A JPS5823437A (en) | 1981-08-06 | 1981-08-06 | Impurity introduction method in semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5823437A true JPS5823437A (en) | 1983-02-12 |
Family
ID=14855219
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12322281A Pending JPS5823437A (en) | 1981-08-06 | 1981-08-06 | Impurity introduction method in semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5823437A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5465710A (en) * | 1977-11-05 | 1979-05-26 | Dai Ichi Kogyo Seiyaku Co Ltd | Additive for mixture of finely pulverized coal and oil |
| EP0628213A1 (en) * | 1992-02-25 | 1994-12-14 | Ag Associates, Inc. | Gas phase doping of semiconductor material in a cold-wall radiantly heated reactor under reduced pressure |
-
1981
- 1981-08-06 JP JP12322281A patent/JPS5823437A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5465710A (en) * | 1977-11-05 | 1979-05-26 | Dai Ichi Kogyo Seiyaku Co Ltd | Additive for mixture of finely pulverized coal and oil |
| JPS59548B2 (en) * | 1977-11-05 | 1984-01-07 | 第一工業製薬株式会社 | Additive for pulverized coal-oil mixture |
| EP0628213A1 (en) * | 1992-02-25 | 1994-12-14 | Ag Associates, Inc. | Gas phase doping of semiconductor material in a cold-wall radiantly heated reactor under reduced pressure |
| EP0628213A4 (en) * | 1992-02-25 | 1997-02-19 | Processing Technology Inc D B | Gas phase doping of semiconductor material in a cold-wall radiantly heated reactor under reduced pressure. |
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