JPS5925220A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5925220A
JPS5925220A JP13530582A JP13530582A JPS5925220A JP S5925220 A JPS5925220 A JP S5925220A JP 13530582 A JP13530582 A JP 13530582A JP 13530582 A JP13530582 A JP 13530582A JP S5925220 A JPS5925220 A JP S5925220A
Authority
JP
Japan
Prior art keywords
platinum
titanium
silicon nitride
film
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13530582A
Other languages
Japanese (ja)
Inventor
Kenji Oka
健次 岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP13530582A priority Critical patent/JPS5925220A/en
Publication of JPS5925220A publication Critical patent/JPS5925220A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To prevent the breakage of wafers as well as to increase the number of processed wafers by a method wherein a silicon nitride film and the like is used as the material to be provided below a titanium and platinum electrode for selective exforiation, and the titanium and platinum located on the upper layer are removed simultaneously when an etching is performed on them. CONSTITUTION:A base 2 is formed by diffusing p type impurities on a semiconductor substrate 1 containing N type impurities. An emitter 3 is obtained by diffusing N type impurities in the base 2. Subsequently, a silicon oxide film 4 is formed, and a contact window to be used to lead out an electrode is formed. Then, platinum is attached to the surface by vapor-deposition, and after an alloy layer 5 of silicon and platinum has been formed by heating, the platinum is removed by aqua regia. Then, a silicon nitride film 6 is grown on the surface, an etching is performed on the desired region using a photoresist, and titanium 7 and platinum 8 are formed on the surface by performing a sputtering method. Then, the titanium and platinum on the fiom are removed simultaneously by performing an etching on the film 6 using phosphoric acid of high temperature. Subsequently, gold-plating 9 is performed on the necessary region.

Description

【発明の詳細な説明】 本発明は表面(て多層電極を有する半導体装置の製造方
法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device having multilayer electrodes on its surface.

半導体基板の表面の電極として金を用いるいわゆる金電
極4・7造の半導体装I〃は高信頼度を有する半導体装
置として各用途に使用されている。これは金の持ってい
る腐食しない性質を利用したものである。ここで従来の
金電極構造の製造方法全説明する。
A so-called gold electrode 4/7 semiconductor device I in which gold is used as an electrode on the surface of a semiconductor substrate is used for various purposes as a highly reliable semiconductor device. This takes advantage of gold's non-corrosive properties. Here, the entire method for manufacturing a conventional gold electrode structure will be explained.

まず、半導体基板の所望の領域へ動作層を作るための不
純物の拡散を行ない、その後基板表面にシリコン酸化膜
を形成する。酸化膜の所望領域全エツチングにて取り去
った後、白金蒸Nt行ない、高温処理にてシリコン白金
合金層(白金シリサイド層)全形成させる。その後白金
を王水等で剥1’i(Cし、フォトレジスト(i’ R
,) i次に形成するチタン、白金領域以外の領域に形
成し、全面にチタン9白金をスパッタ法にて形成する。
First, impurities are diffused into a desired region of a semiconductor substrate to form an active layer, and then a silicon oxide film is formed on the surface of the substrate. After removing the entire desired region of the oxide film by etching, platinum evaporation is performed and a silicon-platinum alloy layer (platinum silicide layer) is completely formed by high-temperature treatment. After that, the platinum was peeled off with aqua regia, etc., and the photoresist (i'R) was applied.
,) Next, titanium and platinum are formed in areas other than the titanium and platinum areas, and titanium and platinum are formed on the entire surface by sputtering.

その後PRを剥離すればP几上のチタン、白金は同時に
除去され所望の領域にのみノシ&択的にチタン、白金電
極全形成できる。その後、白金上に金メッキ全行えば、
所望の金電極構造を得ることができる。このように例え
ば、金電極を必要とする半導体装置では必ず多層金属電
極構造としなければならなかった。
If the PR is then peeled off, the titanium and platinum on the P layer are removed at the same time, allowing the entire titanium and platinum electrodes to be selectively formed only in desired areas. After that, if you do all the gold plating on the platinum,
A desired gold electrode structure can be obtained. Thus, for example, a semiconductor device requiring a gold electrode always has to have a multilayer metal electrode structure.

ところが従来の方法で行なうと、チタン、白金スバツタ
工程でウニバスの割れが多く、また1回の処理での処理
枚数も少プ【いというり(点があった。
However, when using the conventional method, there were many cracks in the sea urchins during the titanium and platinum splicing process, and the number of sheets processed in one process was small.

この:9すれバ1囚はブータン、白金スパッタ時にウェ
ハースの温度上昇を防ぐために水冷治具にウェハースを
締め付けなければならないためである。一方、ウェハー
スの温度上昇金防ぐ必要性はチタン、白金下に設けら1
しているスバ、り1’ Itが高ρIAによ−り変質し
、その結果剥離不11目になるという重大な事態金もた
らすからでちる。l虻って、従来IJ ttを使用して
多層糖、極を形成する限り上記の欠点は避けられなかっ
た。
The reason for this: 9-1 strainer is that the wafer must be tightened in a water-cooling jig to prevent the wafer from rising in temperature during sputtering with Bhutan and platinum. On the other hand, it is necessary to prevent the temperature rise of the wafer due to the need to prevent titanium and platinum from increasing.
This is because the quality of the applied substrate is altered by the high ρIA, resulting in a serious situation where it becomes difficult to peel. However, the above drawbacks were unavoidable as long as IJ tt was used to form multilayer sugar electrodes.

不発明は冷)、11処理を必要としない多層電極の形成
方法を提(31:jろこと金目的とし、ウェハース割れ
全防ぎ処理枚数を増すことができるという効果w ;:
iき川すもので、不発明では下層金j1鳴(19すえば
、チタン。白金)を<A’l l’filiするため(
で用いていた1) ItここでΔ発明のて〜’! Ml
i Hlとしてシリコントランジスタを例に挙げ以下に
説明する。第1図はその断面図でN型不純IiI/Jを
含む仝16導体基板1にPハリ不純物を拡散により形成
しベース2を作る。N現不純!吻全ベース内に拡散によ
り形成して工、ミック3を得る。その後、表面パシベー
ションどしてシリコン酸化膜4全形成し、電極を引き出
すコンタクト窓を形成する。次に白金を蒸着にて表面に
つけ、500°C前後の温度で加熱し、シリコンと白金
との合金層5全作った後、白金全王水で除去する。
We propose a method for forming multilayer electrodes that does not require 11 processing (31:J), which has the effect of completely preventing cracking of wafers and increasing the number of wafers processed.
Ikikawa Sumono, and in non-inventiveness, to make the lower gold j1 ring (19, titanium, platinum) <A'll'fili (
It was used in 1) It is here that Δ invention is ~'! Ml
A description will be given below using a silicon transistor as an example of i Hl. FIG. 1 is a cross-sectional view of the same, and a base 2 is formed by forming a P hari impurity on a conductor substrate 1 containing N type impurities IiI/J by diffusion. N is currently impure! It is formed by diffusion within the entire base of the proboscis to obtain Mic 3. Thereafter, the silicon oxide film 4 is entirely formed by surface passivation, and a contact window from which the electrode is drawn is formed. Next, platinum is applied to the surface by vapor deposition, heated at a temperature of around 500°C to form the entire silicon-platinum alloy layer 5, and then removed with platinum aqua regia.

次に表面に窒化シリコン膜6 ’、r CV D法によ
り成長させPRを用いて所望の領域(上部電極が残され
る↑f1;分以外)をエツチングし、さらにチタン7゜
白金8をスパッタ法にて表面に形成する。この状態を第
1図に示す。チタン9白金スパツタの際には1) Rが
ないのでウェハース全冷却する必要はなく、その捷ま高
温でスパッタすることができる。
Next, a silicon nitride film 6' is grown on the surface by the CVD method, and desired areas (except for the upper electrode ↑f1; where the upper electrode remains) are etched using PR, and then titanium 7° and platinum 8 are deposited by sputtering. to form on the surface. This state is shown in FIG. When performing titanium-9-platinum sputtering, 1) Since there is no R, there is no need to completely cool the wafer, and sputtering can be performed at a high temperature until the wafer is cut.

次に高温のリン酸を用いて窒化シリコン膜をエツチング
することによシ窒化シリコン膜及び窒化シリコン膜上の
チタン、白金が同時に除去される。
Next, by etching the silicon nitride film using high temperature phosphoric acid, the silicon nitride film and the titanium and platinum on the silicon nitride film are simultaneously removed.

この後必要な領域に金メッキ9全行って完成する。After this, gold plating is applied to all required areas to complete the process.

この状態全第2図に示す。This state is shown in FIG.

本実施例によhばチタン、白金スパッタ時の下に敷く物
質として従来のPRのかわりにCVD法で成長した窒化
シリコン膜?用いているため、ウェハースが加熱され高
温になっても焼きつくことがなく、容易に剥離できる。
In this example, a silicon nitride film was grown by CVD instead of conventional PR as a material to be placed under titanium and platinum sputtering. Because of this, even if the wafer is heated to high temperatures, it will not burn and can be easily peeled off.

このため従来必要とした水冷治具へのウェハースの貼イ
づ、締めつけの必要がなくウェハースの割れを防dzす
ることができる他、治具が1711潔になり1回当りの
処理枚数も向上する。
As a result, there is no need to attach or tighten the wafer to a water-cooled jig, which was required in the past, and it is possible to prevent wafer cracking.In addition, the jig is 1711 mm clean, increasing the number of wafers processed per run. .

尚、シリコン窒化膜のかわpKンリコン酸化膜を用いて
もよい。この時はその下の表面保獲膜としてはシリコン
窒化膜を使用し、エツチング液としては希フy酸を1吏
用すればよい。
Note that a pK silicon oxide film may be used instead of a silicon nitride film. At this time, a silicon nitride film may be used as the underlying surface preservation film, and one portion of dilute phosphoric acid may be used as the etching solution.

次に、上記のシリコン窒化)j〆もしくはシリコン酸化
膜のかわジにアルミニウム全筒用した他の実施例を第3
図、第4図を用いて説明する。
Next, another example in which the entire aluminum tube was used instead of the silicon nitride film or silicon oxide film described above will be described in the third example.
This will be explained using FIG.

まず、N型不純物を含む半導体基板1に!1型不純物を
城赦によシ形成しベース2を作る。N型不純物をベース
内に拡散により形成し、エミッタ3全得る。その後表面
パシベーションとしてシリコン酸イ圀(ざ4.シリコン
窒化膜5全形成し 71(極全引き出すコンタクト窓を
形成する。次に表面に白金を蒸着しこれ全500°0前
後の温度で装処理してシリコンと白金との合金6を作っ
た後、白金全王水で除去する。次に表面にアルミニウム
7を蒸Mによシ成長させ、pItl用めて所望の領域(
上層電極形成領域以外)金工、チングし、さらにチタン
8.白金9をスパッタ法にて表面に形成する。
First, a semiconductor substrate 1 containing N-type impurities! Form the type 1 impurity to create base 2. An N-type impurity is formed in the base by diffusion to obtain the entire emitter 3. After that, a silicon nitride film 5 is formed as a surface passivation, and a contact window 71 (which is fully drawn out) is formed.Next, platinum is vapor deposited on the surface and treated at a temperature of about 500°C. After making an alloy 6 of silicon and platinum, it is removed with platinum total aqua regia. Next, aluminum 7 is grown on the surface by vaporized M, and the desired area (
(other than the upper layer electrode formation area) metal work, chiming, and titanium 8. Platinum 9 is formed on the surface by sputtering.

この状態を第3図に示す。チタン、白金スパッタの際に
はP R全周いてないのでウェハース全冷却する必要は
なく、そのまま高温で形成できることが特徴である。
This state is shown in FIG. During titanium and platinum sputtering, since the entire periphery of the PR is not covered, there is no need to completely cool the wafer, and the wafer can be formed directly at high temperatures.

次にリン酸を用いてアルミニウムをエツチングすること
によりアルミニウム及びアルミニウム上のチタン、白金
が剥離される。この後必要な領域に金メッキ10を行っ
て完成する。この状態を第4図に示す。
Next, by etching the aluminum using phosphoric acid, the aluminum and the titanium and platinum on the aluminum are peeled off. After this, gold plating 10 is applied to the necessary areas to complete the process. This state is shown in FIG.

この実施例によればチタン、白金スパッタ時の下に敷く
物質として従来のl) Rのかわりに蒸着で形成したア
ルミニウム金柑いているため、ウェハースが加熱され室
温になってもす尭きつくことがなく容易に剥離できる。
According to this example, aluminum kumquat formed by vapor deposition is used instead of the conventional l)R as a material to be placed under titanium and platinum sputtering, so that the wafer does not become sticky even when the wafer is heated and reaches room temperature. Can be easily peeled off.

このため従来必璧とした水冷治具へのウェハースの貼伺
、締めつけの必要がなくウェハースの割れを防止するこ
とができる他、治具が節紮にな91回当りの処理枚数も
向上する。
Therefore, there is no need to attach or tighten the wafer to a water-cooled jig, which was necessary in the past, and cracking of the wafer can be prevented, and the number of wafers processed per 91 cycles can be increased by saving on the use of the jig.

な卦、この実施例ではアルミニウムの下には表面保獲膜
として窒化シリコン膜全股6、アルミニウム除去には高
温全装しない点で第1の実施例と違違っているが、得ら
れる効果はいずれも従来に比して多大なものである。
This embodiment is different from the first embodiment in that a silicon nitride film is used as a surface retention film under the aluminum, and the aluminum is not completely covered at high temperature for removal, but the effect obtained is Both of these are larger than the conventional ones.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図及び第2図はそれぞれ不発明の一実施例による金
電極構造のトランジスタの製造過程を示す各断面図、第
3図及び第4図は他の実施例の各断面図である。 1・・・・n型半導体栽板、2・・・・ベース、3・・
・・・第1 図 (イ)2図 手続補正書(自発) 58.11.−2 昭和  年  月  1] 特許庁長官 殿 2、発明の名称   半導体装置の製造方法3、補正を
する者 事件との関係       出 19K(人東京都港区
芝五丁1」33番1号 (423)   日本電気株式会社 代表占 関本忠弘 4、代理人 5、補正の対象 明細!jの1発明の詳細な説明」の欄 6、補正の内容 1)明hqn i+rの第3頁2行目の「ウニバス」を
「ウェハース」((訂正する。 2)間約1%トの第4頁5行目の「バミベーション」を
「パシベーション」に訂正する。 3)明細付の第7頁9行目の「違」を削除する。
FIGS. 1 and 2 are sectional views showing the manufacturing process of a transistor with a gold electrode structure according to one embodiment of the invention, and FIGS. 3 and 4 are sectional views of another embodiment. 1...N-type semiconductor planting board, 2...Base, 3...
...Figure 1 (a) Figure 2 procedural amendment (voluntary) 58.11. -2 Month 1, Showa 1] Commissioner of the Japan Patent Office 2 Title of the invention Method for manufacturing semiconductor devices 3 Relationship to the person making the amendment Case No. 19K (No. 33-1, Shiba Go-cho 1, Minato-ku, Tokyo) (423 ) NEC Co., Ltd. Representative Tadahiro Sekimoto 4, Agent 5, Particulars subject to amendment! j. ``Unibus'' is changed to ``wafer.'' Delete "difference".

Claims (1)

【特許請求の範囲】 半導体基板への所望の不純物拡散を行なう工程と、表面
保護膜全形成する工程と、表面にチタン。 白金、金からなる多層電極を形成する工程とを含む半導
体装置の製造方法において、チタン、白金電極ヲ虜択的
に剥離するためその下に設ける材料としてシリコン窒化
膜もしくはアルミニウム膜もしくはシリコン酸化膜k 
fW用し、これらをエツチングする時同時に上層のチタ
ン、白金を除去することを’i’&徴とする半導体装置
の製造方法。
[Claims] A step of diffusing desired impurities into a semiconductor substrate, a step of completely forming a surface protective film, and a step of forming titanium on the surface. In a semiconductor device manufacturing method including a step of forming a multilayer electrode made of platinum and gold, a silicon nitride film, an aluminum film, or a silicon oxide film is used as a material to be provided under the titanium or platinum electrode in order to selectively peel it off.
A method for manufacturing a semiconductor device in which the upper layer of titanium and platinum are removed at the same time as fW is etched.
JP13530582A 1982-08-03 1982-08-03 Manufacture of semiconductor device Pending JPS5925220A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13530582A JPS5925220A (en) 1982-08-03 1982-08-03 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13530582A JPS5925220A (en) 1982-08-03 1982-08-03 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5925220A true JPS5925220A (en) 1984-02-09

Family

ID=15148604

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13530582A Pending JPS5925220A (en) 1982-08-03 1982-08-03 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5925220A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003063228A1 (en) * 2002-01-25 2003-07-31 Mergeoptics Gmbh Method for the production of a hetero-bipolar transistor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003063228A1 (en) * 2002-01-25 2003-07-31 Mergeoptics Gmbh Method for the production of a hetero-bipolar transistor

Similar Documents

Publication Publication Date Title
JPS6281764A (en) Manufacture of silicon carbide device
JPS60201666A (en) Semiconductor device
JPS5925220A (en) Manufacture of semiconductor device
JPH01184927A (en) Manufacture of large area semiconductor substrate
JPH08255769A (en) Method of manufacturing semiconductor device
JPS6362326A (en) Manufacture of semiconductor device
US4632728A (en) Method of manufacturing a glass passivation type semiconductor device
JPS61226958A (en) Semiconductor device and manufacture thereof
JPS59227128A (en) Oxidation method for semiconductor substrate
JPS62104078A (en) Manufacture of semiconductor integrated circuit device
JPH0697166A (en) Electrode structure and fabrication thereof
JPS58147132A (en) Manufacture of semiconductor device
JPS61110462A (en) Semiconductor device and manufacture thereof
JPH0414218A (en) Manufacture of semiconductor element
JPS5823437A (en) Impurity introduction method in semiconductor device
JPS6169122A (en) Manufacture of semiconductor device
JPS60171722A (en) Manufacture of semiconductor device
JPS63126251A (en) Semiconductor integrated circuit device
JPH0669036B2 (en) Method for manufacturing semiconductor device
JPH01112769A (en) Semiconductor device
JPS6010719A (en) Manufacture of semiconductor device
JPS60193330A (en) Method for diffusing impurities into semiconductor
JPS60123027A (en) Manufacture of semiconductor device
JPS57128076A (en) Manufacture of schottky barrier diode
JPS609175A (en) Manufacture of semiconductor device