JPS5925220A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the breakage of wafers as well as to increase the number of processed wafers by a method wherein a silicon nitride film and the like is used as the material to be provided below a titanium and platinum electrode for selective exforiation, and the titanium and platinum located on the upper layer are removed simultaneously when an etching is performed on them. CONSTITUTION:A base 2 is formed by diffusing p type impurities on a semiconductor substrate 1 containing N type impurities. An emitter 3 is obtained by diffusing N type impurities in the base 2. Subsequently, a silicon oxide film 4 is formed, and a contact window to be used to lead out an electrode is formed. Then, platinum is attached to the surface by vapor-deposition, and after an alloy layer 5 of silicon and platinum has been formed by heating, the platinum is removed by aqua regia. Then, a silicon nitride film 6 is grown on the surface, an etching is performed on the desired region using a photoresist, and titanium 7 and platinum 8 are formed on the surface by performing a sputtering method. Then, the titanium and platinum on the fiom are removed simultaneously by performing an etching on the film 6 using phosphoric acid of high temperature. Subsequently, gold-plating 9 is performed on the necessary region.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device having multilayer electrodes on its surface.

A so-called gold electrode 4/7 semiconductor device I in which gold is used as an electrode on the surface of a semiconductor substrate is used for various purposes as a highly reliable semiconductor device. This takes advantage of gold's non-corrosive properties. Here, the entire method for manufacturing a conventional gold electrode structure will be explained.

First, impurities are diffused into a desired region of a semiconductor substrate to form an active layer, and then a silicon oxide film is formed on the surface of the substrate. After removing the entire desired region of the oxide film by etching, platinum evaporation is performed and a silicon-platinum alloy layer (platinum silicide layer) is completely formed by high-temperature treatment. After that, the platinum was peeled off with aqua regia, etc., and the photoresist (i'R) was applied.
,) Next, titanium and platinum are formed in areas other than the titanium and platinum areas, and titanium and platinum are formed on the entire surface by sputtering.

If the PR is then peeled off, the titanium and platinum on the P layer are removed at the same time, allowing the entire titanium and platinum electrodes to be selectively formed only in desired areas. After that, if you do all the gold plating on the platinum,
A desired gold electrode structure can be obtained. Thus, for example, a semiconductor device requiring a gold electrode always has to have a multilayer metal electrode structure.

However, when using the conventional method, there were many cracks in the sea urchins during the titanium and platinum splicing process, and the number of sheets processed in one process was small.

The reason for this: 9-1 strainer is that the wafer must be tightened in a water-cooling jig to prevent the wafer from rising in temperature during sputtering with Bhutan and platinum. On the other hand, it is necessary to prevent the temperature rise of the wafer due to the need to prevent titanium and platinum from increasing.
This is because the quality of the applied substrate is altered by the high ρIA, resulting in a serious situation where it becomes difficult to peel. However, the above drawbacks were unavoidable as long as IJ tt was used to form multilayer sugar electrodes.

We propose a method for forming multilayer electrodes that does not require 11 processing (31:J), which has the effect of completely preventing cracking of wafers and increasing the number of wafers processed.
Ikikawa Sumono, and in non-inventiveness, to make the lower gold j1 ring (19, titanium, platinum) <A'll'fili (
It was used in 1) It is here that Δ invention is ~'! Ml
A description will be given below using a silicon transistor as an example of i Hl. FIG. 1 is a cross-sectional view of the same, and a base 2 is formed by forming a P hari impurity on a conductor substrate 1 containing N type impurities IiI/J by diffusion. N is currently impure! It is formed by diffusion within the entire base of the proboscis to obtain Mic 3. Thereafter, the silicon oxide film 4 is entirely formed by surface passivation, and a contact window from which the electrode is drawn is formed. Next, platinum is applied to the surface by vapor deposition, heated at a temperature of around 500°C to form the entire silicon-platinum alloy layer 5, and then removed with platinum aqua regia.

Next, a silicon nitride film 6' is grown on the surface by the CVD method, and desired areas (except for the upper electrode ↑f1; where the upper electrode remains) are etched using PR, and then titanium 7° and platinum 8 are deposited by sputtering. to form on the surface. This state is shown in FIG. When performing titanium-9-platinum sputtering, 1) Since there is no R, there is no need to completely cool the wafer, and sputtering can be performed at a high temperature until the wafer is cut.

Next, by etching the silicon nitride film using high temperature phosphoric acid, the silicon nitride film and the titanium and platinum on the silicon nitride film are simultaneously removed.

After this, gold plating is applied to all required areas to complete the process.

This state is shown in FIG.

In this example, a silicon nitride film was grown by CVD instead of conventional PR as a material to be placed under titanium and platinum sputtering. Because of this, even if the wafer is heated to high temperatures, it will not burn and can be easily peeled off.

As a result, there is no need to attach or tighten the wafer to a water-cooled jig, which was required in the past, and it is possible to prevent wafer cracking.In addition, the jig is 1711 mm clean, increasing the number of wafers processed per run. .

Note that a pK silicon oxide film may be used instead of a silicon nitride film. At this time, a silicon nitride film may be used as the underlying surface preservation film, and one portion of dilute phosphoric acid may be used as the etching solution.

Next, another example in which the entire aluminum tube was used instead of the silicon nitride film or silicon oxide film described above will be described in the third example.
This will be explained using FIG.

First, a semiconductor substrate 1 containing N-type impurities! Form the type 1 impurity to create base 2. An N-type impurity is formed in the base by diffusion to obtain the entire emitter 3. After that, a silicon nitride film 5 is formed as a surface passivation, and a contact window 71 (which is fully drawn out) is formed.Next, platinum is vapor deposited on the surface and treated at a temperature of about 500°C. After making an alloy 6 of silicon and platinum, it is removed with platinum total aqua regia. Next, aluminum 7 is grown on the surface by vaporized M, and the desired area (
(other than the upper layer electrode formation area) metal work, chiming, and titanium 8. Platinum 9 is formed on the surface by sputtering.

This state is shown in FIG. During titanium and platinum sputtering, since the entire periphery of the PR is not covered, there is no need to completely cool the wafer, and the wafer can be formed directly at high temperatures.

Next, by etching the aluminum using phosphoric acid, the aluminum and the titanium and platinum on the aluminum are peeled off. After this, gold plating 10 is applied to the necessary areas to complete the process. This state is shown in FIG.

According to this example, aluminum kumquat formed by vapor deposition is used instead of the conventional l)R as a material to be placed under titanium and platinum sputtering, so that the wafer does not become sticky even when the wafer is heated and reaches room temperature. Can be easily peeled off.

Therefore, there is no need to attach or tighten the wafer to a water-cooled jig, which was necessary in the past, and cracking of the wafer can be prevented, and the number of wafers processed per 91 cycles can be increased by saving on the use of the jig.

This embodiment is different from the first embodiment in that a silicon nitride film is used as a surface retention film under the aluminum, and the aluminum is not completely covered at high temperature for removal, but the effect obtained is Both of these are larger than the conventional ones.

[Brief explanation of the drawing]

FIGS. 1 and 2 are sectional views showing the manufacturing process of a transistor with a gold electrode structure according to one embodiment of the invention, and FIGS. 3 and 4 are sectional views of another embodiment. 1...N-type semiconductor planting board, 2...Base, 3...
...Figure 1 (a) Figure 2 procedural amendment (voluntary) 58.11. -2 Month 1, Showa 1] Commissioner of the Japan Patent Office 2 Title of the invention Method for manufacturing semiconductor devices 3 Relationship to the person making the amendment Case No. 19K (No. 33-1, Shiba Go-cho 1, Minato-ku, Tokyo) (423 ) NEC Co., Ltd. Representative Tadahiro Sekimoto 4, Agent 5, Particulars subject to amendment! j. ``Unibus'' is changed to ``wafer.'' Delete "difference".

Claims (1)

[Claims] A step of diffusing desired impurities into a semiconductor substrate, a step of completely forming a surface protective film, and a step of forming titanium on the surface. In a semiconductor device manufacturing method including a step of forming a multilayer electrode made of platinum and gold, a silicon nitride film, an aluminum film, or a silicon oxide film is used as a material to be provided under the titanium or platinum electrode in order to selectively peel it off.
A method for manufacturing a semiconductor device in which the upper layer of titanium and platinum are removed at the same time as fW is etched.