JPS60123027A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS60123027A JPS60123027A JP23098383A JP23098383A JPS60123027A JP S60123027 A JPS60123027 A JP S60123027A JP 23098383 A JP23098383 A JP 23098383A JP 23098383 A JP23098383 A JP 23098383A JP S60123027 A JPS60123027 A JP S60123027A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- external lead
- source
- exposed
- silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 13
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 238000000034 method Methods 0.000 claims abstract description 19
- 239000000126 substance Substances 0.000 claims abstract description 11
- 238000001312 dry etching Methods 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 12
- 229910052710 silicon Inorganic materials 0.000 abstract description 12
- 239000010703 silicon Substances 0.000 abstract description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 11
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 11
- 238000004544 sputter deposition Methods 0.000 abstract description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052782 aluminium Inorganic materials 0.000 abstract description 5
- 239000010410 layer Substances 0.000 abstract description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 abstract description 4
- 238000005530 etching Methods 0.000 abstract description 3
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 239000002344 surface layer Substances 0.000 abstract description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 abstract description 2
- 239000010408 film Substances 0.000 description 21
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 230000004913 activation Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 210000001699 lower leg Anatomy 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は半導体装置、特にＭＯ８型半導体装置の製造方
法に係り、ソース、ドレイン領域に対シ良好なコンタク
ト抵抗を有する外部導出用電極を形成し得る半導体装置
の製造方法に関する。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, particularly an MO8 type semiconductor device, and includes forming an external lead-out electrode having good contact resistance in a source and drain region. The present invention relates to a method for manufacturing a semiconductor device.
従来のＭＯ８型半導体装置の一般的な製造方法を、第１
図に断面図を示すＮチャンネルシリコングー）ＭＯ８Ｌ
ＳＩを例にとって説明する。まず、Ｐ型シリコン基板ｔ
（ρ−１０−〃Ω・ｃｒｎ）の片側主面に厚い膜厚と薄
い膜厚を有する絶縁膜、例えばシリコン酸化膜２を形成
し、次に薄いシリコン膜上にポリシリコンゲート領域３
を形成させる。このゲート領域３をマスクにし、薄いシ
リコン酸化膜をパターニングしてからそのゲート３領域
をマスクにしてＮ型高濃度不純物のソースゲａ、ドレイ
ンｐ’ｂ領域を拡散あるいはイオン注入により形成する
。その後ソース、ドレイン、ゲート領域部分上にシリコ
ン酸化膜コを更に堆積させる。続いてソース、ドレイン
２ゲート領域に対して外部導出用電極ｊを形成するため
に、ソース、ドレイン。The general manufacturing method of the conventional MO8 type semiconductor device is explained in the first part.
N-channel silicone (cross-sectional view shown in figure) MO8L
This will be explained using SI as an example. First, P-type silicon substrate t
An insulating film having a thick film thickness and a thin film thickness, for example, a silicon oxide film 2, is formed on one main surface of (ρ-10-〃Ω・crn), and then a polysilicon gate region 3 is formed on the thin silicon film.
to form. Using this gate region 3 as a mask, a thin silicon oxide film is patterned, and then using the gate 3 region as a mask, source gate a and drain p'b regions of N-type high concentration impurities are formed by diffusion or ion implantation. Thereafter, a silicon oxide film is further deposited on the source, drain, and gate regions. Next, in order to form external lead-out electrodes j for the source and drain 2 gate regions, the source and drain electrodes are formed.
ゲート領域の各部上のシリコン酸化膜λに写真蝕刻技術
によりコンタクトホールを開ける。このコンタクトホー
ル内の露出されたソース、ドレイン。Contact holes are made in the silicon oxide film λ on each part of the gate region by photolithography. The exposed source and drain inside this contact hole.
ゲート領域を含むシリコン酸化膜上にθ、Ｊ〜３チのシ
リコン含有のアルミニウム層を外部導出用電極ｊとして
スパッタリングにより形成し、これをパターニングしア
ニーリンｊする。この上かう保護膜としてリンを含んだ
シリコン酸化膜ｔを素子表面全体に形成し、最後に外部
導出用電極取出し部を除去する（図には示されていない
。）。以上が従来技術に係るＭＯＳ ＬＳＩの製造方法
の概略であるが、各種熱処理等の細かい点については省
略した。On the silicon oxide film including the gate region, a silicon-containing aluminum layer of θ, J to 3 cm is formed as an external lead-out electrode j by sputtering, and this is patterned and annealed. On top of this, a silicon oxide film t containing phosphorus is formed as a protective film over the entire surface of the element, and finally the external lead electrode extraction portion is removed (not shown in the figure). The above is an outline of the MOS LSI manufacturing method according to the prior art, but details such as various heat treatments have been omitted.
近年のＭＯＥＩ ＬＳＩでは、ソース、ドレイン領域は
接合深さが浅く、比較的低い表面不純物濃度を有する＠
そのためソース、ドレイン領域と外部導出用電極とのコ
ンタクト抵抗がシリコン含有のアルミニウム層の質およ
びスパッター条件により影響を受けやすく、その両者の
コンタクトは非オーミツク性になり易い。また、コンタ
クトホールより露出されたソース、ドレイン領域表面に
は、コンタクトホール形成の際の工、テン／液により３
０〜２００ Ａの極めて薄い低級の酸化膜が形成され、
その膜の存在により領域と電極とのコンタクトは非オー
ミツク性になり易い。これはＭＯＳ ＬＳＩの性能を著
しく損なう原因となる。このため従来のＭＯＳ Ｌ８工
の製造方法は、ブロービンｊ歩留まゝ゛りの低下、製品
としての高信頼性の欠如といった問題点を有する。In recent MOEI LSIs, the source and drain regions have shallow junction depths and relatively low surface impurity concentrations.
Therefore, the contact resistance between the source and drain regions and the external lead-out electrode is easily influenced by the quality of the silicon-containing aluminum layer and the sputtering conditions, and the contact between the two tends to be non-ohmic. In addition, the surfaces of the source and drain regions exposed through the contact holes are covered with 3.
An extremely thin low-grade oxide film of 0 to 200 A is formed,
The presence of the film tends to make the contact between the region and the electrode non-ohmic. This causes a significant deterioration in the performance of the MOS LSI. For this reason, the conventional manufacturing method for MOS L8 has problems such as a decrease in blowbin yield and a lack of high reliability as a product.
そこで本発明は、半導体装置の領域とその領域に対する
外部導出用電極とのコンタクトが、良好なコンタクト抵
抗を有するオーミック性をもった半導体装置の製造方法
を提供することを目的とする０
〔発明の概要〕
本発明は、半導体装置の領域上の絶縁膜にコンタクトホ
ールな形成しその領域表面部を露出させた後、その露出
面に外部導出用電極をコンタクトするに当り、その領域
露出面の表面をケミカルドライエツチンダ処理により軽
くエツチングして清浄な表面を露呈させ、その後外部導
出用電極を形成することにおる。そして露出面を軽くエ
ツチングする方法には、化学薬品によるものとドライエ
ツチングによるものとに大別されるが、前者は化学薬品
により良好なコンタクト抵抗を逆に妨げる膜が形成され
易いため、本発明では後者、即ちドライエツチングを行
なっている。SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a method for manufacturing a semiconductor device in which the contact between a region of the semiconductor device and an electrode for external conduction to the region has ohmic properties and has good contact resistance. Summary] The present invention involves forming a contact hole in an insulating film on a region of a semiconductor device to expose the surface of the region, and then contacting the exposed surface with an electrode for external conduction. The substrate is lightly etched using a chemical dry etching process to expose a clean surface, and then an electrode for external lead-out is formed. Methods for lightly etching the exposed surface are roughly divided into methods using chemicals and methods using dry etching, but in the former method, chemicals tend to form a film that impedes good contact resistance, so the present invention In this case, the latter method, that is, dry etching is performed.
以下本発明の一実施例を第２図及び第３図を参照しなが
ら説明する。第２図は本発明に係るケミカルドライエラ
テンｊを施す直前のＭＯＳ ＬＳＩの構造断面図であり
、第１図と同一の要素については同一の符号を付し説明
を省略する。第２図に示す構造に至るまでの製造過程、
即ち外部導出用電極形成のためのコンタクトホールな絶
縁膜、例えばシリコン酸化膜に写真蝕刻技術により開け
、ソース、ドレイン、ゲート領域表面を露出させる過程
までは、従来技術と同様である。この後、外部導出用電
極として０．ｊ〜３チのシリコン含有のアルミニウム層
をスパッタリングにより形成する過程に入る前に、以下
の方法によりコンタクトホール内の露出領域表面を活性
化する。An embodiment of the present invention will be described below with reference to FIGS. 2 and 3. FIG. 2 is a cross-sectional view of the structure of a MOS LSI just before applying the chemical dryer temperature j according to the present invention, and the same elements as in FIG. The manufacturing process leading to the structure shown in Figure 2,
That is, the steps up to the process of opening a contact hole in an insulating film, such as a silicon oxide film, for forming an external lead-out electrode by photolithography and exposing the surfaces of the source, drain, and gate regions are the same as those of the prior art. After this, as an electrode for external lead-out, 0. Before starting the process of forming a silicon-containing aluminum layer of 1 to 3 inches by sputtering, the surface of the exposed region within the contact hole is activated by the following method.
ケミカルドライエラテン／（ｃｎｍ）装置により、０．
を−タ、。、ＯＦ４を１００”％ｎｉｎの流速で流し、
真空度をｊ ×１０ ’ｔｏｒｒニ保ち、マグネトロン
出力弘ＯＯＷにおいて１０秒間エエツチングる。A chemical dryer temperature/(cnm) device is used to dry 0.
-ta,. , OF4 is flowed at a flow rate of 100”% nin,
The vacuum level was kept at j x 10' torr, and etching was performed for 10 seconds at the magnetron output OOW.
これによりコンタクトホール内に露出したＮ＋ソース、
ドレイン領域およびポリシリ弓ンゲート領域の表面層が
約ｇｏ；除去され活性化される。この後、良度２チの弗
酸に７０秒間浸し、流水洗浄して乾燥する。第３図は上
述のケミカルドライエツチングを施した直後のＭＯ８Ｌ
ＳＩの構造断面図で、各部分は第２図と同一であるため
同一符号を付しである。本発明実施にあたってのエラテ
ンｊ量はＳＯ〜ｔｏｏ Ａ程度が好ましい。エッテン７
量がこれ以下では活性化が十分性なわれず、これ以上で
は、例えばｔｏｏ Ｘを越えると接触部における電極配
線の断線等のおそれが生ずるためである。As a result, the N+ source exposed in the contact hole,
The surface layers of the drain region and polysilicon gate region are approximately removed and activated. Thereafter, it is immersed in grade 2 hydrofluoric acid for 70 seconds, washed with running water, and dried. Figure 3 shows MO8L immediately after the chemical dry etching described above.
This is a cross-sectional view of the structure of the SI, and since each part is the same as in FIG. 2, the same reference numerals are given. In carrying out the present invention, the amount of elaten j is preferably about SO to too A. Etten 7
This is because if the amount is less than this, activation will not be sufficient, and if the amount is more than this, for example, if it exceeds too X, there is a risk of disconnection of the electrode wiring at the contact portion.
以上の処理を施した後、外部導出用電極としてＯ１ｊ〜
３％のシリコン含有のアルミニウム層をスパッタリング
により形成するが、この場合以下の条件で行なうことが
好ましい。真空度をλｘ１０’ｔｏｎ−より高真空に保
った後、超高純度Ａｒを流入し、真空度を２ Ｘ １０
− ｔｏｒｒ程度に保つ。ここでスパッタリング装置の
電源をコントロールし、スパッタ速度を１０シｊθＣに
調節し最終膜厚が１．０μｍとなるよう外部導出用電極
を形成させる。After performing the above processing, O1j ~
An aluminum layer containing 3% silicon is formed by sputtering, preferably under the following conditions. After maintaining the vacuum level higher than λx10'ton-, ultra-high purity Ar was introduced to increase the vacuum level to 2 x 10
- Maintain at around torr. Here, the power source of the sputtering apparatus is controlled, the sputtering speed is adjusted to 10 psi, and the external lead electrode is formed so that the final film thickness is 1.0 .mu.m.
この後の工程、即ち外部導出用電極のパターニング、ア
ニーリング、そして保護膜としてのリンを含んだシリコ
ン酸化膜の形成、外部導通用電極取出し部の除去、につ
いては従来技術に係る方法と同様である〇
〔発明の効果〕
従来技術に係る゛方法で製造されたＭＯ８ＬＳＩでは、
ソース、ドレイン、ゲートのそれぞれと外部導通用電極
とのコンタクトが非オニミック性になるものがｔ％程度
発生しており、これらｊ％のものについてのブロービン
メ歩留まりは０％、即ち製品としては全くの不良品であ
った。本発明に係る方法を用いると、コンタクトが非オ
ーミツク性になる欠点を完全に克服することができる。The subsequent steps, that is, patterning of the electrode for external conduction, annealing, formation of a silicon oxide film containing phosphorus as a protective film, and removal of the lead-out portion of the electrode for external conduction, are the same as the method according to the prior art. 〇 [Effect of the invention] In the MO8LSI manufactured by the method related to the prior art,
Approximately t% of contacts between the source, drain, and gate and external conductive electrodes are non-onimic, and the yield rate for these j% of contacts is 0%, that is, there is no product at all. It was a defective product. Using the method according to the invention, the disadvantage of non-ohmic contact properties can be completely overcome.
特にＣ−ＭＯ８のシリコンゲート素子、あるいはＮチャ
ンネルシリコンゲート素子においてその効果が著しく、
品質レベルが著しく向上し、総合歩留まりとして数チも
の改善がみられる。This effect is particularly remarkable in C-MO8 silicon gate devices or N-channel silicon gate devices.
The quality level has improved significantly, and the overall yield has improved by several orders of magnitude.
第１図はＮチャンネルシリコンゲートル１０ＢＬＳＩ
の一般的な構造断面図、第１図は本発明に係るケミカル
ドライエツチングを施す直前のＭＯ５ＬＳＩ の構造断
面図、第３図は本発明に係るケミカルドライエツチング
を施した直後のＭＯ８ＬＳＩの構造断面図である。
ｌ・・・Ｐ型シリコン基板、２・・・シリコン酸化膜、
３・・・ポリシリコンゲート、弘・・・Ｎ型高不純物頭
域（４４ａ・・・ソース、ｇｂ・・・ドレイン）、ｊ・
・・外部導出用電極、ｔ・・・リンを含んだシリコン酸
化膜。
出願人代理人 猪 股 清Figure 1 shows N-channel silicon gaiter 10BLSI
1 is a structural sectional view of MO5LSI immediately before chemical dry etching according to the present invention is applied. FIG. 3 is a structural sectional view of MO8LSI immediately after chemical dry etching according to the present invention is applied. It is. l...P-type silicon substrate, 2...silicon oxide film,
3...Polysilicon gate, Hiro...N type high impurity head area (44a...source, gb...drain), j.
...External lead-out electrode, t...Silicon oxide film containing phosphorus. Applicant's agent Kiyoshi Inomata
Claims (1)
コンタクトホールを形成し前記半導体須坂の一部な路用
させ、この露出面に外部導出電極を形成してなる半導体
装置の製造方法において、前記外部導出用電極形成直前
に、前記コンタクトホール内に露出された半導体領域表
面をケミカルドライエツチング処理することを特徴とす
る半導体装置の製造方法。A method for manufacturing a semiconductor device, comprising forming an insulating film on the surface of a semiconductor region, forming a contact hole in a part of the insulating film to allow a part of the semiconductor substrate to be used, and forming an external lead-out electrode on the exposed surface. A method of manufacturing a semiconductor device, characterized in that immediately before forming the external lead-out electrode, the surface of the semiconductor region exposed in the contact hole is subjected to a chemical dry etching process.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23098383A JPS60123027A (en) | 1983-12-07 | 1983-12-07 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23098383A JPS60123027A (en) | 1983-12-07 | 1983-12-07 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60123027A true JPS60123027A (en) | 1985-07-01 |
Family
ID=16916386
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23098383A Pending JPS60123027A (en) | 1983-12-07 | 1983-12-07 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60123027A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63220547A (en) * | 1987-03-09 | 1988-09-13 | Matsushita Electronics Corp | Manufacture of semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5764927A (en) * | 1980-10-08 | 1982-04-20 | Toshiba Corp | Manufacture of semiconductor device |
-
1983
- 1983-12-07 JP JP23098383A patent/JPS60123027A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5764927A (en) * | 1980-10-08 | 1982-04-20 | Toshiba Corp | Manufacture of semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63220547A (en) * | 1987-03-09 | 1988-09-13 | Matsushita Electronics Corp | Manufacture of semiconductor device |
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