JPS5764927A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5764927A
JPS5764927A JP14101280A JP14101280A JPS5764927A JP S5764927 A JPS5764927 A JP S5764927A JP 14101280 A JP14101280 A JP 14101280A JP 14101280 A JP14101280 A JP 14101280A JP S5764927 A JPS5764927 A JP S5764927A
Authority
JP
Japan
Prior art keywords
substrate
openings
film
contact
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14101280A
Other languages
Japanese (ja)
Inventor
Shigeru Morita
Kazuhiko Hashimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP14101280A priority Critical patent/JPS5764927A/en
Publication of JPS5764927A publication Critical patent/JPS5764927A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268

Abstract

PURPOSE:To improve the contact property between a substrate and a wiring layer as well as yield in a process for forming an ohmic contact, by a method wherein openings are formed in an insulating film on a substrate, and after the substrate surface exposed in the openings is dry-etched, a conducting layer is formed. CONSTITUTION:For example, in the manufacturing process of an MOSIC, after source and drain regions 7, 8 and a diffusion wiring layer 9 are formed, by means of diffusion, in a substrate 1 on which a gate film 5, a gate polycrystalline Si layer 6 have been formed, a CVD oxide film 10 is deposited on the whole surface. Then, after openings for contact are provided in the film 10, for example, a plasma etching is applied such an extent that unevenness 11 is formed on the exposed substrate surface. Then, Al is deposited on the whole surface and patterned to form electrode wiring layers 13-15, and a sintering treatment is applied thereto. Thereby, even in case of a small opening area, an excellent ohmic contact can be obtaind, and yield can be improved.
JP14101280A 1980-10-08 1980-10-08 Manufacture of semiconductor device Pending JPS5764927A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14101280A JPS5764927A (en) 1980-10-08 1980-10-08 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14101280A JPS5764927A (en) 1980-10-08 1980-10-08 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5764927A true JPS5764927A (en) 1982-04-20

Family

ID=15282133

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14101280A Pending JPS5764927A (en) 1980-10-08 1980-10-08 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5764927A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6085515A (en) * 1983-10-17 1985-05-15 Fujitsu Ltd Manufacture of semiconductor device
JPS60123027A (en) * 1983-12-07 1985-07-01 Toshiba Corp Manufacture of semiconductor device
JPS6171628A (en) * 1984-09-14 1986-04-12 Fuji Electric Co Ltd Formation of semiconductor ohmic contact
USRE36475E (en) * 1993-09-15 1999-12-28 Hyundai Electronics Industries Co., Ltd. Method of forming a via plug in a semiconductor device
WO2013132783A1 (en) * 2012-03-07 2013-09-12 パナソニック株式会社 Nitride semiconductor laminate structure, nitride semiconductor light emitting element provided with nitride semiconductor laminate structure, and method for producing nitride semiconductor laminate structure

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6085515A (en) * 1983-10-17 1985-05-15 Fujitsu Ltd Manufacture of semiconductor device
JPS60123027A (en) * 1983-12-07 1985-07-01 Toshiba Corp Manufacture of semiconductor device
JPS6171628A (en) * 1984-09-14 1986-04-12 Fuji Electric Co Ltd Formation of semiconductor ohmic contact
USRE36475E (en) * 1993-09-15 1999-12-28 Hyundai Electronics Industries Co., Ltd. Method of forming a via plug in a semiconductor device
USRE38383E1 (en) 1993-09-15 2004-01-13 Hyundai Electronics Industries Co. Ltd. Method for forming a via plug in a semiconductor device
WO2013132783A1 (en) * 2012-03-07 2013-09-12 パナソニック株式会社 Nitride semiconductor laminate structure, nitride semiconductor light emitting element provided with nitride semiconductor laminate structure, and method for producing nitride semiconductor laminate structure

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