JPS57141937A - Wiring structure for semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the breaking of wire on the upper layer wiring by a method wherein contact holes are formed on the insulating film located on a substrate by performing an etching, and a polycrystalline Si wirin layer is formed in such a manner that it is filling up the contact holes, thereby enabling to reduce contact resistance, to obtain high density and to flatten the surface of the wiring layer. CONSTITUTION:In the manufacturing process of an MOSIC, for example, after a source and drain region has been formed by providing an Si gate, the first interlayer SiO2 film 8 is deposited, and contact holes 9-11 of approximately 0.3mum in diameter are formed by performing a photoetive using an electron beam exposure. Then, a CVD polycrystalline Si film of 0.3mum or thereabouts in thickness is deposied on the whole surface, and a smooth-surface construction is obtained by filling up the contact holes. Subsequently, a patterning is performed on the polycrystalline Si film 12, and after contact holes 14-16 have been formed by providing the second interlayer film 13, an upper layer Al wiring 17, for example, is formed. Accordingly, as the contact resistance is reduced, the contact holes can be formed in microscopic measurements, thereby enabling to obtain a high degree of integration and to prevent the breaking of wire.