JPS6473663A - Formation of dram cell - Google Patents

Abstract

PURPOSE:To make it possible to enhance an integration density of a cell by a method wherein a trench capacitor is formed at a boundary part between a first and a second semiconductor layers and a transistor to be connected to the trench capacitor is formed in the second semiconductor layer. CONSTITUTION:A p<++> silicon layer 1a is formed on a p<+> silicon substrate 1 and is etched for patterning; a prescribed region is left. Then, p<-> silicon layers 1b are formed; their interface is flattened; the p<++> silicon layer 1a is exposed. In this state, a thickness of the p<++> silicon layer 1a and the p<-> silicon layers 1b is made not to be thinner than a depth of a trench capacitor 3. Then, a device-isolation insulating film 2 is formed on the surface of the p<++> silicon layer 1a; after that, grooves 3a for the trench capacitors 3 are formed in such a way that they are stretched over the p<++> silicon layer 1a and the p<-> silicon layers 1b. Then, a capacitor insulating film 3b composed of silicon dioxide is formed by thermal oxidation or the like; after that, conductive polysilicon is filled and deposited; it is patterned to form a cell plate 3c; the trench capacitors 3 are completed. Then, MOS transistors 4 to be connected to the trench capacitors 3 are formed in the p<-> silicon layers 1b; furthermore, an interlayer insulating film 5, a bit line 6 and the like are formed; a trench capacitor cell is completed.