KR100295661B1 - Method for fabricating capacitor of dram - Google Patents
Method for fabricating capacitor of dram Download PDFInfo
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- KR100295661B1 KR100295661B1 KR1019980037797A KR19980037797A KR100295661B1 KR 100295661 B1 KR100295661 B1 KR 100295661B1 KR 1019980037797 A KR1019980037797 A KR 1019980037797A KR 19980037797 A KR19980037797 A KR 19980037797A KR 100295661 B1 KR100295661 B1 KR 100295661B1
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- interlayer insulating
- forming
- contact hole
- via contact
- etching
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/84—Electrodes with an enlarged surface, e.g. formed by texturisation being a rough surface, e.g. using hemispherical grains
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/485—Bit line contacts
Abstract
본 발명은 디램의 커패시터 제조방법에 관한 것으로, 종래에는 공정이 복잡하여 제조단가가 상승하는 문제점이 있었다. 따라서, 본 발명은 반도체기판의 상부를 제1층간절연막을 통해 평탄화시키는 공정과; 상기 제1층간절연막의 일부를 식각하여 형성된 제1비아콘택 홀에 폴리실리콘을 채워서 제1,제2폴리플러그를 형성하는 공정과; 상기 제1층간절연막의 상부에 제2층간절연막을 형성하고, 제2폴리플러그 상부의 제2층간절연막을 식각하여 형성된 제2비아콘택 홀에 비트라인을 형성하는 공정과; 상기 제2층간절연막의 상부에 제3층간절연막을 형성하고, 제1폴리플러그 상부의 제3,제2층간절연막을 식각하여 형성된 제3비아콘택 홀에 스토리지 노드를 형성하는 공정과; 상기 스토리지 노드가 형성된 반도체기판의 전면에 유전막을 증착한 후, 주변회로 영역의 제3∼제1층간절연막을 식각하여 제4비아콘택 홀을 형성하는 공정과; 상기 스토리지 노드가 형성된 유전막의 상부 및 제4비아콘택 홀에 금속물질을 증착하여 플레이트 전극 및 국부접속층을 형성하는 공정을 구비하여 이루어지는 디램의 커패시터 제조방법을 통해 스토리지 노드의 표면적을 최대한 넓게 하여 커패시턴스를 증가시킬 수 있고, 플레이트 전극과 주변회로 영역에 형성되는 국부접속층을 금속물질을 사용하여 동시에 형성함에 따라 공정의 단순화에 기여함으로써, 제조비용을 절감할 수 있는 효과가 있다.The present invention relates to a method for manufacturing a capacitor of a DRAM, and in the related art, a complicated manufacturing process has a problem in that a manufacturing cost increases. Accordingly, the present invention provides a method for fabricating a semiconductor substrate with a first interlayer insulating film; Forming first and second polyplugs by filling polysilicon in a first via contact hole formed by etching a portion of the first interlayer dielectric layer; Forming a second interlayer insulating layer on the first interlayer insulating layer, and forming a bit line in a second via contact hole formed by etching the second interlayer insulating layer on the second polyplug; Forming a third interlayer dielectric layer on the second interlayer dielectric layer, and forming a storage node in a third via contact hole formed by etching the third and second interlayer dielectric layers on the first polyplug; Depositing a dielectric film on the entire surface of the semiconductor substrate on which the storage node is formed, and then etching the third to first interlayer insulating films in the peripheral circuit region to form a fourth via contact hole; Forming a plate electrode and a local connection layer by depositing a metal material on the upper portion of the dielectric layer on which the storage node is formed and the fourth via contact hole, and forming a plate electrode and a local connection layer. It can increase the, and by simultaneously forming a local connection layer formed in the plate electrode and the peripheral circuit region using a metal material contributes to the simplification of the process, there is an effect that can reduce the manufacturing cost.
Description
본 발명은 디램(DRAM)의 커패시터 제조방법에 관한 것으로, 특히 커패시터 온 비트라인(capacitor on bitline : 이하, COB)구조의 커패시터 제조공정중에 칩 사이즈를 줄이기 위해 사용되는 국부 접속층(local interconnection)과 커패시터의 플레이트(plate) 전극을 동일한 물질로 사용하여 공정을 단순화하기에 적당하도록 한 디램의 커패시터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a capacitor of a DRAM, and in particular, a local interconnection layer used to reduce chip size during a capacitor manufacturing process of a capacitor on bitline (COB) structure. A method of manufacturing a capacitor of a DRAM in which the plate electrode of the capacitor is made of the same material so as to be suitable for simplifying the process.
일반적으로, 디램의 커패시터는 폴리실리콘 재질의 스토리지 노드(storage node), 유전막 및 폴리실리콘 재질의 플레이트 전극이 적층된 구조로 형성된다. 이와같은 종래 디램의 커패시터 제조방법을 도면을 참조하여 상세히 설명하면 다음과 같다.In general, the capacitor of the DRAM is formed of a stacked structure of a storage node made of polysilicon, a dielectric layer, and a plate electrode made of polysilicon. A method of manufacturing a capacitor of the conventional DRAM will be described in detail with reference to the accompanying drawings.
도1a 내지 도1f는 종래 디램의 커패시터 제조방법을 보인 수순단면도로서, 이에 도시한 바와같이 셀 영역 및 주변회로 영역에 게이트(2A,2B,2C)가 형성된 반도체기판(1)의 상부에 층간절연막(3A)을 형성하는 공정(도1a)과; 그 층간절연막(3A)의 일부를 식각하여 제1비아콘택 홀을 형성한 후, 그 제1비아콘택 홀에 폴리실리콘을 채워서 폴리플러그(4A,4B)를 형성하는 공정(도1b)과; 그 폴리플러그(4A,4B)가 형성된 층간절연막(3A)의 상부에 층간절연막(3B)을 형성하고, 상기 폴리플러그(4B) 상부의 층간절연막(3B)를 식각하여 제2비아콘택 홀을 형성한 후, 그 폴리플러그(4B)와 접속되도록 비트라인(5)을 형성하는 공정(도1c)과; 그 비트라인(5)이 형성된 층간절연막(3B)의 상부에 층간절연막(3C)을 형성하고, 상기 폴리플러그(4A) 상부의 층간절연막(3B,3C)을 식각하여 제3비아콘택 홀을 형성한 후, 그 폴리플러그(4A)와 접속되도록 스토리지 노드(6)를 형성하는 공정(도1d)과; 그 스토리지 노드(6)의 노출된 표면에 유전막(7)과 플레이트 전극(8)을 순차적으로 형성하는 공정(도1e)과; 그 플레이트 전극(8)이 형성된 층간절연막(3C)의 상부에 층간절연막(3D)을 형성하고, 상기 층간절연막(3D∼3A)의 일부를 식각하여 제4비아콘택 홀을 형성한 후, 상기 반도체기판(1)과 접속되도록 국부 접속층(9)을 형성하는 공정(도1f)으로 이루어진다. 이하, 상기한 바와같은 종래 디램의 커패시터 제조방법을 좀더 상세히 설명한다.1A to 1F are cross-sectional views illustrating a conventional method of manufacturing a capacitor of a DRAM, and as shown therein, an interlayer insulating film formed on an upper portion of a semiconductor substrate 1 having gates 2A, 2B, and 2C formed in a cell region and a peripheral circuit region. (3A) forming step (FIG. 1A); Etching a part of the interlayer insulating film 3A to form a first via contact hole, and then filling polysilicon in the first via contact hole to form poly plugs 4A and 4B (FIG. 1B); An interlayer insulating film 3B is formed on the interlayer insulating film 3A on which the poly plugs 4A and 4B are formed, and the interlayer insulating film 3B on the polyplug 4B is etched to form a second via contact hole. And then forming a bit line 5 so as to be connected to the polyplug 4B (Fig. 1C); An interlayer insulating film 3C is formed on the interlayer insulating film 3B on which the bit line 5 is formed, and the third via contact hole is formed by etching the interlayer insulating films 3B and 3C on the polyplug 4A. Thereafter, forming the storage node 6 to be connected to the polyplug 4A (Fig. 1D); Sequentially forming the dielectric film 7 and the plate electrode 8 on the exposed surface of the storage node 6 (FIG. 1E); After the interlayer insulating film 3D is formed on the interlayer insulating film 3C on which the plate electrode 8 is formed, a portion of the interlayer insulating films 3D to 3A is etched to form a fourth via contact hole, and then the semiconductor is formed. The process of forming the local connection layer 9 so as to be connected to the substrate 1 (FIG. 1F). Hereinafter, a method of manufacturing a capacitor of a conventional DRAM as described above will be described in more detail.
먼저, 도1a에 도시한 바와같이 소정거리 이격되어 게이트(2A,2B,2C)가 형성된 반도체기판(1)의 상부에 층간절연막(3A)을 형성한다. 이때, 디램 셀은 하나의 커패시터와 패스 트랜지스터로 이루어지므로 반도체기판(1) 상에는 웰영역, 소스/드레인영역 및 분리영역이 형성되어 있지만 설명의 단순화를 꾀하기 위해 생략하였다. 그리고, 상기 층간절연막(3A)은 콘택 홀을 통해 반도체기판(1)의 상부에 형성되는 층간을 선택적으로 접속시키고 아울러 평탄화를 도모하기 위해 형성한다.First, as shown in FIG. 1A, an interlayer insulating film 3A is formed on the semiconductor substrate 1 on which the gates 2A, 2B, and 2C are formed at a predetermined distance apart. In this case, since the DRAM cell includes one capacitor and a pass transistor, a well region, a source / drain region, and an isolation region are formed on the semiconductor substrate 1, but are omitted for simplicity of explanation. The interlayer insulating film 3A is formed to selectively connect the interlayers formed on the upper portion of the semiconductor substrate 1 through contact holes and to planarize.
그 다음, 도1b에 도시한 바와같이 층간절연막(3A)의 일부를 식각하여 제1비아콘택 홀을 형성한 후, 그 제1비아콘택 홀에 폴리실리콘을 채워서 폴리플러그(4A,4B)를 형성한다. 이때, 폴리플러그(4A,4B)는 이후에 반도체기판(1)의 소스와 드레인에 접속되는 스토리지 노드(6)와 비트라인(5)을 형성하기 위한 제2비아콘택 홀의 형성시 공정마진(margin)을 확보하기 위해서 층간절연막(3A)의 상부까지 증착한 후, 에치백(etch-back)공정을 수행하여 형성한다.Next, as shown in FIG. 1B, a portion of the interlayer insulating film 3A is etched to form a first via contact hole, and then polysilicon is filled in the first via contact hole to form polyplugs 4A and 4B. do. In this case, the polyplugs 4A and 4B may have a process margin when forming the second via contact hole for forming the storage node 6 and the bit line 5, which are subsequently connected to the source and drain of the semiconductor substrate 1. In order to secure), it is formed by depositing the upper portion of the interlayer insulating film 3A and then performing an etch-back process.
그 다음, 도1c에 도시한 바와같이 폴리플러그(4A,4B)가 형성된 층간절연막(3A)의 상부에 층간절연막(3B)을 형성하고, 상기 폴리플러그(4B) 상부의 층간절연막(3B)를 식각하여 제2비아콘택 홀을 형성한 후, 그 폴리플러그(4B)와 접속되도록 비트라인(5)을 형성한다. 이때, 비트라인(5)은 층간절연막(3B)의 상부까지 증착한 후, 패터닝을 통해 적절한 면적으로 형성한다.Then, as shown in Fig. 1C, an interlayer insulating film 3B is formed on the interlayer insulating film 3A on which the poly plugs 4A and 4B are formed, and the interlayer insulating film 3B on the polyplug 4B is formed. After etching to form the second via contact hole, the bit line 5 is formed to be connected to the poly plug 4B. At this time, the bit line 5 is deposited to the upper portion of the interlayer insulating film 3B, and then formed into an appropriate area by patterning.
그 다음, 도1d에 도시한 바와같이 비트라인(5)이 형성된 층간절연막(3B)의 상부에 층간절연막(3C)을 형성하고, 상기 폴리플러그(4A) 상부의 층간절연막(3B,3C)을 식각하여 제3비아콘택 홀을 형성한 후, 그 폴리플러그(4A)와 접속되도록 스토리지 노드(6)를 형성한다. 이때, 스토리지 노드(6)는 폴리실리콘을 층간절연막(3C)의 상부까지 증착한 후, 패터닝을 통해 적절한 면적으로 형성하며, 층간절연막(3C)의 상부에 노출되는 폴리실리콘의 면적에 따라 제조되는 커패시터의 커패시턴스가 변화하므로 이를 고려해야 한다.Next, as shown in FIG. 1D, an interlayer insulating film 3C is formed on the interlayer insulating film 3B on which the bit lines 5 are formed, and the interlayer insulating films 3B and 3C on the polyplug 4A are formed. After etching to form the third via contact hole, the storage node 6 is formed to be connected to the polyplug 4A. In this case, the storage node 6 deposits polysilicon up to the upper portion of the interlayer insulating layer 3C, and then forms a suitable area through patterning, and is manufactured according to the area of the polysilicon exposed to the upper portion of the interlayer insulating layer 3C. This should be taken into account as the capacitance of the capacitor changes.
그 다음, 도1e에 도시한 바와같이 스토리지 노드(6)의 노출된 표면에 유전막(7)과 플레이트 전극(8)을 순차적으로 형성한다. 이때, 플레이트 전극(8)은 폴리실리콘을 유전막(7) 및 층간절연막(3C)의 상부에 원하는 두께로 형성한 후, 패터닝을 통해 적절한 면적으로 형성한다.Next, as shown in FIG. 1E, the dielectric film 7 and the plate electrode 8 are sequentially formed on the exposed surface of the storage node 6. At this time, the plate electrode 8 is formed on the dielectric film 7 and the interlayer insulating film 3C to the desired thickness on the polysilicon, and then formed into a suitable area by patterning.
그 다음, 도1f에 도시한 바와같이 플레이트 전극(8)이 형성된 층간절연막(3C)의 상부에 층간절연막(3D)를 형성하고, 상기 층간절연막(3D∼3A)의 일부를 식각하여 제4비아콘택 홀을 형성한 후, 상기 반도체기판(1)과 접속되도록 국부 접속층(9)을 형성한다. 이때, 국부 접속층(9)은 주변회로, 센스앰프(sense amplifier) 및 서브 워드라인 드라이버(sub wordline driver)에서 국부적인 회로연결을 통해 칩 사이즈를 감소시키기 위한 목적으로 형성한다.Next, as shown in FIG. 1F, an interlayer insulating film 3D is formed on the interlayer insulating film 3C on which the plate electrode 8 is formed, and a portion of the interlayer insulating films 3D to 3A is etched to form a fourth via. After the contact hole is formed, the local connection layer 9 is formed to be connected to the semiconductor substrate 1. At this time, the local connection layer 9 is formed for the purpose of reducing the chip size through local circuit connection in the peripheral circuit, sense amplifier, and sub wordline driver.
이후, 배선공정 및 패시베이션(passivation)공정을 수행하여 디램제조를 완료한다.Thereafter, a wiring process and a passivation process are performed to complete DRAM manufacturing.
그러나, 상기한 바와같은 종래 디램의 커패시터 제조방법은 커패시터의 형성을 위해 3회의 사진식각공정이 요구되고, 국부 접속층의 형성을 위해 2회의 사진식각공정이 요구되어 공정이 복잡하고, 제조단가가 상승하는 문제점이 있었다.However, the conventional method of manufacturing a capacitor of a DRAM as described above requires three photolithography processes to form a capacitor, and two photolithography processes are required to form a local connection layer, which makes the process complicated. There was a rising issue.
본 발명은 상기한 바와같은 종래의 문제점을 해결하기 위하여 창안한 것으로, 본 발명의 목적은 커패시터 제조공정중에 칩 사이즈를 줄이기 위해 사용되는 국부 접속층과 커패시터의 플레이트 전극을 동일한 물질로 사용하여 공정의 단순화를 꾀할 수 있는 디램의 커패시터 제조방법을 제공하는데 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the conventional problems as described above, and an object of the present invention is to use a local connection layer and a plate electrode of a capacitor as the same material to reduce chip size during a capacitor manufacturing process. It is to provide a method of manufacturing a capacitor of the DRAM that can be simplified.
도1은 종래 디램의 커패시터 제조방법을 보인 수순단면도.1 is a cross-sectional view showing a method of manufacturing a capacitor of a conventional DRAM.
도2는 본 발명의 일 실시예를 보인 수순단면도.Figure 2 is a cross-sectional view showing an embodiment of the present invention.
***도면의 주요 부분에 대한 부호의 설명****** Description of the symbols for the main parts of the drawings ***
1:반도체기판 2A∼2C:게이트1: semiconductor substrate 2A to 2C: gate
3A∼3C:층간절연막 4A,4B:폴리플러그3A to 3C: Interlayer insulating film 4A, 4B: Poly plug
5:비트라인 6:스토리지 노드5: bit line 6: storage node
7:유전막 8:플레이트 전극7: Dielectric film 8: Plate electrode
9:국부접속층9: Local connection layer
상기한 바와같은 본 발명의 목적을 달성하기 위한 디램의 커패시터 제조방법은 반도체기판의 상부를 제1층간절연막을 통해 평탄화시키는 공정과; 상기 제1층간절연막의 일부를 식각하여 형성된 제1비아콘택 홀에 폴리실리콘을 채워서 제1,제2폴리플러그를 형성하는 공정과; 상기 제1층간절연막의 상부에 제2층간절연막을 형성하고, 제2폴리플러그 상부의 제2층간절연막을 식각하여 형성된 제2비아콘택 홀에 비트라인을 형성하는 공정과; 상기 제2층간절연막의 상부에 제3층간절연막을 형성하고, 제1폴리플러그 상부의 제3,제2층간절연막을 식각하여 형성된 제3비아콘택 홀에 스토리지 노드를 형성하는 공정과; 상기 스토리지 노드가 형성된 반도체기판의 전면에 유전막을 증착한 후, 주변회로 영역의 제3∼제1층간절연막을 식각하여 제4비아콘택 홀을 형성하는 공정과; 상기 스토리지 노드가 형성된 유전막의 상부 및 제4비아콘택 홀에 금속물질을 증착하여 플레이트 전극 및 국부접속층을 형성하는 공정을 구비하여 이루어짐을 특징으로 한다.A method of manufacturing a capacitor of a DRAM for achieving the object of the present invention as described above comprises the steps of planarizing the upper portion of the semiconductor substrate through the first interlayer insulating film; Forming first and second polyplugs by filling polysilicon in a first via contact hole formed by etching a portion of the first interlayer dielectric layer; Forming a second interlayer insulating layer on the first interlayer insulating layer, and forming a bit line in a second via contact hole formed by etching the second interlayer insulating layer on the second polyplug; Forming a third interlayer dielectric layer on the second interlayer dielectric layer, and forming a storage node in a third via contact hole formed by etching the third and second interlayer dielectric layers on the first polyplug; Depositing a dielectric film on the entire surface of the semiconductor substrate on which the storage node is formed, and then etching the third to first interlayer insulating films in the peripheral circuit region to form a fourth via contact hole; And forming a plate electrode and a local connection layer by depositing a metal material on the upper portion of the dielectric layer on which the storage node is formed and the fourth via contact hole.
이하, 상기한 바와같은 본 발명에 의한 디램의 커패시터 제조방법의 바람직할 일 실시예를 첨부한 도2a 내지 도2f의 수순단면도를 참조하여 상세히 설명한다.Hereinafter, a detailed cross-sectional view of FIGS. 2A to 2F will be described in detail with reference to the accompanying drawings.
먼저, 도2a 내지 도2c에 도시한 비트라인(5)이 형성되기까지의 공정순서는 종래 도1a 내지 도1c를 설명한 공정순서와 동일하므로 여기서는 상세한 설명을 생략하기로 하고, 도2d부터 살펴보기로 한다.First, since the process sequence until the bit line 5 shown in FIGS. 2A to 2C is formed is the same as the process procedure described with reference to FIGS. 1A to 1C, a detailed description thereof will be omitted here. Shall be.
도2d를 살펴보면, 비트라인(5)이 형성된 층간절연막(3B)의 상부에 층간절연막(3C)을 형성하고, 폴리플러그(4A) 상부의 층간절연막(3C,3B)을 식각하여 형성된 제3비아콘택 홀에 스토리지 노드(6)를 형성한다.Referring to FIG. 2D, a third via formed by forming an interlayer insulating film 3C on the interlayer insulating film 3B on which the bit lines 5 are formed and etching the interlayer insulating films 3C and 3B on the polyplug 4A. The storage node 6 is formed in the contact hole.
이때, 상기 스토리지 노드(6)를 형성하는 공정은 상기 제3비아콘택 홀에 의해 노출된 폴리플러그(4A)를 블랭킷(blanket) 식각하는 단계와, 상기 제3비아콘택 홀 폭의 절반보다는 얇게 반도체기판(1)의 전면에 폴리실리콘을 증착한 후, 화학기계적 연마공정(CMP) 또는 에치백(etch-back)을 수행하는 단계로 이루어지며, 상기 제3비아콘택 홀 폭의 절반보다는 얇게 폴리실리콘을 증착함에 따라 그 제3비아콘택 홀이 완전히 채워지는 것을 방지할 수 있고, 상기 폴리플러그(4A)를 블랭킷 식각하여 제3비아콘택 홀을 깊게 형성함에 따라 스토리지 노드(6)의 면적이 보다 넓어져 커패시턴스를 증가시킬 수 있게 된다.In this case, the forming of the storage node 6 may include blanket etching the polyplug 4A exposed by the third via contact hole, and forming a semiconductor thinner than half the width of the third via contact hole. After depositing polysilicon on the entire surface of the substrate 1, and performing a chemical mechanical polishing process (CMP) or etch-back (poly-silicon), the polysilicon thinner than half the width of the third via contact hole The third via contact hole may be prevented from being completely filled by depositing the third via contact hole, and the area of the storage node 6 may be larger by blanket etching the polyplug 4A to form the third via contact hole. It is possible to increase the capacitance.
한편, 상기 블랭킷 식각은 식각선택성이 우수한 물질을 사용하여 폴리플러그(4A)만을 소정깊이로 식각하고 층간절연막(3C)은 거의 식각되지 않도록 하며, 상기 스토리지 노드(6)를 형성하기 위한 폴리실리콘은 표면에 요철을 갖는 러기드(rugged) 폴리실리콘을 사용하면 표면적이 보다 넓어짐으로써 커패시턴스를 증가시킬 수 있게 된다.Meanwhile, the blanket etching may be performed using only a material having excellent etching selectivity to etch only the poly plug 4A to a predetermined depth and hardly etch the interlayer insulating layer 3C, and the polysilicon for forming the storage node 6 may be The use of rugged polysilicon having irregularities on the surface makes it possible to increase the capacitance by increasing the surface area.
그리고, 도2e에 도시한 바와같이, 상기 스토리지 노드(6)가 형성된 반도체기판(1)의 전면에 유전막(7)을 증착한 후, 주변회로 영역의 층간절연막(3C∼3A)을 식각하여 제4비아콘택 홀을 형성한다.As shown in FIG. 2E, after the dielectric film 7 is deposited on the entire surface of the semiconductor substrate 1 on which the storage node 6 is formed, the interlayer insulating films 3C to 3A in the peripheral circuit region are etched to form a first film. Four via contact holes are formed.
그리고, 도2f에 도시한 바와같이, 상기 스토리지 노드(6)가 형성된 유전막(7)의 상부 및 제4비아콘택 홀에 금속물질을 증착하여 플레이트 전극(8) 및 국부접속층(9)을 형성한다.As shown in FIG. 2F, a metal material is deposited on the fourth via contact hole and the upper portion of the dielectric layer 7 on which the storage node 6 is formed to form the plate electrode 8 and the local connection layer 9. do.
이와같이 셀영역에 형성되는 플레이트 전극(8)과 주변회로 영역에 형성되는 국부접속층(9)을 금속물질을 사용하여 동시에 형성하게 된다.In this way, the plate electrode 8 formed in the cell region and the local connection layer 9 formed in the peripheral circuit region are simultaneously formed using a metal material.
상기한 바와같은 본 발명에 의한 디램의 커패시터 제조방법은 스토리지 노드의 표면적을 최대한 넓게 하여 커패시턴스를 증가시킬 수 있고, 플레이트 전극과 주변회로 영역에 형성되는 국부접속층을 금속물질을 사용하여 동시에 형성함에 따라 종래의 플레이트 전극 형성을 위한 폴리실리콘 증착 및 사진식각공정을 생략할 수 있고, 플레이트 전극 형성후에 국부접속층 형성을 위한 제4층간절연막의 증착공정을 생략할 수 있게 되어 공정의 단순화에 기여함으로써, 제조비용을 절감할 수 있는효과가 있다.The method of manufacturing a capacitor of a DRAM according to the present invention as described above can increase the capacitance by increasing the surface area of the storage node as much as possible, and simultaneously form a local connection layer formed on the plate electrode and the peripheral circuit region using a metal material. Accordingly, the conventional polysilicon deposition and photolithography process for forming the plate electrode can be omitted, and the deposition process of the fourth interlayer dielectric film for forming the local connection layer can be omitted after the plate electrode is formed, thereby contributing to the simplification of the process. As a result, manufacturing costs can be reduced.
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