KR20030033697A - A semiconductor device and A method for manufacturing the same - Google Patents

Abstract

PURPOSE: A semiconductor device and a manufacturing method thereof are provided to improve the step coverage between a DRAM(Dynamic Random Access Memory) cell and peripheral region, and a logic region and to reduce manufacturing processes by simultaneously forming a plate electrode of a capacitor and the first metal wiring. CONSTITUTION: A lower isolating layer having a storage electrode(44) is formed on the upper portion of a semiconductor substrate(40) divided into a DRAM cell and peripheral region(I,II), and a logic region(III). After forming a dielectric layer(45) on the resultant structure, the first metal layer is formed on the entire surface of the resultant structure for contacting the semiconductor substrate and lower structure bodies(42,43) through the dielectric layer(45) and lower isolating layer. A plate electrode(48) and the first metal wiring(49) are simultaneously formed by patterning the first metal layer.

Description

A semiconductor device and a method for manufacturing the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, a DRAM cell region, a DRAM peripheral circuit region, and a process step during a multilayer metallization forming process in a DRAM DRAM fabricated process. A method of reducing the step between logic regions.

In general, the wiring of a semiconductor device for electrically connecting between devices or between an element and an external circuit is formed by filling a predetermined contact hole and via hole for wiring with a wiring material, forming a wiring layer, and performing a subsequent process. Metal wiring is used where resistance is required.

The metal wiring includes a small amount of silicon or copper (Cu) in aluminum (Al), or both silicon and copper, and has a low resistivity and excellent workability. PVD) is formed by the method of filling the contact hole and the via hole by sputtering.

The polysilicon layer used as the storage electrode is connected to the junction region or the bit line to bias the ground voltage or negative voltage, and to bias the positive voltage on the plate electrode. It is common. At this time, the voltage for forming a conducting channel between the two electrodes by causing the dielectric film to break is required at least 7V.

When biasing the positive voltage to the plate electrode, the positive voltage is biased while being connected to the pad using a metal wiring contact. At this time, since the movement of electrons is faster than the hole, a positive voltage is applied to the plate electrode.

When a high voltage is applied between the metallization contact and the plate electrode, a cut-off phenomenon occurs in which the plate electrode melts due to thermal damage or increased resistance. That is, the dielectric film must be destroyed, but the plate electrode melts first, so that the device cannot be used.

Hereinafter, with reference to the accompanying drawings will be described in the prior art.

1A to 1G are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

First, a device isolation insulating film 11 defining an active region is formed in a semiconductor substrate 10 divided into a DRAM cell region I, a DRAM peripheral circuit region II, and a logic region III.

Next, a word line 12, a bit line 13, and a storage electrode 14 are formed on the semiconductor substrate 10. At this time, the storage electrode 14 is formed only in the DRAM cell region (I). (See Figure 1A)

Next, a conductive layer for the dielectric film and the plate electrode is formed on the entire surface, and the conductive layer and the dielectric film for the plate electrode are etched by a photolithography process using a plate electrode mask to form the dielectric film pattern 15 and the plate electrode 16. ). In this case, the plate electrode 16 is formed of a polysilicon layer, and the dielectric film pattern 15 and the plate electrode 16 are formed on the DRAM cell region I and the DRAM peripheral circuit region II. (See FIG. 1B)

Next, the interlayer insulating film 17 is formed over the entire surface, and then the planarization process is performed. At this time, even after the planarization process, a step of 'H' occurs between the DRAM cell region I, the DRAM peripheral circuit region II, and the logic region III. (See Figure 1C)

Next, the first interlayer insulating layer 17 is etched by a photolithography process using a first metal wiring contact mask to form a first metal wiring contact hole 18. In this case, the first metal wiring contact hole 18 is formed on the plate electrode 16, the bit line 13 and the word line 12 on the DRAM peripheral circuit region II, and the word on the logic region III. It is formed on the line 12 and the active region. (See FIG. 1D)

Next, a first metal wiring contact plug 19 is formed to fill the first metal wiring contact hole 18. (See Figure 1E)

Next, a first metal layer (not shown) is formed on the entire surface, and the first metal layer is etched by a photolithography process using a first metal wiring mask to be connected to the first metal wiring contact plug 19. 1 metal wiring 20 is formed. (See Figure 1f)

Next, a second interlayer insulating film 21 is formed over the entire surface.

Next, the photolithography process using a second metal wiring contact mask exposing a portion of the DRAM cell region I, the DRAM peripheral circuit region II, and the logic region III to be a second metal wiring contact. The second interlayer insulating film 21 is etched to form a second metal wiring contact hole (not shown).

Next, a second metal wiring contact plug 22 connected to the first metal wiring 20 through the second metal wiring contact hole is formed.

A second metal layer (not shown) is then formed over the entire surface.

Next, the second metal layer is formed by a photolithography process using a second metal wiring mask to protect a portion of the DRAM cell region (I), the DRAM peripheral circuit region (II), and the logic region (III) that are intended as a second metal wiring. Etching to form a second metal wiring (23).

Then, a third interlayer insulating film 24 is formed over the entire surface.

Next, the third interlayer dielectric layer 24 is etched by a photolithography process using a third metal interconnect contact mask exposing a portion of the logic region III to be a third metal interconnect contact. (Not shown).

Next, a third metal wiring contact plug 24 connected to the second metal wiring 23 through the third metal wiring contact hole is formed.

Next, a third metal wiring 26 connected to the third metal wiring contact plug 24 is formed.

Thereafter, a fourth interlayer insulating film 27 is formed.

Next, the fourth interlayer insulating layer 27 is etched by a photolithography process using a fourth metal wiring contact mask exposing a portion of the logic region III to be a fourth metal wiring contact. (Not shown).

Next, a fourth metal wiring contact plug 28 connected to the third metal wiring 26 through the fourth metal wiring contact hole is formed.

Next, the fourth metal wiring 29 is connected to the fourth metal wiring contact plug 28. (See Figure 1g)

As described above, the semiconductor device and the method of manufacturing the same according to the related art have a higher step height than the DRAM peripheral circuit area and the logic area in which the DRAM cell region in which the capacitor is formed are higher in the DRAM cell area and the DRAM in the subsequent multilayer metallization process. Due to the metal etching residue at the interface of the peripheral circuit region, there is a problem of causing leakage current between the metal wirings and making the exposure process difficult during the mask process, thereby reducing the reproducibility of the device. In addition, since the second metal wiring is formed on the DRAM cell region and the DRAM peripheral circuit region, and the fourth metal wiring or more is formed on the logic region, the process is complicated.

In order to solve the above problems of the prior art, the first metal wiring is simultaneously formed during the plate electrode formation process of the capacitor in the manufacturing process of the DRAM logic composite semiconductor device, thereby forming a gap between the DRAM cell region, the DRAM peripheral circuit region, and the logic region. SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device and a method of manufacturing the same, which improve the process yield and reliability of the semiconductor device by reducing the step and reducing the metal wiring forming step, thereby simplifying the process and securing the process margin.

1A to 1G are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

2A to 2G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

<Brief description of the main parts of the drawing>

10, 40: semiconductor substrate 11, 41: device isolation insulating film

12, 42: word line 13, 33: bit line

14, 44: storage electrode 15, 45: dielectric film pattern

16, 48: plate electrodes 17, 50: first interlayer insulating film

18, 46: first metal wiring contact hole 19, 52: first metal wiring contact plug

20, 49, 63: first metal wiring 21, 54: second interlayer insulating film

22, 55: second metal wiring contact plug 23, 53, 66: second metal wiring

24, 57: third interlayer insulating film 25, 58: third metal wiring contact plug

26, 56: 3rd metal wiring 27: 4th interlayer insulation film

28: fourth metal wiring contact plug 29, 59: fourth metal wiring

47: first metal layer

The semiconductor device according to the present invention for achieving the above object,

And a plate electrode formed of the same material as the first metal wiring of the peripheral circuit area and the logic area of the DRAM.

In addition, the manufacturing method of the semiconductor device according to the present invention in order to achieve the above object,

Forming a lower insulating film having a storage electrode on the semiconductor substrate including a DRAM cell region, a DRAM peripheral circuit region, and a logic region;

Forming a dielectric film over the entire surface;

Forming a first metal layer on the entire surface of the first circuit layer connected to the semiconductor substrate or the lower structure through the dielectric film formed in the peripheral circuit region and the logic region and the lower insulating film;

The first metal layer is patterned by a photolithography process using a plate electrode mask and a first metal wiring mask to simultaneously form a plate electrode and a first metal wiring.

Hereinafter, with reference to the accompanying drawings will be described the present invention.

2A to 2G are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.

First, a device isolation insulating film 41 defining an active region is formed in the semiconductor substrate 40 including the DRAM cell region I, the DRAM peripheral circuit region II, and the logic region III.

Next, a lower insulating layer having a lower structure such as a word line 42, a bit line 43, and a storage electrode 44 is formed on the semiconductor substrate 40. (See Figure 2A)

Next, a dielectric film 45 is formed over the entire surface.

Next, the lower insulating layer is etched by a photolithography process using a first metal wiring contact mask that exposes portions of the DRAM peripheral circuit region (II) and the logic region (III) to be the first metal wiring contact. The contact hole 46 is formed. (See Figure 2b)

Next, the first metal layer 47 is formed over the entire surface. In this case, the first metal layer 47 is formed in a stacked structure of Ti / TiN / Al / Ti / TiN by using a CVD method. (See Figure 2c)

Next, a portion intended as a plate electrode in the DRAM cell region I and the DRAM peripheral circuit region II is protected, and at the same time, a first metal wiring in the DRAM peripheral circuit region II and the logic region III is intended. The first metal layer 47 is etched to form a plate electrode 48 and a first metal wiring 49 by a photolithography process using an etching mask to protect portions. (See FIG. 2D)

Next, a first interlayer insulating film 50 is formed over the entire surface. In this case, it can be seen that the step between the DRAM cell region I, the DRAM peripheral circuit region II, and the logic region III is 'h', which is alleviated compared to the prior art. (See Figure 2E)

Next, a portion of the DRAM cell region (I) and the DRAM peripheral circuit region (II), which are intended as a first metal wiring contact, over the entire surface, and the second metal in the DRAM peripheral circuit region (II) and the logic region (III). The first interlayer insulating layer 50 is etched to form a second metal wiring contact hole (not shown) by a photolithography process using a second metal wiring contact mask that exposes a predetermined portion of the wiring contact.

Next, a first metal wire contact plug 52 connected to the first metal wire 49 and the plate electrode 48 is formed through the second metal wire contact hole.

Next, a second metal layer (not shown) is formed over the entire surface.

Next, a second metal wiring that protects the portion of the DRAM cell region (I), which is intended as the first metal wiring, and the portion of the DRAM peripheral circuit region (II) and the logic region (III), which is intended as the second metal wiring. The second metal layer is etched by a photolithography process using a mask to form a first metal wiring 63 and a second metal wiring 53.

Next, a second interlayer insulating film 54 is formed over the entire surface.

Next, a portion of the DRAM cell region (I) and the DRAM peripheral circuit region (II) that are supposed to be the second metal wiring contacts, and the DRAM peripheral circuit region (II) and the logic region (III) to the third metal wiring contact. A second metal interconnect contact hole (not shown) is formed by etching the second interlayer insulating layer 54 by a photolithography process using an etching mask using a third metal interconnect contact mask that exposes a predetermined portion.

Next, a second metal wire contact plug 55 connected to the first metal wire 63 and the second metal wire 53 through the second metal wire contact hole is formed.

A third metal layer (not shown) is then formed over the entire surface.

Next, a portion intended as the second metal wiring in the DRAM cell region I and the DRAM peripheral circuit region II, and a portion intended as the third metal wiring in the DRAM peripheral circuit region II and the logic region III. The third metal layer is etched by a photolithography process using a third metal wiring mask to expose the second metal wiring 66 and the third metal wiring 56.

Next, a third interlayer insulating film 57 is formed over the entire surface.

Next, the third interlayer dielectric layer 57 is etched by a photolithography process using a fourth metal interconnection contact mask exposing a portion of the logic region III to be a fourth metal interconnection contact. (Not shown).

Next, a third metal wiring contact plug 58 connected to the third metal wiring 56 through the third metal wiring contact hole is formed.

Next, a fourth metal layer (not shown) is formed over the entire surface.

Next, the fourth metal layer is etched by a photolithography process using a fourth metal wiring mask that protects a portion of the logic region III that is supposed to be the fourth metal wiring. The fourth metal wire 59 is formed to be connected to the third metal wire 56 through the second metal wire 59. (See Figure 2g)

As described above, the method of manufacturing a semiconductor device according to the present invention includes forming a plate electrode and a first metal wiring of a capacitor on a DRAM peripheral circuit region and a logic region at the same time. By reducing the step difference between the logic regions to prevent the leakage current caused by the etch residues, it is easy to follow-up photographic process, simplify the process and thereby improve the reliability and process yield of the semiconductor device.

Claims (6)

A semiconductor device comprising a plate electrode formed of the same material as the first metal wiring of the peripheral circuit area and the logic area of the DRAM. The method of claim 1, And the plate electrode is made of Al. Forming a lower insulating film having a storage electrode on the semiconductor substrate including a DRAM cell region, a DRAM peripheral circuit region, and a logic region; Forming a dielectric film over the entire surface; Forming a first metal layer on the entire surface of the first circuit layer connected to the semiconductor substrate or the lower structure through the dielectric film formed in the peripheral circuit region and the logic region and the lower insulating film; A method of manufacturing a semiconductor device, comprising forming a plate electrode and a first metal wiring at the same time by patterning the first metal layer by a photolithography process using a plate electrode mask and a first metal wiring mask. The method of claim 3, wherein The first metal layer is a method of manufacturing a semiconductor device, characterized in that formed using Al. The method of claim 4, wherein The first metal layer is a method of manufacturing a semiconductor device, characterized in that formed by the CVD method. The method of claim 3, wherein After forming the interlayer insulating film to planarize the surface of the first metal layer and the plate electrode to form a second metal layer that is connected to the first metal layer and the plate electrode through the photolithography process using a second metal wiring mask through the cell region, A method of manufacturing a semiconductor device, comprising forming a second metal wiring in a peripheral circuit region and a logic region.