KR100546143B1 - Method for forming conductive wiring in semiconductor device - Google Patents
Method for forming conductive wiring in semiconductor device Download PDFInfo
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- KR100546143B1 KR100546143B1 KR1019980062036A KR19980062036A KR100546143B1 KR 100546143 B1 KR100546143 B1 KR 100546143B1 KR 1019980062036 A KR1019980062036 A KR 1019980062036A KR 19980062036 A KR19980062036 A KR 19980062036A KR 100546143 B1 KR100546143 B1 KR 100546143B1
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- storage electrode
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- bit line
- conductive layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/485—Bit line contacts
Abstract
본 발명은 반도체소자의 도전배선 형성방법에 관한 것으로, 반도체기판 상부에 하부 도전층을 일정두께 형성하고 하부 도전층 패턴마스크와 상부 도전층 패턴마스크를 이용하여 상기 하부도전층을 패터닝하고, 후속공정으로 상기 상부 도전층 패턴마스크를 이용하여 패터닝된 하부 도전층에 접속되는 상부 도전층을 형성함으로써 상부 도전층과 하부 도전층의 브릿지 ( bridge ) 현상을 방지하고 그에 따른 반도체소자의 고집적화를 가능하게 하는 기술이다. The present invention relates to a method for forming a conductive wiring of a semiconductor device, wherein a lower conductive layer is formed on the semiconductor substrate to a predetermined thickness, and the lower conductive layer is patterned by using a lower conductive layer pattern mask and an upper conductive layer pattern mask. By forming the upper conductive layer connected to the patterned lower conductive layer using the upper conductive layer pattern mask to prevent the bridge phenomenon of the upper conductive layer and the lower conductive layer, thereby enabling high integration of the semiconductor device Technology.
Description
본 발명은 반도체소자의 도전배선 형성방법에 관한 것으로, 특히 고집적화에 따라 유발될 수 있는 도전배선 간의 브릿지 ( bridge ) 를 방지하는 방법에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming conductive wiring in a semiconductor device, and more particularly, to a method for preventing a bridge between conductive wirings that can be caused by high integration.
반도체 메모리 소자의 도전배선으로는 워드라인, 비트라인 및 금속배선 등이 있으며 캐패시터와 같이 도전물질로 형성하는 캐패시터가 있다. The conductive wirings of semiconductor memory devices include word lines, bit lines, and metal wirings, and capacitors formed of conductive materials such as capacitors.
일반적인 반도체 메모리 소자인 디램은 반도체기판 상부에 소자분리막을 형성하고, 활성영역에 워드라인을 형성한 다음, 상기 워드라인 상부에 평탄화된 하부절연층을 형성하고 상기 반도체기판에 접속되는 비트라인을 형성한 다음, 그 상부를 평탄화시키는 층간절연막을 형성하고 상기 반도체기판에 접속되는 저장전극을 형성한 다음, 상부를 평탄화시키는 다른 층간절연막을 형성하고 상기 반도체기판에 접속되는 금속배선을 형성하였다. A DRAM, which is a general semiconductor memory device, forms a device isolation layer on a semiconductor substrate, a word line on an active region, a flattened lower insulating layer on the word line, and a bit line connected to the semiconductor substrate. Next, an interlayer insulating film was formed to planarize an upper portion thereof, a storage electrode connected to the semiconductor substrate was formed, and another interlayer insulating film was formed to planarize an upper portion thereof, and a metal wiring connected to the semiconductor substrate was formed.
그러나, 반도체소자가 고집적화됨에따라 비트라인과 워드라인 간의 거리가 좁아져 브릿지가 유발될 수 있게 되었다. However, as the semiconductor devices are highly integrated, the distance between the bit lines and the word lines is narrowed, which may cause bridges.
도 1 은 종래기술에 따른 반도체소자의 도전배선 형성방법을 도시한 단면도이다. 1 is a cross-sectional view illustrating a method for forming conductive wirings of a semiconductor device according to the prior art.
먼저, 반도체기판(41) 상부에 활성영역을 정의하는 소자분리막(43)을 형성한다. First, an isolation layer 43 defining an active region is formed on the semiconductor substrate 41.
그리고, 상기 반도체기판(41) 상에 워드라인(도시안됨)을 형성하고, 후속공정으로 형성될 비트라인과 저장전극의 콘택패드(45)를 동시에 형성한다. A word line (not shown) is formed on the semiconductor substrate 41, and a bit line to be formed in a subsequent process and a contact pad 45 of the storage electrode are simultaneously formed.
그리고, 상기 비트라인 콘택패드(45)에 접속되는 비트라인(47)이 구비되는 하부절연층(49)을 형성하고, 상기 저장전극 콘택패드(45)를 노출시키는 저장전극 콘택홀(51)을 형성한다. In addition, a lower insulating layer 49 having a bit line 47 connected to the bit line contact pad 45 is formed, and the storage electrode contact hole 51 exposing the storage electrode contact pad 45 is formed. Form.
그리고, 상기 저장전극 콘택홀(51)을 통하여 상기 콘택패드(45)에 접속되는 저장전극(53)을 형성한다. (도 1)In addition, a storage electrode 53 connected to the contact pad 45 through the storage electrode contact hole 51 is formed. (Figure 1)
상기한 바와같이 종래기술에 따른 반도체소자의 도전배선 형성방법은, 도 1 의 ⓐ 부분과 같이 비트라인과 저장전극(53) 사이의 간격이 좁아 오정렬시 브릿지가 유발될 수 있으므로 정렬마진이 감소하여 반도체소자의 고집적화를 어렵게 하는 문제점이 있다. As described above, in the method of forming conductive wirings of the semiconductor device according to the related art, as shown in ⓐ in FIG. There is a problem that makes it difficult to integrate the semiconductor device.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 콘택플러그에 접속되는 비트라인과 저장전극 마스크를 이용하여 비트라인의 형성공정시 패터닝함으로써 비트라인과 저장전극의 오정렬로 인한 브릿지를 방지할 수 있어 반도체소자의 고집적화를 가능하게 하는 반도체소자의 도전배선 형성방법을 제공하는데 그 목적이 있다. The present invention can prevent the bridge due to misalignment of the bit line and the storage electrode by patterning during the formation of the bit line using the bit line and the storage electrode mask connected to the contact plug to solve the above problems of the prior art. Accordingly, an object of the present invention is to provide a method for forming a conductive wiring of a semiconductor device that enables high integration of the semiconductor device.
이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 도전배선 형성방법은, In order to achieve the above object, the conductive wiring forming method of the semiconductor device according to the present invention,
반도체기판의 불순물 접합영역에 접속되는 콘택패드를 형성하는 공정과,Forming a contact pad connected to the impurity junction region of the semiconductor substrate;
전체표면상부에 하부절연층을 형성하는 공정과,Forming a lower insulating layer over the entire surface;
상기 하부절연층을 통하여 상기 콘택패드에 접속되는 비트라인용 도전체를 형성하는 공정과,Forming a bit line conductor connected to the contact pad through the lower insulating layer;
비트라인 마스크와 저장전극 마스크를 이용하여 상기 비트라인용 도전체를 패터닝함으로써 비트라인과 저장전극 콘택플러그를 형성하는 공정과,Forming a bit line and a storage electrode contact plug by patterning the bit line conductor using a bit line mask and a storage electrode mask;
전체표면상부에 층간절연막을 형성하고 이를 통하여 상기 저장전극 콘택플러그를 노출시키는 저장전극 콘택홀을 형성하는 공정을 포함하는 것을 제1특징으로한다.A first feature is to form an interlayer insulating film over the entire surface and to form a storage electrode contact hole through which the storage electrode contact plug is exposed.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2d 는 본 발명의 실시예에 따른 반도체소자의 도전배선 형성방법을 도시한 단면도이다.2A to 2D are cross-sectional views illustrating a method of forming conductive wirings in a semiconductor device according to an embodiment of the present invention.
먼저, 반도체기판(11)에 활성영역을 정의하는 소자분리막(13)을 형성한다. 그리고, 상기 반도체기판(11)의 활성영역에 워드라인(도시안됨)을 형성하고 상기 반도체기판에 불순물 접합영역(도시안됨)을 형성한다. First, an isolation layer 13 defining an active region is formed on the semiconductor substrate 11. A word line (not shown) is formed in the active region of the semiconductor substrate 11 and an impurity junction region (not shown) is formed in the semiconductor substrate.
그리고, 상기 불순물 접합영역에 접속되는 콘택패드(15)를 형성한다. 이때, 상기 콘택패드(15)는 비트라인용과 저장전극용이 모두 형성된 것이다. Then, a contact pad 15 connected to the impurity junction region is formed. At this time, the contact pad 15 is formed for both the bit line and the storage electrode.
그 다음에, 전체표면상부를 평탄화시키는 하부절연층(16)을 형성하고 상기 비트라인용과 저장전극용 콘택패드(15)를 모두 노출시키는 비트라인 콘택홀(17)과 저장전극 제1콘택홀(19)을 형성한다. Next, the lower insulating layer 16 is formed to planarize the entire upper surface, and the bit line contact hole 17 and the storage electrode first contact hole exposing both the bit line and the storage electrode contact pads 15 are formed. 19).
그리고, 상기 콘택홀 측벽에 절연막 스페이서(21)를 형성한다. 그리고, 상기 콘택패드(15)에 접속되는 비트라인용 도전체(23)를 형성하고 그 상부에 반사방지막(미도시)인 산화질화막을 형성한다. 이때, 상기 비트라인용 도전체(23)은 다결정실리콘으로 형성한다. (도 2a)The insulating layer spacer 21 is formed on the sidewalls of the contact hole. A bit line conductor 23 connected to the contact pad 15 is formed, and an oxynitride film, which is an antireflection film (not shown), is formed thereon. In this case, the bit line conductor 23 is formed of polysilicon. (FIG. 2A)
그 다음, 비트라인 마스크와 저장전극 마스크를 이용하여 상기 비트라인용 도전체(23)와 반사방지막(25) 적층구조를 동시에 정의함으로써 비트라인(27)과 저장전극 콘택플러그(29)를 형성한다. Next, the bit line 27 and the storage electrode contact plug 29 are formed by simultaneously defining the stacked structure of the bit line conductor 23 and the anti-reflection film 25 using the bit line mask and the storage electrode mask. .
여기서, ⓑ 는 상기 비트라인 마스크와 저장전극 마스크를 이용하여 정의된 적층구조의 평면도를 도시한다. (도 2b)Here, ⓑ shows a plan view of the stacked structure defined using the bit line mask and the storage electrode mask. (FIG. 2B)
그 다음, 전체표면상부를 평탄화시키는 층간절연막(31)을 형성하고 그 상부에 감광막패턴(33)을 형성한다. 이때, 상기 감광막패턴(33)은 저장전극 콘택마스크(도시안됨)를 이용한 노광 및 현상공정으로 형성한다. Next, an interlayer insulating film 31 is formed to planarize the entire upper surface, and a photosensitive film pattern 33 is formed thereon. In this case, the photoresist pattern 33 is formed by an exposure and development process using a storage electrode contact mask (not shown).
그리고, 상기 감광막패턴(33) 측벽에 폴리머 스페이서(35)를 형성한다. 이때, 상기 폴리머 스페이서(35)는 상기 감광막패턴(33)의 형성공정시 폴리머를 유발시켜 형성한 것이다.A polymer spacer 35 is formed on sidewalls of the photoresist pattern 33. In this case, the polymer spacer 35 is formed by inducing a polymer during the formation process of the photoresist pattern 33.
그 다음, 상기 감광막패턴(33)을 마스크로하여 상기 저장전극 콘택플러그(29)를 노출시키는 저장전극 제2콘택홀(37)을 형성한다. (도 2c, 도 2d)Next, the storage electrode second contact hole 37 exposing the storage electrode contact plug 29 is formed using the photoresist pattern 33 as a mask. (FIG. 2C, FIG. 2D)
후속공정으로 상기 저장전극 제2콘택홀(37)을 통하여 상기 저장전극 콘택플러그(29)에 접속되는 저장전극을 형성한다. In a subsequent process, a storage electrode connected to the storage electrode contact plug 29 through the storage electrode second contact hole 37 is formed.
이상에서 설명한 바와같이 본 발명에 따른 반도체소자의 도전배선 형성방법은, 하부 도전층의 패터닝 공정시 상부 도전층 마스크를 이용하여 동시에 패터닝하고 후속공정으로 이에 콘택되는 상부 도전층을 형성함으로써 상부 도전층과 하부 도전층의 단락 문제를 해결하고 상부 도전층 콘택홀의 에스펙트비를 줄일 수 있어 반도체소자의 고집적화를 가능하게 그에 따른 반도체소자의 특성 및 신뢰성을 향상시키는 효과가 있다.As described above, in the method for forming conductive wirings of the semiconductor device according to the present invention, the upper conductive layer is formed by simultaneously patterning the upper conductive layer using the upper conductive layer mask during the patterning process of the lower conductive layer and forming the upper conductive layer contacted thereto in a subsequent process. The short-circuit problem of the lower conductive layer and the lower conductive layer can be solved, and the aspect ratio of the upper conductive layer contact hole can be reduced, thereby enabling high integration of the semiconductor device, thereby improving characteristics and reliability of the semiconductor device.
도 1 은 종래기술에 따른 반도체소자의 도전배선 형성방법 형성방법을 도시한 단면도.1 is a cross-sectional view showing a method for forming a conductive wiring of a semiconductor device according to the prior art.
도 2a 내지 도 2d 는 본 발명의 실시예에 따른 반도체소자의 도전배선 형성방법 형성방법을 도시한 단면도.2A to 2D are cross-sectional views illustrating a method of forming a conductive wiring forming method of a semiconductor device according to an embodiment of the present invention.
<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>
11,41 : 반도체기판 13,43 : 소자분리막11,41: semiconductor substrate 13,43: device isolation film
15,45 : 콘택패드 16,49 : 하부절연층15,45: contact pad 16,49: lower insulating layer
17 : 비트라인 콘택홀 19,51 : 저장전극 제1콘택홀 17: bit line contact hole 19,51: storage electrode first contact hole
21 : 절연막 스페이서 23 : 비트라인용 도전체 21 insulating film spacer 23 conductor for bit line
25 : 반사방지막 27,47 : 비트라인 25: antireflection film 27,47: bit line
29 : 저장전극 콘택플러그 31 : 층간절연막 29 storage electrode contact plug 31 interlayer insulating film
33 : 감광막패턴 35 : 저장전극 제2콘택홀33: photoresist pattern 35: storage electrode second contact hole
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| KR1019980062036A KR100546143B1 (en) | 1998-12-30 | 1998-12-30 | Method for forming conductive wiring in semiconductor device |
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| KR1019980062036A KR100546143B1 (en) | 1998-12-30 | 1998-12-30 | Method for forming conductive wiring in semiconductor device |
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| KR100546143B1 true KR100546143B1 (en) | 2006-03-31 |
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