KR20010059980A - Method for manufacturing dram cell capacitor - Google Patents

Abstract

PURPOSE: A method for manufacturing a DRAM cell capacitor is provided to prevent a crack from creating in a periphery area by forming a lower electrode by using a nitride layer formed only at both sides of a plug layer. CONSTITUTION: A plurality of word lines(12) and bit lines(16) are formed on a semiconductor substrate(11). An interlayer dielectric having a plurality of capacitor contact holes are formed on the bit lines. A plug layer(15) is formed on the capacitor contact holes. Then, the plug layer(15) is etched such that the plug layers are insulated from each other. The interlayer dielectric is etched such that the insulated plug layer is protruded. Then, the first insulating layer is formed on the entire surface of the structure. After etching the first insulating layer, the second insulating layer having an etching selectivity with respect to the first insulating layer is formed on the entire surface of the structure. Then, the second insulating layer is etched. After forming a lower electrode, the second insulating layer is removed. A dielectric layer is formed on the surface of the lower electrode.

Description

Method for manufacturing DRAM cell capacitors

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a DRAM cell capacitor, and more particularly, to a method for manufacturing a DRAM cell capacitor, which prevents cracking in a peripheral region and improves yield and integration of devices.

In general, DRAM (Dynamic Random Access Memory) is composed of a unit cell (Cell) consisting of a transistor that performs a number of switching operations and a capacitor that stores information in the form of charge, and stores information as a state of charge stored in the capacitor It is characterized by.

1A to 1C are cross-sectional views illustrating a method of manufacturing a DRAM cell capacitor according to the prior art, and FIG. 2 is a photograph illustrating a crack occurrence in a conventional peripheral region.

In the conventional method of manufacturing a DRAM cell capacitor, as shown in FIG. 1A, a plurality of word lines 12 having an insulating film are formed on a semiconductor substrate 11.

After the first nitride film 13 is formed on the entire surface including the word lines 12, the first oxide film 14 is formed on the first nitride film 13 as an interlayer insulating film.

After the first photoresist film is coated on the first oxide film 14, the first photoresist film is selectively exposed and developed to be removed only at a portion where a bit line contact hole is to be formed by a photolithography process.

Thereafter, the first oxide film 14 and the first nitride film 13 are selectively etched using the selectively exposed and developed first photosensitive film as a mask to form a first contact hole, and then the first photosensitive film is removed. do.

Subsequently, a first polycrystalline silicon layer is formed on the first oxide layer 14 including the first contact hole, and then etched back to form a first plug layer in the first contact hole. 15) and a second polycrystalline silicon layer, a tungsten (W) silicide layer, a second nitride film, and a second photosensitive film are formed on the first oxide film 14 including the first plug layer 15. Thereafter, a photolithography process is performed such that the second photoresist layer remains only at a portion where a bit line is to be formed around the first contact hole.

Next, the second nitride film, the tungsten silicide layer, and the second polycrystalline silicon layer are selectively etched using the photo-etched second photosensitive film as a mask to form a plurality of bit lines 16, and then the second photosensitive film is removed. .

A third nitride film 17 is formed on the entire surface including the bit lines 16 and a second oxide film 18 is formed on the entire surface including the third nitride film 17 as an interlayer insulating film.

Subsequently, after the third photoresist film is coated on the second oxide film 18, a photolithography process is performed such that the third photoresist film is removed only at the portion where the capacitor contact hole is to be formed.

Thereafter, the first and second oxide layers 14 and 18 and the first nitride layer 13 are selectively etched using the photo-etched third photosensitive layer as a mask to form a second contact hole, and then the third photosensitive layer Remove it.

Next, after forming the third polycrystalline silicon layer on the second oxide layer 18 including the second contact hole, the second plug layer 19 is formed in the second contact hole by etching back.

As shown in FIG. 1B, a third oxide film 20 and a fourth nitride film 21 and a fourth oxide film 22 for forming a lower electrode are formed on the second oxide film 18 including the second plug layer 19 as a barrier layer. ) Are formed sequentially.

As shown in FIG. 1C, a fourth photoresist layer 23 is coated on the fourth oxide layer 22, and the fourth photoresist layer 23 is subjected to a photolithography process so as to remove only the portion where the lower electrode of the capacitor is to be formed.

The fourth oxide film 22 is etched using the photo-etched fourth photoresist film 23 as a mask, and the fourth nitride film 21 and the third oxide film are etched after the fourth nitride film 21 is used as an etch end point. Selectively etch (20).

Here, since the fourth nitride film 21 remains in the peripheral region even after performing the etching process of the third oxide film 20, the fourth nitride film 21 and the fourth oxide film 22, as shown in FIG. By the process, a crack (A) is generated by receiving a thermal stress in the peripheral region.

After the fourth photoresist layer 23 is removed in a later step, a lower electrode is formed on the etched portion of the fourth oxide layer 22, and then the fourth oxide layer 22 is removed.

A dielectric film is formed on the exposed lower electrode surface, and an upper electrode is formed on the entire surface including the dielectric film.

However, the conventional method of manufacturing a DRAM cell capacitor is formed on the front surface including the peripheral area during the oxide film etching process of the portion where the lower electrode of the capacitor is formed, so that the nitride film used as the etching end point remains as a flat plate in the peripheral area even after the etching process. The crack phenomenon occurs due to the thermal stress caused by the post-process, and the crack phenomenon occurs in the oxide films formed on the upper and lower layers of the nitride film. Thus, bridges between wires such as word lines and bit lines or between bit lines and capacitors are generated. There was a problem that the yield and density of the deterioration.

The present invention has been made in order to solve the above problems, and the lower electrode is formed by using a nitride film formed only on both sides of the plug layer after protruding the plug layer, thereby preventing the occurrence of cracks in the peripheral region. It is an object to provide a manufacturing method.

1A to 1C are cross-sectional views illustrating a method of manufacturing a DRAM cell capacitor according to the prior art.

2 is a photograph showing a crack occurrence of a conventional peripheral region

3A to 3D are cross-sectional views illustrating a method of manufacturing a DRAM cell capacitor according to an embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

11: semiconductor substrate 12: word line

13: first nitride film 14: first oxide film

15: first plug layer 16: bit line

17: third nitride film 18: second oxide film

19: second plug layer 20: third oxide film

21: fourth nitride film 22: fourth oxide film

23: fourth photosensitive film

A method of manufacturing a DRAM cell capacitor of the present invention includes the steps of providing a substrate having a plurality of word lines and a plurality of bit lines, forming an interlayer insulating film having a plurality of capacitor contact holes on the bit lines, the capacitor Forming a plug layer in a contact hole, etching the plug layers to be insulated from each other, etching the interlayer insulating film to protrude the insulated plug layer, and forming a first insulating film having an etch selectivity with the interlayer insulating film. Forming a first insulating film on the entire surface of the interlayer insulating film on both sides of the protruding plug layer; forming a second insulating film on the front surface of the second insulating film having an etching selectivity with the first insulating film; Etching the second insulating film at a portion where the lower electrode of the capacitor is to be formed using the insulating film as an etching end point; Forming a lower electrode by forming a conductive layer on a portion where the insulating film is etched, forming an lower electrode, and performing an etching process to insulate the lower electrode from each other, removing the second insulating film, forming a dielectric film on the exposed lower electrodes; And forming an upper electrode on the dielectric layer.

A preferred embodiment of the method for manufacturing a DRAM cell capacitor according to the present invention as described above will be described in detail with reference to the accompanying drawings.

3A to 3D are cross-sectional views illustrating a method of manufacturing a DRAM cell capacitor according to an exemplary embodiment of the present invention.

In the method of manufacturing the DRAM cell capacitor according to the embodiment of the present invention, as shown in FIG. 3A, a plurality of word lines 12 having an insulating film are formed on the semiconductor substrate 11.

After the first nitride film 13 is formed on the entire surface including the word lines 12, the first oxide film 14 is formed on the first nitride film 13 as an interlayer insulating film.

After applying a first photoresist film on the first oxide film 14, the first photoresist film is selectively exposed and developed to be removed only at the portion where the bit line contact hole is to be formed by a photolithography process.

Thereafter, the first oxide film 14 and the first nitride film 13 are selectively etched using the selectively exposed and developed first photosensitive film as a mask to form a first contact hole, and then the first photosensitive film is removed. do.

Subsequently, after the first polycrystalline silicon layer is formed on the first oxide layer 14 including the first contact hole, the first plug layer 15 is formed in the first contact hole by etching back. After forming the second polycrystalline silicon layer, the tungsten silicide layer, the second nitride film and the second photosensitive film on the first oxide film 14 including the first plug layer 15, the second photosensitive film is formed into the first contact hole. The photolithography process is performed so that only the bit line is formed at the center.

Next, the second nitride film, the tungsten silicide layer, and the second polycrystalline silicon layer are selectively etched using the photo-etched second photosensitive film as a mask to form a plurality of bit lines 16, and then the second photosensitive film is removed. .

A third nitride film 17 is formed on the entire surface including the bit lines 16 and a second oxide film 18 is formed on the entire surface including the third nitride film 17 as an interlayer insulating film.

Subsequently, after the third photoresist film is coated on the second oxide film 18, a photolithography process is performed such that the third photoresist film is removed only at the portion where the capacitor contact hole is to be formed.

Thereafter, the second oxide layer 18, the first oxide layer 14, and the first nitride layer 13 are selectively etched using the photo-etched third photosensitive layer as a mask to form a second contact hole, and then 3 Remove the photoresist film.

Next, after forming the third polycrystalline silicon layer on the second oxide layer 18 including the second contact hole, the second plug layer 19 is formed in the second contact hole by etching back.

Here, the second plug layer 19 may be formed in the second contact hole by using a mechanical polishing process instead of the etch back process.

As shown in FIG. 3B, the second oxide layer 18 is etched back such that the second plug layer 19 protrudes.

Here, during the etch back process of the third polycrystalline silicon layer, the etching rate of the second oxide layer may be increased to protrude the second plug layer 19 without the etch back process of the second oxide layer.

In addition, during the mechanical pulsing process of the third polycrystalline silicon layer, the etching rate of the second oxide layer may be increased to protrude the second plug layer 19 without an etch back process of the second oxide layer.

As shown in FIG. 3C, a fourth nitride film 21 is formed and etched back on the entire surface of the second plug layer 19 protruding.

Here, the fourth nitride film is removed on the second oxide film 18 on both sides of the protruding second plug layer 19 by removing the fourth nitride film 21 in the peripheral region by an etch back process of the fourth nitride film 21. (21) is left.

Meanwhile, the fourth nitride layer 21 may be buried between the second plug layer 19 by adjusting the height of the protruding second plug layer 19 and the gap between the second plug layer 19 to enhance the etching end function. Can be.

That is, the fourth nitride film 21 is the second plug layer 19 with the height at which the second plug layer 19 protrudes from 1000 to 2000 kPa and the distance between the second plug layer 19 from 2000 to 4000 kPa. Buried in between.

Instead of the fourth nitride film 21, it may be formed of Low Press-TetraEthyl Ortho Silicate (LP-TEOS).

As shown in FIG. 3D, the fourth oxide film 22 for forming the lower electrode is formed on the entire surface including the fourth nitride film 21 remaining on the second oxide film 18 on both sides of the protruding second plug layer 19. Form.

The fourth photoresist layer 23 is coated on the fourth oxide layer 22, and the fourth photoresist layer 23 is subjected to a photolithography process so as to remove only the portion where the lower electrode of the capacitor is to be formed.

The fourth oxide film 22 and the third oxide film 20 are etched using the photo-etched fourth photosensitive film 23 as a mask, and the fourth nitride film 21 is etched as an end point.

After the fourth photoresist layer 23 is removed in a later step, a lower electrode is formed on the etched portion of the fourth oxide layer 22, and then the fourth oxide layer 22 is removed.

A dielectric film is formed on the exposed lower electrode surface, and an upper electrode is formed on the entire surface including the dielectric film.

In the method of manufacturing the DRAM cell capacitor of the present invention, since the lower electrode is formed using the nitride film formed only on both sides of the plug layer after protruding the plug layer, the nitride film of the peripheral region is removed, so that the crack phenomenon occurring in the peripheral region is eliminated. Since it is suppressed, the bridge between wirings is prevented and the yield and integration degree of an element are improved.

Claims (4)

Providing a substrate on which a plurality of word lines and a plurality of bit lines are formed; Forming an interlayer insulating film having a plurality of capacitor contact holes on the bit lines; Forming a plug layer in the capacitor contact hole; Etching the plug layers to be insulated from each other; Etching the interlayer insulating film to protrude the insulated plug layer; Forming a first insulating film having an etch selectivity with respect to the interlayer insulating film; Etching the first insulating film so as to remain only on the interlayer insulating film on both sides of the protruding plug layer; Forming a second insulating film on an entire surface having an etch selectivity with the first insulating film; Etching the second insulating film at a portion where the lower electrode of the capacitor is to be formed using the first insulating film as an etching end point; Forming a lower electrode by forming a conductive layer on a portion where the second insulating film is etched, performing an etching process of mutually insulating the lower electrode, and removing the second insulating film; Forming a dielectric film on the exposed lower electrodes; And forming an upper electrode on the dielectric layer. The method of claim 1, A method of manufacturing a DRAM cell capacitor, wherein the interlayer insulating film is planarized to a thickness of 500 to 1500 kPa and the first insulating film is formed to a thickness of 500 to 1500 kPa. The method of claim 1, The first insulating film is formed of a nitride film or LP-TEOS, characterized in that the manufacturing method of the DRAM cell capacitor. The method of claim 1, A method of manufacturing a DRAM cell capacitor, wherein the first insulating film is interposed between the plugs at a height at which the plug layer protrudes from 1000 to 2000 kPa and a plug layer mutual spacing of 2000 to 4000 kPa.