JPS58176974A - Preparation of semiconductor device - Google Patents
Preparation of semiconductor deviceInfo
- Publication number
- JPS58176974A JPS58176974A JP5989682A JP5989682A JPS58176974A JP S58176974 A JPS58176974 A JP S58176974A JP 5989682 A JP5989682 A JP 5989682A JP 5989682 A JP5989682 A JP 5989682A JP S58176974 A JPS58176974 A JP S58176974A
- Authority
- JP
- Japan
- Prior art keywords
- film
- polycrystalline silicon
- deposited
- gate
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 238000000034 method Methods 0.000 claims abstract description 23
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 21
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 11
- 238000007740 vapor deposition Methods 0.000 claims description 11
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 238000004544 sputter deposition Methods 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 8
- 229910052710 silicon Inorganic materials 0.000 abstract description 8
- 239000010703 silicon Substances 0.000 abstract description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 4
- 239000000758 substrate Substances 0.000 abstract description 4
- 238000000151 deposition Methods 0.000 abstract description 3
- 239000000126 substance Substances 0.000 abstract description 3
- 238000001312 dry etching Methods 0.000 abstract description 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 2
- 239000000377 silicon dioxide Substances 0.000 abstract description 2
- 238000001771 vacuum deposition Methods 0.000 abstract description 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 230000009545 invasion Effects 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 230000015556 catabolic process Effects 0.000 description 8
- 238000010586 diagram Methods 0.000 description 4
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 239000003921 oil Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 229910000073 phosphorus hydride Inorganic materials 0.000 description 1
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
■ 発明の技術分身
本発明は半導体装置の製造方法に関し、特にＭＩＳ形半
導体素子のシリコンゲート電極の形成方法の改普に関す
る。DETAILED DESCRIPTION OF THE INVENTION (1) Technique of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a modification of a method for forming a silicon gate electrode of an MIS type semiconductor element.
（至）従来技術と問題点
ＩＣ，ＬＳＩ、ＴｏるいはＶＬＳＩなどの記憶囲路、論
理回路はその大半がＭＩＳ形（昔通はＭＯ８ＪＩでＴｏ
ｌｌ、以下ではＭＯＳ形で代表して説明する）半導体素
子から構成されておシ、第１図はこのよう１上ＭＯ８形
素子の基本構造を示す 公知のように、半導体基板１上
にゲート絶縁膜２を介してゲート電極８が設けられるが
、素子自身は高密度化されて小型化し、ゲート絶縁膜も
数ｌＯＯλ程度とうすく形成され、またゲート電極も同
様に薄く形成されるよう罠なってきてお夛、品質面でそ
れに起因する種々の問題がある。(To) Conventional technology and problems Most of the memory circuits and logic circuits of IC, LSI, TO or VLSI are MIS type (old-time experts call it MO8JI)
Figure 1 shows the basic structure of such a MO8 type element.As is known, a gate insulator is provided on a semiconductor substrate 1. A gate electrode 8 is provided through the film 2, but as the device itself has become more dense and smaller, the gate insulating film has become thinner, on the order of several 100λ, and the gate electrode has become similarly thin. However, there are various problems caused by this in terms of quality.
そのうち、ゲート絶縁耐圧劣化の問題は初期から良く検
討されており、例えば１μミニウムゲート電極はシリコ
ンゲート電極よプゲート耐圧の良い素子であることも知
られている。しかしながら、ＬＳＩのように高集積化す
るためには、ゲートセルファフィン工程を採用しようと
するとゲート電極に耐熱性が要求され、ま九多層配線構
造にする必要があるから、軟かいアルミニウムを用いる
ことは囃しく、’リコンゲー）ｔｌｌが用いられること
が多い。Among these, the problem of gate dielectric breakdown voltage deterioration has been well studied from the beginning, and it is also known that, for example, a 1 μm gate electrode has a higher gate breakdown voltage than a silicon gate electrode. However, in order to achieve high integration such as LSI, if a gate cell fin process is used, the gate electrode must have heat resistance, and a multilayer wiring structure is required, so soft aluminum is used. It is a noisy sound, and 'recon game) tll is often used.
本発明はそのｙリコンゲート電Ｉｉの被着方法に係り、
多結晶シリコン形成には通常蒸着法、スパッタ法、ある
いは化学気相成長（ＣＶＤ）法があるが、これら何れの
形成法も利点と欠点とを併せもっている。即ち、ＣＶＤ
法で被着したシリコンゲート電極を有する半導体素子Ｆ
ｉ耐圧劣化が激しくて、その他の蒸着又はスパッタで被
膚形成したゲート電極より劣る。一方、蒸着法で被着し
た多結晶シリコンからなるゲー）ｔ−は無定形でアモル
ファス状態に近く、且つポーラスな膜である。そのため
、製造工程中に、弗酸浴数などがゲート電極に浸み込ん
で、直下の二酸化シリコン（Ｓｊ−０，）膜からなるゲ
ート絶縁膜をＧ４蝕し、同様に耐圧劣化させたり、また
スレーＶＨＩＷド電圧ｖｔｈを変動させる。また、スパ
ッタ法は蒸着法と類似の膜質が形成される。The present invention relates to a method for depositing the y recongate electrode Ii,
Polycrystalline silicon is usually formed by vapor deposition, sputtering, or chemical vapor deposition (CVD), but each of these methods has both advantages and disadvantages. That is, CVD
Semiconductor device F with a silicon gate electrode deposited by a method
The breakdown voltage deteriorates significantly and is inferior to other gate electrodes formed by vapor deposition or sputtering. On the other hand, a film made of polycrystalline silicon deposited by vapor deposition is amorphous, close to an amorphous state, and porous. Therefore, during the manufacturing process, the hydrofluoric acid bath and other substances seep into the gate electrode, corrode the gate insulating film made of silicon dioxide (Sj-0,) directly below, and cause breakdown voltage degradation as well. The slave VHIW voltage vth is varied. Further, the sputtering method forms a film quality similar to that of the vapor deposition method.
（Ｃ） 発明の目的
本発明はこのような問題点を解消し、安定したゲート絶
縁耐圧かえられるＭＯＳ形半導体素子の製造方法を提案
するものである。(C) Object of the Invention The present invention solves these problems and proposes a method of manufacturing a MOS type semiconductor device that can stabilize the gate dielectric breakdown voltage.
（１）発明の構成
このような目的は、ゲート絶縁膜上に蒸着法わるいはス
パッタ法によ）多結晶シリコン膜を形成し、更にその上
にＣＶＤ法により多結晶シリコン膜を被着して、併せて
ゲート電極にする製造方法によって達成することができ
る。(1) Structure of the Invention The object is to form a polycrystalline silicon film on a gate insulating film by vapor deposition or sputtering, and then deposit a polycrystalline silicon film thereon by CVD. This can be achieved by a method of manufacturing a gate electrode as well.
（ｆ１３） 発明の実施例
第２図ないし第４図は本元明にか＼る一央厖例の工程順
断面図をボしている。先づ第２図に示すように半導体基
板ｔ２ｉｉ−ｍ択賑化１７てフィールド絶縁膜４を形成
した後、膜厚７００ＡのＳ） （Ｊ ｇ膜からなるゲー
ト絶縁膜２を形成する。(f13) Embodiments of the Invention Figures 2 through 4 are cross-sectional views of the process steps of an example by Akira Honmoto. First, as shown in FIG. 2, after a field insulating film 4 is formed on a semiconductor substrate t2ii-m selection layer 17, a gate insulating film 2 made of a 700 Å thick film is formed.
次いで、第３図に示すようにその上面に蒸着法によって
膜厚２０００Ａの多結晶シリコン膜５を被着し、更にそ
の上にＣＶＤ法によって同じく膜厚２０００Ａの多結晶
シリコン膜６を被着する。これらの多結晶シリコン膜は
例えば燐などをドープした導電膜であり、最初に真空蒸
着装置内で燐を含む多結晶シリコンを蒸着させる。続い
てＣＶＤ装置に入れて初めにその表面を僅かにエツチン
グして清浄化し、次いでフォスフインを含むモノシフン
（ＳｉＨ４）を導入し分解して被着させる。Next, as shown in FIG. 3, a polycrystalline silicon film 5 with a thickness of 2000 Å is deposited on the upper surface by a vapor deposition method, and a polycrystalline silicon film 6 with a thickness of 2000 Å is further deposited on top of this by a CVD method. . These polycrystalline silicon films are, for example, conductive films doped with phosphorus or the like, and polycrystalline silicon containing phosphorus is first deposited in a vacuum deposition apparatus. Subsequently, it is placed in a CVD apparatus, and its surface is first slightly etched and cleaned, and then monosiphne (SiH4) containing phosphine is introduced, decomposed, and deposited.
次いで、第４図に示すようにフォトプロセスを用いてパ
ターンユングし、二層の多結晶Ｖリコン１１１５．６か
らなるゲート電極およびゲート絶縁膜２を形成する。そ
れＫは、レジスト膜マスク（図示せず）を被数し、四弗
化炭素（フレオン）と酸素との混合ガスによってドライ
エツチングを行なう方法を用いる。Next, as shown in FIG. 4, a pattern is formed using a photo process to form a gate electrode and gate insulating film 2 made of two layers of polycrystalline V silicon 1115.6. This method uses a resist film mask (not shown) and performs dry etching using a mixed gas of carbon tetrafluoride (Freon) and oxygen.
以下、公知の製法によってソース、ドレインを形成し、
ＭＯＳ形半導体素子に仕上げるが、このような二層の多
結晶Ｖリコン膜にすると、下層の多結晶シリコン膜５は
蒸着して被着している丸めゲート耐圧の劣化がなくなり
、また上層の多結晶シリコン膜６はＣＶＤ法で被着し九
膜であるからち密な膜で薬品＊＊の浸入を阻止し、製造
中にゲート絶縁膜を安定に保つ。且つ、気相成長し九ド
ープド多結晶Ｖリコン膜・は同じくドープした蒸着膜よ
）電子やホールの易動度が大きい丸め、電気伝導度が改
善される効果ももっている。Thereafter, the source and drain are formed by a known manufacturing method,
A MOS type semiconductor device is finished, but if such a two-layer polycrystalline silicon film is used, the lower layer polycrystalline silicon film 5 will be vapor-deposited and the rounded gate breakdown voltage will not deteriorate, and the upper layer polycrystalline silicon film 5 will not deteriorate. Since the crystalline silicon film 6 is deposited by the CVD method and is a dense film, it prevents penetration of chemicals** and keeps the gate insulating film stable during manufacturing. In addition, the vapor-phase grown nine-doped polycrystalline V silicon film (similarly to a doped vapor deposited film) has the effect of rounding, which has a high mobility of electrons and holes, and improves electrical conductivity.
また、第６図は他の実施例の工程途中図で、上記実施例
の第８図に対応する工程図を示しているが、上記例のよ
うに蒸着法で多結晶Ｖリコン膜ｉを形成し、次いで（４
Ｄ法で多結晶シリコン膜６を形成した後、更にその上に
蒸着法で多結晶Ｖリコン膜７を形成する。このように三
層に積層したダート電極も同じく上記の利点がえられる
。In addition, FIG. 6 is a process diagram of another example, and shows a process diagram corresponding to FIG. 8 of the above example. and then (4
After forming the polycrystalline silicon film 6 by the D method, a polycrystalline V silicon film 7 is further formed thereon by the vapor deposition method. The dirt electrodes laminated in three layers in this manner also provide the above advantages.
尚、上記例において蒸着法の代りにスパッタ法で多結晶
シリコン膜を被着しても蒸着法と変わりなく、同様の効
果かえられる。Incidentally, in the above example, even if the polycrystalline silicon film is deposited by sputtering instead of the vapor deposition method, the same effect as the vapor deposition method can be obtained.
（イ）発明の効果
上記実施例から明らかなように１本発明はシリコンゲー
ト電極を二層あるいは三層と被着法を変えて積層する形
成方法で、ゲート絶縁耐圧を改善し、安定したｖｔｈを
えることができて、半導体装置の品質向上に著しく・貢
献する龜のである。(B) Effects of the Invention As is clear from the above embodiments, the present invention improves gate dielectric breakdown voltage and achieves stable vth by using a method of laminating silicon gate electrodes in two or three layers using different deposition methods. It is a tool that significantly contributes to improving the quality of semiconductor devices.
第１図はＭＯＳ形半導体素子の基本構造図、第２図ない
し第４図は本発明Ｋか覧る一実施例ＯＩｌ造工程順断面
図、第５図は他の実施例の一工程途中図である。図中、
１は半導体基板、２はゲート絶縁膜、Ｓはゲート電極、
４はフィールド絶縁膜。
５．１は蒸着法による多結晶ｙリコン膜、６はＣＶＤ沫
による多結晶Ｖ９コン膜を示す。
第１図
第２図Fig. 1 is a basic structural diagram of a MOS type semiconductor device, Figs. 2 to 4 are sequential cross-sectional views of an oil manufacturing process according to an embodiment of the present invention, and Fig. 5 is an intermediate step diagram of another embodiment. It is. In the figure,
1 is a semiconductor substrate, 2 is a gate insulating film, S is a gate electrode,
4 is a field insulating film. 5.1 shows a polycrystalline Y-recon film made by vapor deposition, and 6 shows a polycrystalline V9-recon film made by CVD. Figure 1 Figure 2
Claims (1)
表面に蒸着法あるいはスパッタ法により多結晶ｙリコン
膜を形成し、更にその上に化学気相成長法により多結晶
シリコン膜を被着して、併せてゲート電極にする工程が
含まれてなることを特徴とする半導体装置の製造方法。After forming the gate insulating film of the MIS type semiconductor device, a polycrystalline silicon film is formed on its surface by vapor deposition or sputtering, and then a polycrystalline silicon film is deposited on top of it by chemical vapor deposition. A method for manufacturing a semiconductor device, comprising the steps of forming a gate electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5989682A JPS58176974A (en) | 1982-04-09 | 1982-04-09 | Preparation of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5989682A JPS58176974A (en) | 1982-04-09 | 1982-04-09 | Preparation of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58176974A true JPS58176974A (en) | 1983-10-17 |
Family
ID=13126332
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5989682A Pending JPS58176974A (en) | 1982-04-09 | 1982-04-09 | Preparation of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58176974A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0452720A2 (en) * | 1990-04-02 | 1991-10-23 | National Semiconductor Corporation | A semiconductor structure and method of its manufacture |
| JPH07200089A (en) * | 1993-12-28 | 1995-08-04 | Konami Kk | Joy stick |
| WO2001020684A1 (en) * | 1999-09-14 | 2001-03-22 | General Semiconductor, Inc. | Trench dmos transistor having improved trench structure |
| US6781196B2 (en) | 2002-03-11 | 2004-08-24 | General Semiconductor, Inc. | Trench DMOS transistor having improved trench structure |
-
1982
- 1982-04-09 JP JP5989682A patent/JPS58176974A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0452720A2 (en) * | 1990-04-02 | 1991-10-23 | National Semiconductor Corporation | A semiconductor structure and method of its manufacture |
| EP0452720A3 (en) * | 1990-04-02 | 1994-10-26 | Nat Semiconductor Corp | A semiconductor structure and method of its manufacture |
| JPH07200089A (en) * | 1993-12-28 | 1995-08-04 | Konami Kk | Joy stick |
| WO2001020684A1 (en) * | 1999-09-14 | 2001-03-22 | General Semiconductor, Inc. | Trench dmos transistor having improved trench structure |
| US6781196B2 (en) | 2002-03-11 | 2004-08-24 | General Semiconductor, Inc. | Trench DMOS transistor having improved trench structure |
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