JPS6425481A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6425481A
JPS6425481A JP18151387A JP18151387A JPS6425481A JP S6425481 A JPS6425481 A JP S6425481A JP 18151387 A JP18151387 A JP 18151387A JP 18151387 A JP18151387 A JP 18151387A JP S6425481 A JPS6425481 A JP S6425481A
Authority
JP
Japan
Prior art keywords
pattern
film
substrate
sidewall
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP18151387A
Other languages
Japanese (ja)
Other versions
JPH07105492B2 (en
Inventor
Kazuhiko Tsuji
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP18151387A priority Critical patent/JPH07105492B2/en
Publication of JPS6425481A publication Critical patent/JPS6425481A/en
Publication of JPH07105492B2 publication Critical patent/JPH07105492B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

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  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To reduce an occupying area on the surface of a semiconductor substrate and to enhance the density by forming source, drain on the sidewall of the substrate, and simultaneously forming the connecting region of the source, drain to connecting wirings of the same silicide layer. CONSTITUTION:A gate insulating film 2, a polycrystalline silicon film 3 and a silicon nitride film 4 are formed on one conductivity type silicon semiconductor substrate 1 (A), and a predetermined first pattern is formed (B). Then, an insulating film 5 is formed on a whole surface, and an insulating film 5 remains on the sidewall of first pattern by an anisotropic dry etching method (C). Thereafter, with the first pattern and the film 5 as masks an opening is formed at the substrate to form a second pattern (D). A silicon nitride film 6 is formed on the sidewall of the second pattern (E), with the films 4, 6 as masks an insulating film 7 is formed on the substrate (F), the films 4, 6 are removed, and a high melting point metal 8 is formed on the whole surface (G). Then, the surface of the film 3 is reacted with the substrate of the sidewall of the opening to form silicide layers 9, 10 as a gate electrode 9 and source, drain electrode regions 10.
JP18151387A 1987-07-21 1987-07-21 Method for manufacturing semiconductor device Expired - Lifetime JPH07105492B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18151387A JPH07105492B2 (en) 1987-07-21 1987-07-21 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18151387A JPH07105492B2 (en) 1987-07-21 1987-07-21 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPS6425481A true JPS6425481A (en) 1989-01-27
JPH07105492B2 JPH07105492B2 (en) 1995-11-13

Family

ID=16102073

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18151387A Expired - Lifetime JPH07105492B2 (en) 1987-07-21 1987-07-21 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JPH07105492B2 (en)

Also Published As

Publication number Publication date
JPH07105492B2 (en) 1995-11-13

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