WO2013132783A1 - Nitride semiconductor laminate structure, nitride semiconductor light emitting element provided with nitride semiconductor laminate structure, and method for producing nitride semiconductor laminate structure - Google Patents

Nitride semiconductor laminate structure, nitride semiconductor light emitting element provided with nitride semiconductor laminate structure, and method for producing nitride semiconductor laminate structure Download PDF

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WO2013132783A1
WO2013132783A1 PCT/JP2013/001120 JP2013001120W WO2013132783A1 WO 2013132783 A1 WO2013132783 A1 WO 2013132783A1 JP 2013001120 W JP2013001120 W JP 2013001120W WO 2013132783 A1 WO2013132783 A1 WO 2013132783A1
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nitride semiconductor
semiconductor layer
type nitride
layer
plane
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PCT/JP2013/001120
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French (fr)
Japanese (ja)
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満明 大屋
横川 俊哉
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パナソニック株式会社
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/40Materials therefor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/16Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26Materials of the light emitting region
    • H01L33/30Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen

Definitions

  • the present invention relates to a nitride semiconductor multilayer structure including an n-type nitride semiconductor layer having a nonpolar or semipolar surface, a nitride semiconductor light emitting device including the nitride semiconductor multilayer structure, and the nitride semiconductor
  • the present invention relates to a method for manufacturing a laminated structure.
  • a nitride semiconductor having nitrogen (N) as a group V element is considered promising as a material for a short-wavelength light-emitting element because of its band gap.
  • LED Blue light emitting diode
  • FIG. 1 schematically shows a unit cell of GaN.
  • a part of gallium (Ga) shown in FIG. 1 can be replaced with at least one of aluminum (Al) and indium (In).
  • FIG. 2 (a), 2 (b), and 2 (c) show the plane orientation of the wurtzite crystal structure in four-index notation (hexagonal crystal index).
  • the crystal plane and its plane orientation are represented using basic vectors represented by a 1 , a 2 , a 3 and c.
  • the basic vector c extends in the [0001] direction, and this direction is called “c-axis”.
  • a plane perpendicular to the c-axis is called a “c-plane” or “(0001) plane”.
  • FIG. 2C shows the (11-22) plane.
  • the symbol “-” attached to the left side of the number in parentheses representing the Miller index represents the inversion of the index for convenience, and corresponds to “bar” in the figure.
  • a c-plane substrate that is, a substrate having a (0001) plane as a main surface is used as a substrate on which a GaN-based semiconductor crystal is grown.
  • the c-plane since the arrangement of the atomic layer of gallium (Ga) and the atomic layer of nitrogen (N) is slightly shifted in the c-axis direction, spontaneous polarization (Electrical Polarization) is generated. For this reason, the “c plane” is also called a “polar plane”.
  • a piezo electric field is generated along the c-axis direction in the quantum well layer made of InGaN constituting the active layer of the nitride semiconductor light emitting device.
  • a piezo electric field is generated in the active layer, a position shift occurs in the distribution of electrons and holes in the active layer, and the internal quantum efficiency of the active layer is reduced due to the quantum confinement Stark effect of carriers.
  • an increase in threshold current is caused. If it is an LED element, the increase in power consumption and the fall of luminous efficiency will be caused.
  • the piezo electric field screening occurs as the injected carrier density increases, the emission wavelength also changes.
  • m-plane GaN-based substrate that has a (10-10) plane called a m-plane, which is a nonpolar plane, for example, perpendicular to the [10-10] direction.
  • the m plane is a plane parallel to the c axis (basic vector c) and is orthogonal to the c plane.
  • Ga atoms and N atoms are located on the same atomic plane, and therefore no polarization occurs in a direction perpendicular to the m plane.
  • the m-plane is a general term for the (10-10) plane, the (-1010) plane, the (1-100) plane, the (-1100) plane, the (01-10) plane, and the (0-110) plane.
  • the X plane may be referred to as a “growth plane”, and a semiconductor layer formed by the X plane growth may be referred to as an “X plane semiconductor layer”.
  • Japanese Patent No. 4605193 Japanese Patent Laid-Open No. 55-9442 Japanese Patent No. 2783349 Japanese Patent No. 2967743
  • the present invention has been made in view of this problem, and an object thereof is to reduce contact resistance.
  • the nitride semiconductor multilayer structure of one embodiment of the present invention includes an n-side electrode and an n-type nitride semiconductor layer having a nonpolar or semipolar surface.
  • the n-side electrode includes an aluminum portion, the aluminum portion is in contact with the surface of the n-type nitride semiconductor layer, and the concentration of nitrogen atoms on the surface of the n-type nitride semiconductor layer in contact with the aluminum portion is It is higher than the concentration of gallium atoms on the surface of the n-type nitride semiconductor layer that is in contact.
  • a nitride semiconductor light emitting device comprising the following: an n-side electrode, a p-side electrode, an n-type nitride semiconductor layer having a nonpolar or semipolar surface, A p-type nitride semiconductor layer electrically connected to the p-side electrode, and an active layer sandwiched between the n-type nitride semiconductor layer and the p-type nitride semiconductor layer.
  • the n-side electrode includes an aluminum portion. The aluminum portion is in contact with the surface of the n-type nitride semiconductor layer. The concentration of nitrogen atoms on the surface of the n-type nitride semiconductor layer in contact with the aluminum portion is higher than the concentration of gallium atoms on the surface of the n-type nitride semiconductor layer in contact with the aluminum portion.
  • another aspect of the present invention is a light source device including a nitride semiconductor light emitting device and a wavelength conversion unit including a fluorescent material that converts the wavelength of light emitted from the nitride semiconductor light emitting device.
  • Another aspect of the present invention is a method for manufacturing a nitride semiconductor multilayer structure, which includes the following steps: (a) an n-type nitride semiconductor layer having a nonpolar or semipolar surface. Irradiating the surface of the substrate with oxygen plasma, (b) contacting the surface irradiated with the oxygen plasma in step (a) with acid, and (c) contacting the surface with the acid in step (b) with aluminum. Forming a portion;
  • the contact resistance can be reduced.
  • FIG. 1 is a diagram showing a crystal structure of a GaN-based semiconductor in a stick ball model.
  • FIG. 2A is a perspective view showing the basic vectors a 1 , a 2 , a 3 and c of the wurtzite crystal structure and the a, c and m planes.
  • FIG. 2B is a perspective view showing the r-plane of the wurtzite crystal structure.
  • FIG. 2C is a perspective view showing the (11-22) plane of the wurtzite crystal structure.
  • FIG. 3A is a schematic cross-sectional view showing a nitride semiconductor light emitting device according to an embodiment.
  • FIG. 3A is a schematic cross-sectional view showing a nitride semiconductor light emitting device according to an embodiment.
  • FIG. 3B is a diagram showing the crystal structure of the m-plane in the nitride semiconductor by a stick ball model.
  • FIG. 3C is a diagram showing the crystal structure of the c-plane in the nitride semiconductor by a stick ball model.
  • FIG. 4 is a schematic cross-sectional view showing a light source device according to an embodiment.
  • 5 (a) and 5 (b) are reference examples showing the electrical characteristics of an n-side electrode in which aluminum (Al) is applied to m-plane GaN, and
  • FIG. 5 (a) shows the voltage between the n-side electrodes.
  • FIG. 5B is a graph showing the current-voltage characteristics between the n-side electrodes for each sinter temperature.
  • 5C is a schematic diagram showing an evaluation method for evaluating electrical characteristics.
  • 6 (a) and 6 (b) are reference examples, showing electrical characteristics of an n-side electrode in which a laminated film of titanium (Ti) / aluminum (Al) is applied to m-plane GaN, and FIG. ) Is a graph showing the relationship between the voltage between the n-side electrodes and the sintering temperature, and FIG. 6B is a graph showing the current-voltage characteristics between the n-side electrodes for each sintering temperature.
  • 7A and 7B are schematic cross-sectional views in order of steps showing the method for manufacturing a nitride semiconductor multilayer structure according to one embodiment.
  • FIG. 8A and 8B show the electrical characteristics of the n-side electrode in the nitride semiconductor multilayer structure according to one embodiment
  • FIG. 8A shows the relationship between the voltage between the n-side electrodes and the sintering temperature.
  • FIG. 8B is a graph showing the current-voltage characteristics between the n-side electrodes for each sintering temperature.
  • FIG. 9 shows a comparison between the electrical characteristics of the n-side electrode in the nitride semiconductor multilayer structure according to one embodiment and the electrical characteristics of the n-side electrode to which Al is applied and the n-side electrode to which Ti / Al is applied. It is a graph.
  • FIG. 8A shows the relationship between the voltage between the n-side electrodes and the sintering temperature.
  • FIG. 8B is a graph showing the current-voltage characteristics between the n-side electrodes for each sintering temperature.
  • FIG. 9 shows a comparison between the electrical characteristics of the n-side electrode in the nitrid
  • FIG. 10 is a graph comparing current-voltage characteristics of a nitride semiconductor light emitting device according to one embodiment with a nitride semiconductor light emitting device having an n-side electrode to which Ti / Al is applied.
  • FIGS. 11A and 11B are reference examples, and the electrical characteristics of an n-side electrode in which a Ti / Al laminated film is applied to m-plane GaN subjected to “O 2 plasma irradiation + hydrofluoric acid treatment”.
  • FIG. 11A is a graph showing the relationship between the voltage between the n-side electrodes and the sintering temperature
  • FIG. 11B is a graph showing the current-voltage characteristics between the n-side electrodes for each sintering temperature. is there.
  • FIG. 11A is a graph showing the relationship between the voltage between the n-side electrodes and the sintering temperature
  • FIG. 11B is a graph showing the current-voltage characteristics between the n-side electrodes for each s
  • FIG. 12A is a reference example, in which no sintering treatment is performed on an n-side electrode in which a Ti / Al laminated film is applied to m-plane GaN subjected to “O 2 plasma irradiation + hydrofluoric acid treatment”. Are photographs observed with an optical microscope from the back side according to the sintering temperature.
  • FIG. 12B is a schematic cross-sectional view showing an observation method.
  • FIGS. 13A and 13B are reference examples, and show the electrical characteristics of an n-side electrode in which Ti is applied to m-plane GaN subjected to “O 2 plasma irradiation + hydrofluoric acid treatment”.
  • FIG. 14 (A) is a graph showing the relationship between the voltage between the n-side electrodes and the sintering temperature
  • FIG. 13 (b) is a graph showing the current-voltage characteristics between the n-side electrodes for each sintering temperature
  • 14 (a) and 14 (b) show the electrical characteristics of an n-side electrode in which various metal materials are applied to m-plane GaN subjected to “O 2 plasma irradiation + hydrofluoric acid treatment”.
  • Is a graph showing respective voltages between the n-side electrodes
  • FIG. 14B is a graph showing current-voltage characteristics between the n-side electrodes for each metal material.
  • FIG. 15A and 15 (b) show an example of m-plane GaN subjected to “no O 2 plasma”, “O 2 plasma irradiation” and “O 2 plasma irradiation + hydrofluoric acid treatment” for m-plane GaN.
  • FIG. 15A is a graph showing each voltage between the n-side electrodes
  • FIG. 15B is a current-voltage characteristic between the n-side electrodes. It is a graph which shows. 16 (a) to 16 (c) show the depth dependence of oxygen (O) concentration and carbon (C) concentration in m-plane GaN having an n-side electrode in which Al is applied to m-plane GaN.
  • FIG. 17 (A) is a graph when not irradiating m-plane GaN with O 2 plasma
  • FIG. 16 (b) is a graph when m-plane GaN is irradiated with O 2 plasma
  • FIG. 16 (c) is m-plane. It is a graph when subjected to irradiation and hydrofluoric acid treatment of the O 2 plasma GaN.
  • FIG. 17B is a graph in which the vertical axis of FIG.
  • FIG. 17A is normalized with no O 2 plasma.
  • Figure 18 is a sample not irradiated with O 2 plasma, the sample was irradiated with O 2 plasma, and with respect to O 2 plasma irradiation and each sample subjected to hydrofluoric acid treatment, is a graph showing the evaluation results of evaluating the photoluminescence .
  • FIG. 19 is a graph showing a profile in the depth direction of Ga atoms before heat treatment.
  • FIG. 20 is a graph showing a profile of Ga atoms in the depth direction after sintering.
  • FIG. 21 is a graph showing the relationship between the voltage generated between the test patterns constituting the n-side electrode and the plasma processing conditions.
  • FIG. 22 is a graph showing the relationship between plasma input power and contact resistance value.
  • FIG. 23 is an enlarged partial cross-sectional view of region A shown in FIG.
  • FIG. 24 is a partial cross-sectional view according to a first modification of the configuration shown in FIG. 25 is a partial cross-sectional view according to a second modification of the configuration shown in FIG.
  • FIG. 26 is a partial cross-sectional view according to a third modification of the configuration shown in FIG.
  • One form of the present disclosure is a nitride semiconductor multilayer structure including the following: an n-side electrode, and an n-type nitride semiconductor layer having a nonpolar or semipolar surface, where the n-side electrode Comprises an aluminum portion, the aluminum portion is in contact with the surface of the n-type nitride semiconductor layer, and the concentration of nitrogen atoms on the surface of the n-type nitride semiconductor layer in contact with the aluminum portion is in contact with the aluminum portion. It is higher than the concentration of gallium atoms on the surface of the n-type nitride semiconductor layer.
  • the aluminum portion may be made of only aluminum.
  • the aluminum portion may have a layer shape parallel to the n-type nitride semiconductor layer.
  • a plurality of aluminum portions may be provided in the nitride semiconductor multilayer structure according to one embodiment.
  • the surface of the n-type nitride semiconductor layer in contact with the aluminum portion may have gallium vacancies.
  • the surface region of the n-type nitride semiconductor layer in contact with the aluminum portion may have a thickness of 10 nm or more and 150 nm or less.
  • the n-type nitride semiconductor layer may have an m-plane surface.
  • the surface of the n-type nitride semiconductor layer in contact with the aluminum portion has a lower carrier density than the portion of the n-type nitride semiconductor layer not in contact with the aluminum portion. You may do it.
  • a nitride semiconductor light emitting device including the following: an n-type electrode, a p-side electrode, an n-type nitride semiconductor layer having a nonpolar surface or a semipolar surface, a p-type nitride semiconductor layer electrically connected to the p-side electrode, and an active layer sandwiched between the n-type nitride semiconductor layer and the p-type nitride semiconductor layer, wherein the n-side electrode is an aluminum portion And the aluminum portion is in contact with the surface of the n-type nitride semiconductor layer, and the concentration of nitrogen atoms in the surface of the n-type nitride semiconductor layer in contact with the aluminum portion is n-type in contact with the aluminum portion. It is higher than the concentration of gallium atoms on the surface of the nitride semiconductor layer.
  • the aluminum portion may be made of only aluminum.
  • the aluminum portion may have a layer shape parallel to the n-type nitride semiconductor layer.
  • the nitride semiconductor light emitting device may be provided with a plurality of aluminum portions.
  • the surface of the n-type nitride semiconductor layer in contact with the aluminum portion may have gallium vacancies.
  • the surface region of the n-type nitride semiconductor layer in contact with the aluminum portion may have a thickness of 10 nm or more and 150 nm or less.
  • the n-type nitride semiconductor layer may have an m-plane surface.
  • the surface of the n-type nitride semiconductor layer in contact with the aluminum portion has a lower carrier density than the portion of the n-type nitride semiconductor layer not in contact with the aluminum portion. You may have.
  • Another embodiment of the present disclosure is a method for manufacturing a nitride semiconductor multilayer structure, which includes the following steps: (a) an n-type nitride semiconductor layer having a nonpolar or semipolar surface. Irradiating the surface of the substrate with oxygen plasma, (b) contacting the surface irradiated with the oxygen plasma in step (a) with acid, and (c) contacting the surface with the acid in step (b) with aluminum. Forming a portion;
  • the aluminum portion may be made of only aluminum.
  • the aluminum portion may have a layer shape parallel to the n-type nitride semiconductor layer.
  • a plurality of aluminum portions may be provided.
  • the surface of the n-type nitride semiconductor layer in contact with the aluminum portion may have gallium vacancies.
  • the surface region of the n-type nitride semiconductor layer in contact with the aluminum portion may have a thickness of 10 nm or more and 150 nm or less.
  • the n-type nitride semiconductor layer may have an m-plane surface.
  • a nitride semiconductor multilayer structure having an n-type GaN layer having an m-plane as a main surface will be described as an example. However, the same can be said for a nitride semiconductor multilayer structure having another n-type nitride semiconductor layer having an m-plane as a main surface. Also, semipolar planes such as -r plane, r plane, (20-21) plane, (20-2-1) plane, (10-1-3) plane and (11-22) plane, or a plane, etc. The same can be said for a nitride semiconductor multilayer structure having an n-type GaN layer or other n-type nitride semiconductor layer whose main surface is a non-polar surface.
  • the m-plane GaN-based semiconductor element can exhibit a remarkable effect as compared with the c-plane GaN-based semiconductor element, the technology for forming the n-side ohmic electrode for the m-plane GaN has not yet been completed.
  • Patent Document 1 describes that formation of an n-side ohmic electrode for m-plane GaN is more difficult than formation of an n-side ohmic electrode for c-plane GaN.
  • the main surface of the m-plane GaN is etched, for example, in a stripe shape to intentionally expose the c-plane GaN on the stripe-shaped sidewall, and the exposed portion is effective for the c-plane GaN.
  • a technique is described in which an electrode made of Ti / Al is formed, and thereafter, sintering is performed at a temperature of about 500 ° C.
  • the technique described in Patent Document 1 is not a direct n-side ohmic electrode formation technique for m-plane GaN.
  • the process flow at the time of manufacturing the device is limited.
  • a sintering process at a temperature of about 500 ° C. is performed in order to obtain ohmic characteristics, the manufacturing process is further restricted.
  • the present inventors have intensively studied to newly develop a technique for forming an n-side ohmic electrode for a nitride semiconductor layer having a nonpolar or semipolar surface such as m-plane GaN.
  • the present inventors have found a method capable of forming an n-side ohmic electrode with extremely low resistance.
  • FIG. 3A schematically shows a cross-sectional configuration of the nitride semiconductor light emitting device according to this embodiment.
  • a nitride semiconductor light emitting device 100 shown in FIG. 3A is a semiconductor device formed of a GaN-based semiconductor, and includes an n-type nitride semiconductor layer 22, an active layer 24 formed of a nitride semiconductor, and p-type nitride.
  • the semiconductor multilayer structure 20 includes a physical semiconductor layer 26.
  • the nitride semiconductor light emitting device 100 includes a GaN-based substrate 10 having an m-plane as a main surface 10a, and a semiconductor multilayer structure 20 formed on the main surface 10a of the GaN-based substrate 10.
  • the surface modification layer 23 may be a contact layer.
  • the GaN-based substrate 10 is, for example, a GaN substrate.
  • the n-side electrode 40 may be a metal part.
  • the n-side electrode 40 is formed on the surface modification layer 23 provided on the exposed surface of the n-type nitride semiconductor layer 22 exposed from the recess 42 obtained by etching the semiconductor multilayer structure 20.
  • the semiconductor multilayer structure 20 is an m-plane semiconductor multilayer structure formed by m-plane growth, and its main surface is an m-plane.
  • a-plane GaN grows on the r-plane sapphire substrate, and depending on the growth conditions, it is not always necessary that the main surface of the GaN-based substrate 10 is the m-plane.
  • Recess 42 of n-type nitride semiconductor layer 22 in contact with n-side electrode 40 has a surface that is an m-plane.
  • the nitride semiconductor light emitting device 100 includes the GaN-based substrate 10 that holds the semiconductor multilayer structure 20, but may include another holding substrate instead of the GaN-based substrate 10. Further, the holding substrate may be removed.
  • FIG. 3B schematically shows a crystal structure in a nitride semiconductor cross section (a cross section in a direction perpendicular to the surface of the substrate) of the nitride semiconductor whose main surface is the m-plane. Since Ga atoms and N atoms are located on the same atomic plane parallel to the m-plane, no polarization occurs in the direction perpendicular to the m-plane. That is, the m-plane is a nonpolar plane, and no piezo electric field is generated in the active layer grown in the direction perpendicular to the m-plane.
  • the added In and Al are located at the Ga site and replace Ga. Even if at least part of Ga is substituted with In or Al, no polarization occurs in the direction perpendicular to the m-plane.
  • a GaN-based substrate having an m-plane as a main surface is also referred to as an “m-plane GaN-based substrate” in this specification.
  • an m-plane GaN substrate is used, and a nitride semiconductor can be grown on the m-plane of the m-plane GaN substrate. That's fine. This is because the plane orientation of the main surface of the m-plane GaN-based substrate is reflected in the plane orientation of the semiconductor product structure.
  • the main surface of the substrate is not necessarily the m-plane, and the substrate may be removed from the final device.
  • FIG. 3C schematically shows a crystal structure of a nitride semiconductor cross section (cross section in a direction perpendicular to the surface of the substrate) of the nitride semiconductor whose principal surface is the c plane.
  • Ga atoms and N atoms do not exist on the same atomic plane parallel to the c-plane.
  • polarization occurs in a direction perpendicular to the c-plane.
  • a GaN-based substrate having a c-plane as a main surface is also referred to as a “c-plane GaN-based substrate” in this specification.
  • the c-plane GaN-based substrate is a general substrate for growing GaN-based semiconductor crystals. As described above, since the positions of the Ga atomic layer and the N atomic layer parallel to the c-plane are slightly shifted in the c-axis direction, polarization is formed along the c-axis direction.
  • the active layer 24 is an electron injection region in the nitride semiconductor light emitting device 100.
  • An undoped GaN layer may be provided between the active layer 24 and the p-type nitride semiconductor layer 26.
  • the upper portion of the p-type nitride semiconductor layer 26, that is, the upper surface portion of the semiconductor multilayer structure 20, may be composed of a GaN layer having an Al composition d of zero. Thereby, contact resistance can be reduced.
  • the Al composition d need not be uniform in the thickness direction.
  • the Al composition d may change continuously or stepwise in the thickness direction. That is, the p-type nitride semiconductor layer 26 may have a multilayer structure in which a plurality of layers having different Al compositions d are stacked, and the dopant concentration may also change in the thickness direction.
  • a p-side electrode 30 is formed on the semiconductor multilayer structure 20.
  • the p-side electrode 30 according to the present embodiment is an electrode formed from silver (Ag).
  • the p-side electrode 30 is in contact with the p-type nitride semiconductor layer 26 doped with a dopant whose conductivity type is p-type.
  • the p-type nitride semiconductor layer 26 is doped with, for example, magnesium (Mg) as a dopant.
  • Mg magnesium
  • As a p-type dopant other than Mg for example, zinc (Zn) or beryllium (Be) may be doped.
  • a recess 42 exposing a part of the n-type nitride semiconductor layer 22 formed on the GaN-based substrate 10 is formed.
  • the thickness of the n-type nitride semiconductor layer 22 is not less than 0.2 ⁇ m and not more than 2 ⁇ m, for example.
  • a surface modification layer 23 is provided on a part of the exposed surface of the n-type nitride semiconductor layer 22 exposed from the recess 42. This exposed surface is an m-plane.
  • the n-side electrode 40 is formed on the surface modified layer 23 in the exposed n-type nitride semiconductor layer 22 in contact with the surface modified layer 23.
  • the surface modification layer 23 provided on the n-type nitride semiconductor layer 22 is formed by irradiating the n-type nitride semiconductor layer 22 with oxygen (O 2 ) plasma.
  • oxygen oxygen
  • O 2 oxygen
  • the pressure of O 2 is 10 Pa and the gas flow rate is 40 ml / min (standard state).
  • an RF power of 40 W, and irradiation with O 2 plasma for 30 seconds makes it possible to form a suitable surface modified layer 23.
  • the surface modification layer 23 is formed, and then the surface of the formed surface modification layer 23 is subjected to acid treatment. Also good.
  • acid treatment for example, hydrofluoric acid or buffered hydrofluoric acid can be used.
  • the acid treatment time when hydrofluoric acid or buffered hydrofluoric acid is used can be set to 30 seconds, for example.
  • the n-side electrode 40 is made of, for example, a single layer of aluminum (Al), and the thickness thereof can be, for example, 5 nm or more and 1000 nm or less.
  • a single layer of Al can be deposited by, for example, a vacuum deposition method (such as a resistance heating method or an electron beam method).
  • sintering may be performed after the n-side electrode 40 is formed.
  • the n-side electrode 40 can be made a more suitable n-side ohmic electrode by performing a sintering process at 300 ° C. for 10 minutes in a nitrogen (N 2 ) atmosphere.
  • the sintering temperature can be arbitrarily selected within a range of 200 ° C. or more and 700 ° C. or less, for example.
  • the sintering temperature may be 300 ° C. or more and 600 ° C. or less. In this sintering temperature region, the contact resistance takes the lowest value (specific contact resistance 3 ⁇ 10 ⁇ 5 ⁇ cm 2 ).
  • the sintering temperature may be 300 ° C.
  • the manufacturing process of the light-emitting element is facilitated, and the reliability of the m-plane light-emitting element that is easily affected by heat can be improved. Further, the sintering process may not be performed.
  • the n-side electrode 40 does not necessarily need to be a single layer or a single Al, and may be a metal layer containing Al as a main component, that is, an Al alloy.
  • the concentration of Al is, for example, 50% by mass or more.
  • a metal multilayer film in which Al is in contact with the surface modification layer 23 may be used. Since Al has a higher reflectance and thermal conductivity than Ti, when an Al electrode is used, light absorption can be reduced and heat dissipation can be improved compared to the case where a Ti / Al electrode is used. Thereby, the light output can be improved.
  • the n-side electrode 40 Even if the n-side electrode 40 does not form an Al alloy at the time of formation, the n-side electrode 40 finally becomes an Al alloy in the sintering process after the n-side electrode 40 is formed, and Al atoms If they are in contact with the surface modification layer 23, they belong to the technical scope of this embodiment.
  • the n-side electrode 40 is composed of a Ti / Al film in which titanium (Ti) having a thickness of 10 nm and aluminum (Al) having a thickness of 500 nm are stacked thereon, a sinter is used. Unless the treatment is performed, the surface modified layer 23 and Ti are in direct contact and the surface modified layer 23 and Al are not in contact with each other. However, by performing a sintering process at a high temperature of 500 ° C. or higher, Al is mixed with Ti and alloyed, and as a result, Al atoms come into contact with the surface modification layer 23. In this case, an n-side ohmic electrode having a low contact resistance can be realized. Note that another electrode layer or another wiring layer made of a metal or an alloy may be formed on the p-side electrode 30 and the n-side electrode 40.
  • the thickness of the GaN-based substrate 10 having the m-plane main surface 10a is, for example, 100 ⁇ m to 400 ⁇ m. If the thickness of the substrate is approximately 100 ⁇ m or more, handling of the wafer becomes easy.
  • the GaN-based substrate 10 according to the present embodiment may have a laminated structure as long as it has an m-plane main surface 10a made of a GaN-based material. That is, the GaN-based substrate 10 according to this embodiment includes a substrate in which at least the main surface 10a that is the uppermost surface is an m-plane. Therefore, the entire substrate may be GaN-based or a combination with other materials.
  • the active layer 24 is, for example, a multiple quantum well (MQW) made of GaInN / GaN in which well layers made of Ga 0.9 In 0.1 N and barrier layers made of GaN are alternately stacked. It has a structure.
  • the thicknesses of the well layer and the barrier layer are each 9 nm, for example, and the thickness of the active layer 24 is 81 nm, for example.
  • a p-type nitride semiconductor layer 26 is formed on the active layer 24.
  • the thickness of the p-type nitride semiconductor layer 26 is, for example, not less than 0.2 ⁇ m and not more than 2 ⁇ m.
  • an undoped GaN layer may be provided between the active layer 24 and the p-type nitride semiconductor layer 26.
  • a p-type GaN layer can be formed on the p-type nitride semiconductor layer 26.
  • a contact layer made of p + -GaN may be formed on the p-type GaN layer, and the p-side electrode 30 may be formed on the contact layer.
  • the contact layer made of GaN may be considered as a part of the p-type nitride semiconductor layer 26 instead of being a semiconductor layer different from the p-type nitride semiconductor layer 26.
  • the nitride semiconductor light emitting device 100 may be used as a light source device in this state.
  • a resin material or the like in which a fluorescent material for wavelength conversion is dispersed it can be used as a light source device with an expanded wavelength band, such as a white light source device.
  • FIG. 4 schematically shows a cross-sectional configuration of an example of the light source device.
  • the light source device shown in FIG. 4 converts the nitride semiconductor light emitting device 100 according to this embodiment shown in FIG. 3A and the wavelength of light emitted from the nitride semiconductor light emitting device 100 into a longer wavelength.
  • the nitride semiconductor light emitting device 100 is fixed on a holding member 220 having a wiring pattern 210 formed on the surface thereof.
  • a reflecting member 240 is disposed and fixed so as to surround the nitride semiconductor light emitting element 100.
  • the resin layer 200 is formed inside the reflecting member 240 so as to cover the nitride semiconductor light emitting element 100.
  • the LED element has been described as the nitride semiconductor light emitting element 100 as an example of the embodiment, but the effect of reducing the contact resistance in the n-side electrode 40 is also obtained in a light emitting element other than the LED element, for example, a semiconductor laser element. be able to. Further, this effect is not limited to the light emitting element, and can naturally be obtained in a device such as a transistor or a light receiving element.
  • the main surface or surface of the m-plane semiconductor does not have to be a plane that is completely parallel to the m-plane, and may be inclined at a predetermined angle from the m-plane.
  • the tilt angle is determined by the angle formed by the normal of the main surface in the nitride semiconductor layer and the normal of the non-tilted m-plane.
  • the main surface or surface of the m-plane nitride semiconductor layer can be inclined from the non-inclined m-plane toward the vector direction represented by the c-axis direction and the a-axis direction.
  • the absolute value of the inclination angle ⁇ may be 5 ° or less or 1 ° or less in the c-axis direction.
  • the “m-plane” includes a plane inclined in a predetermined direction from the non-inclined m-plane within a range of ⁇ 5 °. Within such a tilt angle range, the main surface or surface of the nitride semiconductor layer is entirely tilted from the m-plane, but a large number of m-plane regions are exposed microscopically. Conceivable. Thereby, it is considered that the surface inclined at an angle of 5 ° or less from the m-plane has the same properties as the m-plane.
  • the “ ⁇ r plane”, “r plane”, “(20-21) plane”, “(20-2-1) plane”, “(10-1-3) plane” and “( The “11-22) plane” and the “a plane” include a plane inclined in a predetermined direction within a range of ⁇ 5 ° from these non-inclined planes.
  • Non-Patent Document 1 describes that aluminum (Al) can be applied as a material of an n-side electrode for GaN (considering c-plane GaN because it is conventional GaN).
  • Patent Document 2 also describes that Al can be applied as a material for the n-side electrode for GaN.
  • the present inventors first applied aluminum (Al) as an n-side electrode material for m-plane GaN as a basic study experiment, and evaluated its electrical characteristics.
  • the film thickness of Al was 500 nm.
  • the sintering process was performed, it was performed in a nitrogen atmosphere, and the sintering process time was 10 minutes.
  • FIG. 5C shows a schematic configuration of an electrical property evaluation method.
  • two n-side electrodes 51 each having a planar rectangular shape with a thickness of 500 nm, a length of 200 ⁇ m, and a width of 100 ⁇ m are only 20 ⁇ m from each other. Formed apart.
  • FIG. 5A shows the relationship between the voltage between the n-side electrodes 51 and the sintering temperature when a current of 20 mA is applied between the n-side electrodes 51.
  • FIG. 5B shows current-voltage characteristics between the n-side electrodes 51 for each sintering temperature. Since the measurement limit voltage of the evaluation apparatus used in this evaluation is 10V, data exceeding 10V is a reference value. In this specification, unless otherwise specified, the electrical characteristics of the n-side electrode are evaluated by the method described above.
  • ohmic characteristics can be obtained when aluminum (Al) is used as the n-side electrode material on the surface of m-plane GaN without any special treatment. It turned out not to be. Sintering was also attempted, but the properties deteriorated and there was no sign of ohmic properties. Thus, it has been clarified that an ohmic electrode cannot be formed for m-plane GaN even if Al used for c-plane GaN is directly applied as an n-side electrode material.
  • n-side electrode material in order to obtain ohmic characteristics, it is conceivable to change the n-side electrode material from aluminum (Al) to another metal.
  • titanium (Ti) / aluminum (Al) see Patent Document 2
  • Ti titanium
  • Al aluminum
  • the present inventors applied Ti / Al as it is to m-plane GaN as an n-side electrode material provided on c-plane GaN, and evaluated the electrical characteristics.
  • a Ti film and an Al film were sequentially deposited on the main surface of the m-plane GaN.
  • the thickness of the Ti film was 10 nm
  • the thickness of the Al film was 500 nm.
  • 6 (a) and 6 (b) show the results of electrical characteristics when a current of 20 mA is applied to an n-side electrode in which Ti / Al is applied to m-plane GaN.
  • the thickness of the Ti film is 10 nm
  • the thickness of the Al film is 500 nm.
  • a certain amount of n-side ohmic electrode could be formed by performing the sintering process in a high temperature region of 500 ° C. to 600 ° C.
  • further reduction of contact resistance is required. That is, one of the greatest merits of using m-plane GaN as a light-emitting device is that a decrease in output due to a piezoelectric field is suppressed in a large current density region. For this reason, in consideration of operating in a large current density region not used in c-plane GaN, it is important to further reduce contact resistance.
  • FIGS. 7A and 7B a configuration and a manufacturing method thereof for forming an n-side ohmic electrode with reduced contact resistance with respect to m-plane GaN according to the present embodiment. explain.
  • the m-plane GaN layer 50 is selectively irradiated with O 2 plasma to form a surface modification layer 52 on the m-plane GaN layer 50.
  • O 2 plasma for example, RIE-10NR manufactured by samco
  • the pressure of O 2 is 10 Pa
  • the gas flow rate is 40 ml / min (standard state)
  • the RF power is 40 W.
  • a suitable surface modification layer 52 can be formed by irradiating O 2 plasma for 30 seconds.
  • the entire surface of the m-plane GaN layer 50 is not irradiated with O 2 plasma, but only the n-side electrode formation region is irradiated.
  • the resist film covers a portion excluding the n-side electrode formation region. Instead of this, the entire surface of the m-plane GaN layer 50 may be irradiated with O 2 plasma.
  • the surface of the surface modification layer 52 is subjected to an acid treatment.
  • an acid treatment for example, hydrofluoric acid or buffered hydrofluoric acid can be used for the acid treatment.
  • the acid treatment time when using hydrofluoric acid or buffered hydrofluoric acid can be set to 30 seconds, for example.
  • Al is deposited on the surface modification layer 52 as an electrode material.
  • the Al film can be deposited by a vacuum evaporation method (such as a resistance heating method or an electron beam method). Thereby, it will be in the state which the surface modification layer 52 and Al atom contact.
  • the electrode material is not necessarily made of Al alone, but may be a metal layer containing Al as a main component, that is, an Al alloy.
  • FIGS. 8A and 8B show the n electrical characteristics of the n-side electrode formed by “O 2 plasma irradiation + hydrofluoric acid treatment + Al” according to this embodiment when a current of 20 mA is applied. Yes.
  • the thickness of the Al film is 500 nm.
  • a good n-side ohmic electrode is formed on the m-plane GaN without performing the sintering process.
  • the contact resistance is further reduced by performing a sintering process for 10 minutes at a temperature of 200 ° C. or more and 700 ° C. or less in a nitrogen atmosphere.
  • the sintering temperature may be 300 ° C. or more and 600 ° C. or less. In this sintering temperature region, the contact resistance showed the lowest value (specific contact resistance 3 ⁇ 10 ⁇ 5 ⁇ cm 2 ).
  • TLM transmission line matrix
  • FIG. 9 shows the electrical characteristics of the n-side electrode (corresponding to FIG. 8) according to this embodiment “O 2 plasma irradiation + hydrofluoric acid treatment + Al”, and the electrical characteristics of the n-side electrode when Al is applied (FIG. 9). 5), and the electrical characteristics of the n-side electrode when Ti / Al is applied (corresponding to FIG. 6). From FIG. 9, it is clear that the n-side electrode according to the present embodiment has a great advantage.
  • the sintering process for the Al film for the n-side electrode may not be performed. Even if the sintering process is performed at a temperature lower than usual, for example, 300 ° C. or lower, or 500 ° C. or lower, an n-side ohmic electrode having a low contact resistance can be formed. This greatly increases the degree of freedom of design related to the device manufacturing process flow. Also, according to the study by the present inventors, m-plane GaN is more susceptible to heat than c-plane GaN. It is very significant that an n-side ohmic electrode with low contact resistance can be formed without performing sintering on such m-plane GaN.
  • FIG. 10 shows the current-voltage characteristics of the nitride semiconductor light emitting device according to this embodiment, here the LED device.
  • the LED device As can be seen from FIG. 10, by applying the above-described n-side electrode to the nitride semiconductor light emitting device, a significant reduction in operating voltage and a significant variation in electrical characteristics are realized.
  • the device characteristics can be significantly improved by actually applying the n-side electrode according to the present embodiment to a device.
  • the present inventors dare to obtain extremely low contact resistance by using Al as the n-side electrode material and contacting Al atoms with m-plane GaN whose surface has been modified by O 2 plasma irradiation. did it.
  • n-plane GaN is irradiated with O 2 plasma and hydrofluoric acid treatment to modify its surface, and then provided on the c-plane GaN.
  • the electrical characteristics of the n-side electrode when a side electrode material of Ti / Al is deposited and a current of 20 mA is applied are shown.
  • FIG. 12A is a photograph of an optical microscope observed from the back surface of the m-plane GaN layer 50 with respect to a sample in which the presence or absence of sintering treatment and the temperature of sintering treatment were changed in three ways.
  • the main surface of the m-plane GaN layer 50 is irradiated with O 2 plasma and hydrofluoric acid to form a surface modification layer 52 on the surface.
  • an n-side electrode 51 made of Ti / Al was formed.
  • the sample not subjected to the sintering process and the sample subjected to the sintering process at temperatures of 400 ° C., 500 ° C., and 600 ° C. were observed with an optical microscope from the back surface of the m-plane GaN layer 50.
  • the thickness of the Ti film is 10 nm
  • the thickness of the Al film is 500 nm.
  • Ti is in contact with the surface modification layer 52 entirely.
  • Al atoms constituting the n-side electrode 51 are mixed with the Ti film by solid phase diffusion or alloying to break through the Ti film, It can be clearly seen that they are in contact.
  • the sintering process is performed at 600 ° C.
  • Al atoms break through almost the entire surface of the Ti film, both atoms are mixed and alloyed, and almost the entire surface of the interface with the m-plane GaN layer 50 is in contact with the Al atoms. It turns out that it is in a state.
  • n-side electrode material In the usual “metal-semiconductor interface junction theory”, a metal having a smaller work function value is more suitable as an n-side electrode material. Thus, in order to obtain ohmic characteristics, it is necessary to select an electrode material having a work function smaller than the work function value in the semiconductor, in this case, the work function value in the m-plane GaN. According to Non-Patent Document 2 described above, the work function of n-type m-plane GaN is 3.7 eV. Therefore, as an n-side electrode material, an electrode material having a work function smaller than 3.7 eV, that is, in the examination experiment shown in FIG. 14, magnesium (Mg) having a work function value of 3.66 eV is n-side electrode material. Seems to be optimal.
  • Comparative Experiment 1 Comparative Experiment 2, and Comparative Experiment 3 that the combination of m-plane GaN and Al atoms whose surfaces have been modified by O 2 plasma irradiation and hydrofluoric acid treatment is specific. became. That is, when the Al atoms are not in contact with the surface-modified m-plane GaN, the contact resistance becomes extremely high, and when the Al atoms are in contact with the surface-modified m-plane GaN, It was discovered that an n-side ohmic electrode with extremely low contact resistance can be realized.
  • the second conceivable difficulty is that contact resistance is further reduced by adding acid treatment after the O 2 plasma irradiation.
  • Patent Document 4 as a technique for forming an n-side electrode provided on c-plane GaN, a method of depositing Ti / Al after performing O 2 plasma irradiation is disclosed.
  • the purpose of irradiating with O 2 plasma is to form an oxygen (O) doped layer on the outermost surface of GaN by irradiating with O 2 plasma.
  • the O-doped layer is a compound layer of GaN and O in which O is introduced into GaN as a donor. That is, it is expected that a high concentration n-type carrier layer is formed on the outermost surface of GaN by O atoms contributing as donors. Therefore, a technique for reducing the contact resistance of the n-side electrode by increasing the carrier density on the outermost surface is widely known.
  • the O-doped layer on the outermost surface of GaN is important. Therefore, after surface treatment for removing the O-doped layer, that is, after irradiating O 2 plasma, the surface of GaN is treated with an acid. It is totally unreasonable to apply processing.
  • the examination of performing acid treatment after irradiating O 2 plasma is also performed. In this case, as expected, an experimental result was obtained that the electrical characteristics of the n-side electrode deteriorated, and as a result, acid treatment after irradiation with O 2 plasma was completely denied. Thus, acid treatment after irradiation with O 2 plasma is not possible as normal technical common sense.
  • the present inventors perform acid treatment on the surface of GaN after being irradiated with O 2 plasma. Moreover, the acid treatment is performed using hydrofluoric acid (HF), which has an extremely high ability to remove oxygen compounds among acids. According to conventional common general knowledge, if such an acid treatment is performed, the O-doped layer in the vicinity of the outermost surface of GaN is removed, and the electrical characteristics are considered to be greatly deteriorated. On the other hand, the present inventors can realize an n-side electrode having a contact resistance lower than that before hydrofluoric acid treatment by performing hydrofluoric acid treatment on the surface of GaN after being irradiated with O 2 plasma. I found out.
  • HF hydrofluoric acid
  • 15 (a) and 15 (b) show an n-side electrode using Al as the electrode material in each sample without O 2 plasma, O 2 plasma irradiation, and O 2 plasma irradiation + hydrofluoric acid treatment.
  • the result of an electrical property is shown.
  • the sintering process was performed at a temperature of 400 ° C. for 10 minutes.
  • a remarkable effect is exhibited by the combination of depositing an Al film on m-plane GaN whose surface has been modified by O 2 plasma irradiation.
  • FIG. 16A plots the oxygen (O) concentration and the carbon (C) concentration in the depth direction of the GaN layer in the first sample in which the Al film was deposited without irradiating the O 2 plasma. It is a graph.
  • the interface between the Al film and the GaN layer was defined as depth 0, and the GaN layer side was defined as the positive direction. That is, the negative side on the horizontal axis indicates the position in the Al film (electrode), and the positive side indicates the position in the GaN layer.
  • FIG. 16B is a graph in which the O concentration and the C concentration in the second sample in which the Al film is deposited after the O 2 plasma irradiation are plotted in the depth direction of the GaN layer. It can be seen that O atoms increase while C atoms decrease due to the O 2 plasma irradiation.
  • FIG. 16C is a graph in which the concentration of O and the concentration of C in the third sample in which an Al film is deposited after O 2 plasma irradiation and hydrofluoric acid treatment are plotted in the depth direction of the GaN layer. It is. C concentration has not changed after the irradiation of the O 2 plasma, it can be seen that O atoms which is increased by irradiation of O 2 plasma is removed by hydrofluoric acid treatment.
  • O atoms are removed after the hydrofluoric acid treatment. This is because, from the experimental results that the electrical characteristics of the n-side electrode were better after the hydrofluoric acid treatment than before the treatment, the removed O atoms were not caused by the “O-doped layer” but the potential. This is considered to be caused by a surface oxide film or a surface amorphous film that contributes as a barrier. Here, both the surface oxide film and the surface amorphous are expressed as Ga x O y .
  • the depth direction distribution of the carrier density in the vicinity of the surface of the GaN layer is determined using a capacitance-voltage (CV) evaluation method. Examined.
  • the first sample is a m-plane GaN is not irradiated with O 2 plasma
  • the second sample of O 2 plasma is irradiated m-plane GaN, as well as O 2 plasma exposure
  • hydrofluoric acid treatment of the in each went third sample is a m-plane GaN, a plot of carrier density (N D -N a) in the depth direction of the GaN layer. From the second sample, it can be seen that the carrier density in the vicinity of the surface of the GaN layer, that is, the region from the surface to about 150 nm is reduced by the O 2 plasma irradiation. Further, it can be seen from the third sample that the carrier density is almost unchanged even when hydrofluoric acid treatment is performed after the O 2 plasma is irradiated.
  • FIG. 17 (b) a second sample was irradiated with O 2 plasma, and O 2 plasma irradiation and the respective carrier densities of the third sample subjected to hydrofluoric acid treatment, first without irradiating the O 2 plasma
  • the cause of the decrease in carrier density is not clear, for example, as one physical model, crystal defects are formed near the surface of the m-plane GaN layer by O 2 plasma irradiation, and the formed crystal defects trap donor carriers. Therefore, it can be considered that the carrier density decreases.
  • the surface of the m-plane GaN layer was evaluated by photoluminescence.
  • Figure 18 is a first sample not irradiated with O 2 plasma, a second sample was irradiated with O 2 plasma, and for each of the third sample subjected to irradiation and hydrofluoric acid treatment of the O 2 plasma, photo The result of performing luminescence evaluation (PL evaluation) is shown.
  • PL evaluation luminescence evaluation
  • the band edge emission in GaN was reduced by about one digit. This result suggests that crystal defects that can act as non-luminescent centers were formed by O 2 plasma irradiation.
  • no yellow luminescence is observed in the wavelength region of 500 nm to 600 nm due to nitrogen vacancies which are typical crystal defects in GaN.
  • the “surface modified layer” formed in the vicinity of the GaN surface by the O 2 plasma irradiation is defined again.
  • the surface modified layer contains crystal defects.
  • the carrier density is 0.7 nm at a depth of 90 nm from the surface of the GaN layer. Since it is decreased by ⁇ 10 17 cm ⁇ 3 , the crystal defect density in this region is considered to be 0.7 ⁇ 10 17 cm ⁇ 3 .
  • the surface modified layer is defined as a region having a carrier density lower than the carrier density when not irradiated with O 2 plasma. More specifically, for example, it can be defined as a region having a carrier density of 0.9 times or less of the carrier density when not irradiated with O 2 plasma. It is believed that the decrease in carrier density is caused by crystal defects. For example, assuming that one crystal defect traps one carrier, the value of the carrier density ratio becomes 0.9 by forming a crystal defect density of 10% of the donor density.
  • the thickness of the surface modification layer is defined as the depth to a region having a carrier density lower than the carrier density when not irradiated with O 2 plasma. More specifically, for example, it can be defined as the depth to the portion where the value of the carrier density ratio becomes 0.9 as described above. If it defines in this way, in this embodiment, the thickness of a surface modification layer is about 120 nm from FIG.17 (b).
  • the thickness of the surface modification layer may be about 10 nm, for example. Of course, it may be 10 nm or more like 120 nm in the present embodiment. Even when the thickness is 10 nm or less, if the surface modification layer is formed, the contact resistance reduction effect due to the contact between the surface modification layer and the Al atoms can be appropriately obtained.
  • an ohmic electrode having a small contact resistance In order to form an ohmic electrode having a small contact resistance, a technique for increasing the carrier density on the outermost surface on which the electrode is formed is widely used. For example, there is a technique of forming a high carrier density layer by doping a dopant at a high concentration on the outermost surface of a semiconductor layer and forming an electrode thereon.
  • an electrode is formed on m-plane GaN having a reduced carrier density on the outermost surface, that is, m-plane GaN having a modified surface.
  • the electrode material in contact with the surface modified layer exhibits a particularly remarkable effect in a metal mainly composed of aluminum (Al) or aluminum (Al).
  • a metal mainly composed of aluminum (Al) or aluminum (Al) mainly composed of aluminum (Al) or aluminum (Al).
  • a further feature of this embodiment is that the m-plane GaN layer whose surface has been modified by irradiation with O 2 plasma is subjected to acid treatment.
  • Patent Document 4 in general technical common sense, if an acid treatment is performed after irradiating O 2 plasma, an O-doped layer is removed, and thus a region having a high carrier density is removed. The characteristics of the n-side electrode deteriorate. However, in the present embodiment, on the contrary, the contact resistance can be further reduced by performing the acid treatment.
  • the material of the n-side electrode is Al alone (that is, a metal having an Al concentration of 100%), good contact resistance can be obtained.
  • the material of the n-side electrode does not necessarily need to be Al alone.
  • a metal mainly composed of Al may be used. That is, the material of the n-side electrode may be a metal containing Al as a main component and atoms other than Al at the impurity level.
  • the metal which occupies 90 mass% or more of the whole with the Al atom may be sufficient.
  • the metal which occupies more than half (namely, 50 mass% or more) of the whole with Al atom may be sufficient.
  • the material of the n-side electrode is an Al alloy
  • AlSi or AlSiCu may be used.
  • Use of these Al alloys for the n-side electrode can be expected to improve the reliability of the electrode in addition to reducing the contact resistance.
  • the Al concentration may be 98% by mass or more, and the Si and Cu concentrations may be 2% by mass or less.
  • FIG. 19 shows a profile in the depth direction of Ga atoms before the heat treatment.
  • a secondary ion mass spectrometer Secondary ion mass spectrometer: SIMS
  • the position indicated by a broken line near the depth of 200 nm from the surface corresponds to the interface between the Al electrode and n-GaN.
  • oxygen plasma treatment is not performed ( ⁇ mark)
  • ⁇ mark when oxygen plasma treatment is performed ( ⁇ mark)
  • BHF buffereuffered hydrofluoric acid
  • the concentration of Ga atoms in n-GaN decreases when oxygen plasma treatment is performed and when treatment with BHF is performed after oxygen plasma treatment. Observed. From this result, it is considered that Ga atoms diffuse from the n-GaN to the interface between the Al electrode and n-GaN when the oxygen plasma treatment is performed and when the treatment is performed with BHF after the oxygen plasma treatment. This suggests that Ga vacancies are formed in n-GaN due to the diffusion of Ga atoms.
  • FIG. 20 shows the result when a sintering process is performed at a temperature of 500 ° C. for 10 minutes.
  • Ga atoms diffused at the interface between the Al electrode and n-GaN before the sintering process are further diffused to the Al electrode side, and no pile-up is observed.
  • the concentration of Ga atoms in n-GaN decreases when oxygen plasma treatment is performed (marked with ⁇ ) and when treated with GHF after oxygen plasma treatment (marked with ⁇ ). You can see that This result also suggests that Ga vacancies are formed in n-GaN due to the diffusion of Ga atoms.
  • FIG. 21 shows a change in voltage during energization of 100 mA between the test patterns constituting the n-side electrode when the plasma power, the oxygen flow rate, and the plasma processing time are changed.
  • the arrangement of the n-side electrode test pattern is shown in the figure.
  • the distance between the electrodes here is 20 ⁇ m.
  • the voltage between these two n-side electrodes is measured, and the voltage reflects the contact resistance at the n-side electrode.
  • a low voltage suggests a low contact resistance.
  • the plasma power is 10 W
  • the oxygen flow rate is 30 ml / min (0 ° C., 1 atm)
  • the treatment time is 300 s. Comparing the first process (I) and the second process (II), it can be seen that the voltage of the second process (II) is lower. This indicates that the contact resistance of the n-side electrode is decreased by increasing the processing time of the oxygen plasma. Furthermore, the case where plasma power differs is compared.
  • the first process is compared with the third process (III) when the plasma power is 40 W
  • the oxygen flow rate is 30 ml / min (0 ° C., 1 atm)
  • the process time is 30 s
  • the contact resistance of the n-side electrode decreases by increasing the plasma power, increasing the oxygen flow rate, and increasing the processing time.
  • Increasing the plasma power, increasing the oxygen flow rate, and increasing the processing time is nothing but increasing the impact energy by physical sputtering imparted to the n-GaN layer by the plasma processing.
  • 19 and 20 together with the results of elemental analysis it is shown that Ga vacancies are formed in the n-GaN layer by plasma treatment, the Ga vacancies increase, and the contact resistance decreases. ing.
  • FIG. 22 shows the relationship between plasma input power and contact resistance value.
  • the plasma power is increased from 10 W to around 40 W, a decrease in contact resistance is observed. Very good low contact resistance is exhibited up to a plasma power of about 120 W.
  • the plasma power increases beyond 120 W, the contact resistance starts to increase. That is, the plasma power has an optimum value in the vicinity of 40W to 120W. This is considered that when the plasma power is extremely low, the Ga vacancy concentration is low and the contact resistance cannot be reduced.
  • the plasma power is too high and the impact energy is too high, the concentration of defects other than Ga vacancies, such as nitrogen vacancies and their composite defects, will increase, and the effect of Ga vacancies Screening for defects is thought to increase contact resistance.
  • FIG. 23 shows the area A shown in FIG. 3 in an enlarged manner.
  • the nitride semiconductor multilayer structure includes an n-side electrode 40 and an n-type nitride semiconductor layer 22 having a surface modification layer 23 having a nonpolar surface or a semipolar surface.
  • the n-side electrode 40 includes an aluminum portion 40a.
  • Aluminum portion 40 a is in contact with the surface of n-type nitride semiconductor layer 22.
  • the surface modified layer of the n-type nitride semiconductor layer 22 in contact with the aluminum portion 40a due to Ga vacancies formed in the surface modified layer 23.
  • the concentration of nitrogen (N) atoms in 23 is higher than the concentration of gallium (Ga) atoms in the surface modification layer 23 of the n-type nitride semiconductor layer 22 in contact with the aluminum portion 40a.
  • the following surface layer 23 having Ga vacancies may have a thickness of 10 nm or more and 150 nm or less.
  • the n-side electrode 40 is composed of an aluminum portion 40a and a metal portion 40b formed thereon.
  • the aluminum part 40a may be formed only from aluminum (Al).
  • the metal part 40b can also be formed only from aluminum (Al). In other words, the entire n-side electrode 40 can be formed only from aluminum.
  • the metal part 40b can be formed from metals other than aluminum. Examples of such metals are platinum (Pt), nickel (Ni), gold (Au), titanium (Ti), or palladium (Pd).
  • the aluminum portion 40a and the metal portion 40b may be layered, and the interface thereof may be parallel or substantially parallel to the n-type nitride semiconductor layer 22.
  • the aluminum portion 40 a having a layer shape may be sandwiched between the metal portion 40 b having a layer shape and the n-type nitride semiconductor layer 22.
  • the metal portion 40 b is not in contact with the n-type nitride semiconductor layer 22.
  • FIG. 24 shows a first modification of the configuration shown in FIG.
  • the aluminum alloy part 40c may be formed between the aluminum part 40a and the metal part 40b.
  • a part of the aluminum part 40a and a part of the metal part 40 may be alloyed at the interface between the aluminum part 40a and the metal part 40b to form the aluminum alloy part 40c.
  • the aluminum alloy portion 40c is formed of an aluminum-platinum (AlPt) alloy, an aluminum-nickel (AlNi) alloy, an aluminum-gold (AlAu) alloy, an aluminum-titanium (AlTi) alloy, or an aluminum-palladium (AlPd) alloy. Can do.
  • the aluminum alloy portion 40c may also have a layer shape.
  • FIGS. 25 and 26 show a second modification and a third modification.
  • a plurality of divided aluminum portions 40a may be formed on the surface modification layer 23 of the n-type nitride semiconductor layer 22, respectively.
  • the surface modification layer of the n-type nitride semiconductor layer 22 so that the metal portion 40b or the aluminum alloy portion 40c covers the plurality of aluminum portions 40a. 23 may be in contact.
  • the present invention can be used for light emitting elements such as LED elements, for example.

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Abstract

This nitride semiconductor light emitting element is provided with: an n-side electrode (40); a p-side electrode (30); an n-type nitride semiconductor layer (22) that has a nonpolar or semi-polar surface; a p-type nitride semiconductor layer (26) that is electrically connected to the p-side electrode; and an active layer (24) that is sandwiched between the n-type nitride semiconductor layer and the p-type nitride semiconductor layer. The n-side electrode (40) has an aluminum part, and the aluminum part is in contact with the surface of the n-type nitride semiconductor layer. The nitrogen atom concentration in the surface of the n-type nitride semiconductor layer, said surface being in contact with the aluminum part, is higher than the gallium atom concentration in the surface of the n-type nitride semiconductor layer, said surface being in contact with the aluminum part.

Description

窒化物半導体積層構造、その窒化物半導体積層構造を備えた窒化物半導体発光素子、及びその窒化物半導体積層構造の製造方法Nitride semiconductor multilayer structure, nitride semiconductor light emitting device including the nitride semiconductor multilayer structure, and method for manufacturing the nitride semiconductor multilayer structure
 本発明は、非極性面又は半極性面である表面を有するn型窒化物半導体層を含む窒化物半導体積層構造、その窒化物半導体積層構造を備えた窒化物半導体発光素子、及びその窒化物半導体積層構造の製造方法に関する。 The present invention relates to a nitride semiconductor multilayer structure including an n-type nitride semiconductor layer having a nonpolar or semipolar surface, a nitride semiconductor light emitting device including the nitride semiconductor multilayer structure, and the nitride semiconductor The present invention relates to a method for manufacturing a laminated structure.
 V族元素に窒素(N)を有する窒化物半導体は、そのバンドギャップの大きさから、短波長発光素子の材料として有望視されている。なかでも、窒化ガリウム系化合物半導体(GaN系半導体:AlGaInN(但し、x+y+z=1,0≦x,z<1、0<y≦1である。))の研究は盛んに行われており、青色発光ダイオード(LED)素子、緑色LED素子、及び青色半導体レーザ素子も実用化されている。 A nitride semiconductor having nitrogen (N) as a group V element is considered promising as a material for a short-wavelength light-emitting element because of its band gap. In particular, research on gallium nitride-based compound semiconductors (GaN-based semiconductors: Al x Ga y In z N (where x + y + z = 1, 0 ≦ x, z <1, 0 <y ≦ 1)) is active. Blue light emitting diode (LED) elements, green LED elements, and blue semiconductor laser elements have also been put into practical use.
 GaN系半導体は、ウルツ鉱型結晶構造を有している。図1は、GaNの単位格子を模式的に表している。GaN系半導体は、図1に示すガリウム(Ga)の一部がアルミニウム(Al)及びインジウム(In)の少なくとも一方で置換され得る。 A GaN-based semiconductor has a wurtzite crystal structure. FIG. 1 schematically shows a unit cell of GaN. In the GaN-based semiconductor, a part of gallium (Ga) shown in FIG. 1 can be replaced with at least one of aluminum (Al) and indium (In).
 図2(a)、図2(b)及び図2(c)は、ウルツ鉱型結晶構造の面方位を4指数表記(六方晶指数)で表している。4指数表記では、a、a、a及びcで表される基本ベクトルを用いて結晶面及びその面方位が表される。基本ベクトルcは、[0001]方向に延びており、この方向は「c軸」と呼ばれる。c軸に垂直な面(plane)は「c面」又は「(0001)面」と呼ばれる。図2(a)には、c面の他に、a面「=(11-20)面」及びm面「=(1-100)面」を示している。また、図2(b)には、r面「=(1-102)面」を示し、図2(c)には、(11-22)面を示している。なお、本明細書においては、ミラー指数を表すカッコ内の数字の左側に付された符号「-」は、その指数の反転を便宜的に表しており、図中の「バー」と対応する。 2 (a), 2 (b), and 2 (c) show the plane orientation of the wurtzite crystal structure in four-index notation (hexagonal crystal index). In the 4-index notation, the crystal plane and its plane orientation are represented using basic vectors represented by a 1 , a 2 , a 3 and c. The basic vector c extends in the [0001] direction, and this direction is called “c-axis”. A plane perpendicular to the c-axis is called a “c-plane” or “(0001) plane”. FIG. 2A shows an a-plane “= (11-20) plane” and an m-plane “= (1-100) plane” in addition to the c-plane. FIG. 2B shows the r plane “= (1-102) plane”, and FIG. 2C shows the (11-22) plane. In the present specification, the symbol “-” attached to the left side of the number in parentheses representing the Miller index represents the inversion of the index for convenience, and corresponds to “bar” in the figure.
 従来から、GaN系半導体を用いて半導体素子を作製する場合は、GaN系半導体結晶を成長させる基板として、c面基板、すなわち(0001)面を主面とする基板が用いられている。しかしながら、c面においては、ガリウム(Ga)の原子層と窒素(N)の原子層との配置がc軸方向に僅かにずれているため、自発的な分極(ElectricalPolarization)が生成される。このため、「c面」は「極性面」とも呼ばれる。分極の結果、窒化物半導体発光素子の活性層を構成するInGaNからなる量子井戸層には、c軸方向に沿ってピエゾ電界が発生する。ピエゾ電界が活性層に発生すると、活性層内における電子及びホールの分布に位置ずれが生じ、キャリアの量子閉じ込めシュタルク効果によって、活性層の内部量子効率が低下する。このため、半導体レーザ素子であれば、しきい値電流の増大が引き起こされる。LED素子であれば、消費電力の増大及び発光効率の低下が引き起こされる。また、注入キャリア密度の上昇と共にピエゾ電界のスクリーニングが起こるため、発光波長にも変化が生じる。 Conventionally, when manufacturing a semiconductor element using a GaN-based semiconductor, a c-plane substrate, that is, a substrate having a (0001) plane as a main surface is used as a substrate on which a GaN-based semiconductor crystal is grown. However, in the c-plane, since the arrangement of the atomic layer of gallium (Ga) and the atomic layer of nitrogen (N) is slightly shifted in the c-axis direction, spontaneous polarization (Electrical Polarization) is generated. For this reason, the “c plane” is also called a “polar plane”. As a result of polarization, a piezo electric field is generated along the c-axis direction in the quantum well layer made of InGaN constituting the active layer of the nitride semiconductor light emitting device. When a piezo electric field is generated in the active layer, a position shift occurs in the distribution of electrons and holes in the active layer, and the internal quantum efficiency of the active layer is reduced due to the quantum confinement Stark effect of carriers. For this reason, in the case of a semiconductor laser element, an increase in threshold current is caused. If it is an LED element, the increase in power consumption and the fall of luminous efficiency will be caused. In addition, since the piezo electric field screening occurs as the injected carrier density increases, the emission wavelength also changes.
 そこで、近年、非極性面である、例えば[10-10]方向に垂直な、m面と呼ばれる(10-10)面を主面とする基板(m面GaN系基板)を用いることが検討されている。m面は、図2(a)に示すように、c軸(基本ベクトルc)に平行な面であり、c面と直交している。m面においては、Ga原子とN原子とは同一原子面上に位置するため、m面に垂直な方向に分極は発生しない。このため、m面に垂直な方向に半導体積層構造を形成すれば、活性層にピエゾ電界が発生しないので、キャリアの量子閉じ込めシュタルク効果による内部量子効率の低下という問題を解決することができる。このことは、m面以外の非極性面でも同様であり、また、半極性面でも類似の効果を得ることができる。 Therefore, in recent years, it has been studied to use a substrate (m-plane GaN-based substrate) that has a (10-10) plane called a m-plane, which is a nonpolar plane, for example, perpendicular to the [10-10] direction. ing. As shown in FIG. 2A, the m plane is a plane parallel to the c axis (basic vector c) and is orthogonal to the c plane. In the m plane, Ga atoms and N atoms are located on the same atomic plane, and therefore no polarization occurs in a direction perpendicular to the m plane. For this reason, if a semiconductor multilayer structure is formed in a direction perpendicular to the m-plane, a piezoelectric field is not generated in the active layer, so that the problem of a decrease in internal quantum efficiency due to the quantum confinement Stark effect of carriers can be solved. This is the same for non-polar surfaces other than the m-plane, and a similar effect can be obtained for a semi-polar surface.
 m面は、(10-10)面、(-1010)面、(1-100)面、(-1100)面、(01-10)面及び(0-110)面の総称である。なお、本明細書では、「X面成長」とは、六方晶ウルツ鉱構造のX面(X=c、m等)に垂直な方向にエピタキシャル成長が生じることを意味する。X面成長において、X面を「成長面」と称し、X面成長によって形成された半導体の層を「X面半導体層」と称する場合がある。 The m-plane is a general term for the (10-10) plane, the (-1010) plane, the (1-100) plane, the (-1100) plane, the (01-10) plane, and the (0-110) plane. In this specification, “X-plane growth” means that epitaxial growth occurs in a direction perpendicular to the X-plane (X = c, m, etc.) of the hexagonal wurtzite structure. In X-plane growth, the X plane may be referred to as a “growth plane”, and a semiconductor layer formed by the X plane growth may be referred to as an “X plane semiconductor layer”.
特許第4605193号公報Japanese Patent No. 4605193 特開昭55-9442号公報Japanese Patent Laid-Open No. 55-9442 特許第2783349号公報Japanese Patent No. 2783349 特許第2967743号公報Japanese Patent No. 2967743
 しかしながら、上記従来の技術においては、コンタクト抵抗の低減が求められていた。 However, in the above conventional technique, reduction of contact resistance has been demanded.
 本発明は、この課題に鑑みてなされたものであり、コンタクト抵抗を低減できるようにすることを目的とする。 The present invention has been made in view of this problem, and an object thereof is to reduce contact resistance.
 上記の課題を解決するために、本発明の一態様の窒化物半導体積層構造は、n側電極、及び非極性面又は半極性面の表面を有するn型窒化物半導体層を具備する。n側電極はアルミニウム部分を具備し、アルミニウム部分はn型窒化物半導体層の表面と接しており、アルミニウム部分と接しているn型窒化物半導体層の表面における窒素原子の濃度は、アルミニウム部分と接しているn型窒化物半導体層の表面におけるガリウム原子の濃度よりも高い。 In order to solve the above problems, the nitride semiconductor multilayer structure of one embodiment of the present invention includes an n-side electrode and an n-type nitride semiconductor layer having a nonpolar or semipolar surface. The n-side electrode includes an aluminum portion, the aluminum portion is in contact with the surface of the n-type nitride semiconductor layer, and the concentration of nitrogen atoms on the surface of the n-type nitride semiconductor layer in contact with the aluminum portion is It is higher than the concentration of gallium atoms on the surface of the n-type nitride semiconductor layer that is in contact.
 また、本発明の他の態様は、窒化物半導体発光素子であって、以下を具備する:n側電極、p側電極、非極性面又は半極性面の表面を有するn型窒化物半導体層、p側電極に電気的に接続されたp型窒化物半導体層、及びn型窒化物半導体層及びp型窒化物半導体層の間に挟まれた活性層。n側電極はアルミニウム部分を具備する。アルミニウム部分はn型窒化物半導体層の表面と接している。アルミニウム部分と接しているn型窒化物半導体層の表面における窒素原子の濃度は、アルミニウム部分と接しているn型窒化物半導体層の表面におけるガリウム原子の濃度よりも高い。 Another embodiment of the present invention is a nitride semiconductor light emitting device comprising the following: an n-side electrode, a p-side electrode, an n-type nitride semiconductor layer having a nonpolar or semipolar surface, A p-type nitride semiconductor layer electrically connected to the p-side electrode, and an active layer sandwiched between the n-type nitride semiconductor layer and the p-type nitride semiconductor layer. The n-side electrode includes an aluminum portion. The aluminum portion is in contact with the surface of the n-type nitride semiconductor layer. The concentration of nitrogen atoms on the surface of the n-type nitride semiconductor layer in contact with the aluminum portion is higher than the concentration of gallium atoms on the surface of the n-type nitride semiconductor layer in contact with the aluminum portion.
 また、本発明の他の態様は、窒化物半導体発光素子と、窒化物半導体発光素子から放射された光の波長を変換する蛍光物質を含む波長変換部とを備えた光源装置である。 Further, another aspect of the present invention is a light source device including a nitride semiconductor light emitting device and a wavelength conversion unit including a fluorescent material that converts the wavelength of light emitted from the nitride semiconductor light emitting device.
 また、本発明の他の態様は、窒化物半導体積層構造を製造する方法であって、以下の工程を具備する:(a)非極性面又は半極性面の表面を有するn型窒化物半導体層の表面を酸素プラズマで照射する工程、(b)工程(a)において酸素プラズマで照射された表面を酸に接触させる工程、及び(c)工程(b)において酸に接触された表面に、アルミニウム部分を形成する工程。 Another aspect of the present invention is a method for manufacturing a nitride semiconductor multilayer structure, which includes the following steps: (a) an n-type nitride semiconductor layer having a nonpolar or semipolar surface. Irradiating the surface of the substrate with oxygen plasma, (b) contacting the surface irradiated with the oxygen plasma in step (a) with acid, and (c) contacting the surface with the acid in step (b) with aluminum. Forming a portion;
 本発明によれば、コンタクト抵抗を低減することができる。 According to the present invention, the contact resistance can be reduced.
図1はGaN系半導体の結晶構造を棒球モデルで表した図である。FIG. 1 is a diagram showing a crystal structure of a GaN-based semiconductor in a stick ball model. 図2(a)はウルツ鉱型結晶構造の基本ベクトルa、a、a及びcと、a面、c面及びm面とを示す斜視図である。図2(b)はウルツ鉱型結晶構造のr面を示す斜視図である。図2(c)はウルツ鉱型結晶構造の(11-22)面を示す斜視図である。FIG. 2A is a perspective view showing the basic vectors a 1 , a 2 , a 3 and c of the wurtzite crystal structure and the a, c and m planes. FIG. 2B is a perspective view showing the r-plane of the wurtzite crystal structure. FIG. 2C is a perspective view showing the (11-22) plane of the wurtzite crystal structure. 図3(a)は一実施形態に係る窒化物半導体発光素子を示す模式的な断面図である。図3(b)は窒化物半導体におけるm面の結晶構造を棒球モデルで表した図である。図3(c)は窒化物半導体におけるc面の結晶構造を棒球モデルで表した図である。FIG. 3A is a schematic cross-sectional view showing a nitride semiconductor light emitting device according to an embodiment. FIG. 3B is a diagram showing the crystal structure of the m-plane in the nitride semiconductor by a stick ball model. FIG. 3C is a diagram showing the crystal structure of the c-plane in the nitride semiconductor by a stick ball model. 図4は一実施形態に係る光源装置を示す模式的な断面図である。FIG. 4 is a schematic cross-sectional view showing a light source device according to an embodiment. 図5(a)及び図5(b)は参考例であって、m面GaNにアルミニウム(Al)を適用したn側電極の電気特性を示し、図5(a)はn側電極間の電圧とシンター温度との関係を示すグラフであり、図5(b)はn側電極間の電流-電圧特性をシンター温度ごとに示すグラフである。図5(c)は電気特性を評価する評価方法を示す概略図である。5 (a) and 5 (b) are reference examples showing the electrical characteristics of an n-side electrode in which aluminum (Al) is applied to m-plane GaN, and FIG. 5 (a) shows the voltage between the n-side electrodes. FIG. 5B is a graph showing the current-voltage characteristics between the n-side electrodes for each sinter temperature. FIG. 5C is a schematic diagram showing an evaluation method for evaluating electrical characteristics. 図6(a)及び図6(b)は参考例であって、m面GaNにチタン(Ti)/アルミニウム(Al)の積層膜を適用したn側電極の電気特性を示し、図6(a)はn側電極間の電圧とシンター温度との関係を示すグラフであり、図6(b)はn側電極間の電流-電圧特性をシンター温度ごとに示すグラフである。6 (a) and 6 (b) are reference examples, showing electrical characteristics of an n-side electrode in which a laminated film of titanium (Ti) / aluminum (Al) is applied to m-plane GaN, and FIG. ) Is a graph showing the relationship between the voltage between the n-side electrodes and the sintering temperature, and FIG. 6B is a graph showing the current-voltage characteristics between the n-side electrodes for each sintering temperature. 図7(a)及び(b)は一実施形態に係る窒化物半導体積層構造の製造方法を示す工程順の模式断面図である。7A and 7B are schematic cross-sectional views in order of steps showing the method for manufacturing a nitride semiconductor multilayer structure according to one embodiment. 図8(a)及び図8(b)は一実施形態に係る窒化物半導体積層構造におけるn側電極の電気特性を示し、図8(a)はn側電極間の電圧とシンター温度との関係を示すグラフであり、図8(b)はn側電極間の電流-電圧特性をシンター温度ごとに示すグラフである。8A and 8B show the electrical characteristics of the n-side electrode in the nitride semiconductor multilayer structure according to one embodiment, and FIG. 8A shows the relationship between the voltage between the n-side electrodes and the sintering temperature. FIG. 8B is a graph showing the current-voltage characteristics between the n-side electrodes for each sintering temperature. 図9は一実施形態に係る窒化物半導体積層構造におけるn側電極の電気特性と、Alを適用したn側電極及びTi/Alを適用したn側電極との各電気特性とを比較して示したグラフである。FIG. 9 shows a comparison between the electrical characteristics of the n-side electrode in the nitride semiconductor multilayer structure according to one embodiment and the electrical characteristics of the n-side electrode to which Al is applied and the n-side electrode to which Ti / Al is applied. It is a graph. 図10は一実施形態に係る窒化物半導体発光素子における電流-電圧特性を、Ti/Alを適用したn側電極を有する窒化物半導体発光素子と比較したグラフである。FIG. 10 is a graph comparing current-voltage characteristics of a nitride semiconductor light emitting device according to one embodiment with a nitride semiconductor light emitting device having an n-side electrode to which Ti / Al is applied. 図11(a)及び図11(b)は参考例であって、「Oプラズマ照射+フッ酸処理」を施したm面GaNにTi/Alの積層膜を適用したn側電極の電気特性を示し、図11(a)はn側電極間の電圧とシンター温度との関係を示すグラフであり、図11(b)はn側電極間の電流-電圧特性をシンター温度ごとに示すグラフである。FIGS. 11A and 11B are reference examples, and the electrical characteristics of an n-side electrode in which a Ti / Al laminated film is applied to m-plane GaN subjected to “O 2 plasma irradiation + hydrofluoric acid treatment”. FIG. 11A is a graph showing the relationship between the voltage between the n-side electrodes and the sintering temperature, and FIG. 11B is a graph showing the current-voltage characteristics between the n-side electrodes for each sintering temperature. is there. 図12(a)は参考例であって、「Oプラズマ照射+フッ酸処理」を施したm面GaNにTi/Alの積層膜を適用したn側電極に対してシンター処理を行わない場合を含め、シンター処理の温度別に裏面から光学顕微鏡により観察した写真である。図12(b)は観察方法を示す概略の断面図である。FIG. 12A is a reference example, in which no sintering treatment is performed on an n-side electrode in which a Ti / Al laminated film is applied to m-plane GaN subjected to “O 2 plasma irradiation + hydrofluoric acid treatment”. Are photographs observed with an optical microscope from the back side according to the sintering temperature. FIG. 12B is a schematic cross-sectional view showing an observation method. 図13(a)及び図13(b)は参考例であって、「Oプラズマ照射+フッ酸処理」を施したm面GaNにTiを適用したn側電極の電気特性を示し、図13(a)はn側電極間の電圧とシンター温度との関係を示すグラフであり、図13(b)はn側電極間の電流-電圧特性をシンター温度ごとに示すグラフである。FIGS. 13A and 13B are reference examples, and show the electrical characteristics of an n-side electrode in which Ti is applied to m-plane GaN subjected to “O 2 plasma irradiation + hydrofluoric acid treatment”. (A) is a graph showing the relationship between the voltage between the n-side electrodes and the sintering temperature, and FIG. 13 (b) is a graph showing the current-voltage characteristics between the n-side electrodes for each sintering temperature. 図14(a)及び図14(b)は「Oプラズマ照射+フッ酸処理」を施したm面GaNに、種々の金属材料を適用したn側電極の電気特性を示し、図14(a)はn側電極間のそれぞれの電圧を示すグラフであり、図14(b)はn側電極間の電流-電圧特性を金属材料ごとに示すグラフである。14 (a) and 14 (b) show the electrical characteristics of an n-side electrode in which various metal materials are applied to m-plane GaN subjected to “O 2 plasma irradiation + hydrofluoric acid treatment”. ) Is a graph showing respective voltages between the n-side electrodes, and FIG. 14B is a graph showing current-voltage characteristics between the n-side electrodes for each metal material. 図15(a)及び図15(b)はm面GaNに対して「Oプラズマなし」、「Oプラズマ照射」及び「Oプラズマ照射+フッ酸処理」が施されたm面GaNにAlを適用したn側電極の電気特性を示し、図15(a)はn側電極間のそれぞれの電圧を示すグラフであり、図15(b)はn側電極間のそれぞれの電流-電圧特性を示すグラフである。15 (a) and 15 (b) show an example of m-plane GaN subjected to “no O 2 plasma”, “O 2 plasma irradiation” and “O 2 plasma irradiation + hydrofluoric acid treatment” for m-plane GaN. FIG. 15A is a graph showing each voltage between the n-side electrodes, and FIG. 15B is a current-voltage characteristic between the n-side electrodes. It is a graph which shows. 図16(a)~図16(c)はm面GaNにAlを適用したn側電極を有するm面GaNにおける酸素(O)濃度及び炭素(C)濃度の深さ依存性を示し、図16(a)はm面GaNにOプラズマを照射しない場合のグラフであり、図16(b)はm面GaNにOプラズマを照射した場合のグラフであり、図16(c)はm面GaNにOプラズマの照射及びフッ酸処理を施した場合のグラフである。16 (a) to 16 (c) show the depth dependence of oxygen (O) concentration and carbon (C) concentration in m-plane GaN having an n-side electrode in which Al is applied to m-plane GaN. (A) is a graph when not irradiating m-plane GaN with O 2 plasma, FIG. 16 (b) is a graph when m-plane GaN is irradiated with O 2 plasma, and FIG. 16 (c) is m-plane. it is a graph when subjected to irradiation and hydrofluoric acid treatment of the O 2 plasma GaN. 図17(a)はOプラズマを照射しない試料、Oプラズマを照射した試料、並びにOプラズマ照射及びフッ酸処理を施した試料のそれぞれに対して、キャリア密度の深さ依存性を示すグラフである。図17(b)は図17(a)の縦軸をOプラズマなしの場合で規格化したグラフである。FIG. 17 (a) not irradiated with O 2 plasma samples, the sample was irradiated with O 2 plasma, and with respect to O 2 plasma irradiation and each sample subjected to hydrofluoric acid treatment, indicating the depth dependence of the carrier density It is a graph. FIG. 17B is a graph in which the vertical axis of FIG. 17A is normalized with no O 2 plasma. 図18はOプラズマを照射しない試料、Oプラズマを照射した試料、並びにOプラズマ照射及びフッ酸処理を施した試料のそれぞれに対して、フォトルミネッセンスを評価した評価結果を示すグラフである。Figure 18 is a sample not irradiated with O 2 plasma, the sample was irradiated with O 2 plasma, and with respect to O 2 plasma irradiation and each sample subjected to hydrofluoric acid treatment, is a graph showing the evaluation results of evaluating the photoluminescence . 図19は熱処理前のGa原子の深さ方向のプロファイルを示すグラフである。FIG. 19 is a graph showing a profile in the depth direction of Ga atoms before heat treatment. 図20はシンター処理後のGa原子の深さ方向のプロファイルを示すグラフである。FIG. 20 is a graph showing a profile of Ga atoms in the depth direction after sintering. 図21はn側電極を構成するテストパターン同士の間に生じる電圧とプラズマ処理条件との関係を表すグラフである。FIG. 21 is a graph showing the relationship between the voltage generated between the test patterns constituting the n-side electrode and the plasma processing conditions. 図22はプラズマの投入パワーとコンタクト抵抗値との関係を表すグラフである。FIG. 22 is a graph showing the relationship between plasma input power and contact resistance value. 図23は図3に示す領域Aを拡大した部分断面図である。FIG. 23 is an enlarged partial cross-sectional view of region A shown in FIG. 図24は図3に示す構成の第1変形例に係る部分断面図である。FIG. 24 is a partial cross-sectional view according to a first modification of the configuration shown in FIG. 図25は図3に示す構成の第2変形例に係る部分断面図である。25 is a partial cross-sectional view according to a second modification of the configuration shown in FIG. 図26は図3に示す構成の第3変形例に係る部分断面図である。FIG. 26 is a partial cross-sectional view according to a third modification of the configuration shown in FIG.
 本開示の一形態は、窒化物半導体積層構造であって、以下を具備する:n側電極、及び非極性面又は半極性面の表面を有するn型窒化物半導体層、ここで、n側電極は、アルミニウム部分を具備し、アルミニウム部分は、n型窒化物半導体層の表面と接しており、アルミニウム部分と接しているn型窒化物半導体層の表面における窒素原子の濃度は、アルミニウム部分と接しているn型窒化物半導体層の表面におけるガリウム原子の濃度よりも高い。 One form of the present disclosure is a nitride semiconductor multilayer structure including the following: an n-side electrode, and an n-type nitride semiconductor layer having a nonpolar or semipolar surface, where the n-side electrode Comprises an aluminum portion, the aluminum portion is in contact with the surface of the n-type nitride semiconductor layer, and the concentration of nitrogen atoms on the surface of the n-type nitride semiconductor layer in contact with the aluminum portion is in contact with the aluminum portion. It is higher than the concentration of gallium atoms on the surface of the n-type nitride semiconductor layer.
 一形態に係る窒化物半導体積層構造であって、アルミニウム部分は、アルミニウムのみからなっていてもよい。 In the nitride semiconductor multilayer structure according to one embodiment, the aluminum portion may be made of only aluminum.
 一形態に係る窒化物半導体積層構造であって、アルミニウム部分は、n型窒化物半導体層と平行な層状を有していてもよい。 In the nitride semiconductor multilayer structure according to one embodiment, the aluminum portion may have a layer shape parallel to the n-type nitride semiconductor layer.
 一形態に係る窒化物半導体積層構造には、複数のアルミニウム部分が設けられていてもよい。 A plurality of aluminum portions may be provided in the nitride semiconductor multilayer structure according to one embodiment.
 一形態に係る窒化物半導体積層構造であって、アルミニウム部分と接しているn型窒化物半導体層の表面は、ガリウムの空孔を有していてもよい。 In the nitride semiconductor multilayer structure according to one embodiment, the surface of the n-type nitride semiconductor layer in contact with the aluminum portion may have gallium vacancies.
 一形態に係る窒化物半導体積層構造であって、アルミニウム部分と接しているn型窒化物半導体層の表面領域は、10nm以上且つ150nm以下の厚さを有していてもよい。 In the nitride semiconductor multilayer structure according to one embodiment, the surface region of the n-type nitride semiconductor layer in contact with the aluminum portion may have a thickness of 10 nm or more and 150 nm or less.
 一形態に係る窒化物半導体積層構造であって、n型窒化物半導体層は、m面の表面を有していてもよい。 In the nitride semiconductor multilayer structure according to one embodiment, the n-type nitride semiconductor layer may have an m-plane surface.
 一形態に係る窒化物半導体積層構造であって、アルミニウム部分と接しているn型窒化物半導体層の表面は、アルミニウム部分と接していないn型窒化物半導体層の部分よりも低いキャリア密度を有していてもよい。 In the nitride semiconductor multilayer structure according to one embodiment, the surface of the n-type nitride semiconductor layer in contact with the aluminum portion has a lower carrier density than the portion of the n-type nitride semiconductor layer not in contact with the aluminum portion. You may do it.
 また、本開示の他の形態は、窒化物半導体発光素子であって、以下を具備する:n側電極、p側電極、非極性面又は半極性面の表面を有するn型窒化物半導体層、p側電極に電気的に接続されたp型窒化物半導体層、及びn型窒化物半導体層及びp型窒化物半導体層の間に挟まれた活性層、ここで、n側電極は、アルミニウム部分を具備し、アルミニウム部分は、n型窒化物半導体層の表面と接しており、アルミニウム部分と接しているn型窒化物半導体層の表面における窒素原子の濃度は、アルミニウム部分と接しているn型窒化物半導体層の表面におけるガリウム原子の濃度よりも高い。 Further, another embodiment of the present disclosure is a nitride semiconductor light emitting device including the following: an n-type electrode, a p-side electrode, an n-type nitride semiconductor layer having a nonpolar surface or a semipolar surface, a p-type nitride semiconductor layer electrically connected to the p-side electrode, and an active layer sandwiched between the n-type nitride semiconductor layer and the p-type nitride semiconductor layer, wherein the n-side electrode is an aluminum portion And the aluminum portion is in contact with the surface of the n-type nitride semiconductor layer, and the concentration of nitrogen atoms in the surface of the n-type nitride semiconductor layer in contact with the aluminum portion is n-type in contact with the aluminum portion. It is higher than the concentration of gallium atoms on the surface of the nitride semiconductor layer.
 他の形態に係る窒化物半導体発光素子であって、アルミニウム部分は、アルミニウムのみからなっていてもよい。 In the nitride semiconductor light emitting device according to another embodiment, the aluminum portion may be made of only aluminum.
 他の形態に係る窒化物半導体発光素子であって、アルミニウム部分は、n型窒化物半導体層と平行な層状を有していてもよい。 In the nitride semiconductor light emitting device according to another embodiment, the aluminum portion may have a layer shape parallel to the n-type nitride semiconductor layer.
 他の形態に係る窒化物半導体発光素子には、複数のアルミニウム部分が設けられていてもよい。 The nitride semiconductor light emitting device according to another embodiment may be provided with a plurality of aluminum portions.
 他の形態に係る窒化物半導体発光素子であって、アルミニウム部分と接しているn型窒化物半導体層の表面は、ガリウムの空孔を有していてもよい。 In the nitride semiconductor light emitting device according to another embodiment, the surface of the n-type nitride semiconductor layer in contact with the aluminum portion may have gallium vacancies.
 他の形態に係る窒化物半導体発光素子であって、アルミニウム部分と接しているn型窒化物半導体層の表面領域は、10nm以上且つ150nm以下の厚さを有していてもよい。 In the nitride semiconductor light emitting device according to another embodiment, the surface region of the n-type nitride semiconductor layer in contact with the aluminum portion may have a thickness of 10 nm or more and 150 nm or less.
 他の形態に係る窒化物半導体発光素子であって、n型窒化物半導体層は、m面の表面を有していてもよい。 In the nitride semiconductor light emitting device according to another embodiment, the n-type nitride semiconductor layer may have an m-plane surface.
 他の形態に係る窒化物半導体発光素子であって、アルミニウム部分と接しているn型窒化物半導体層の表面は、アルミニウム部分と接していないn型窒化物半導体層の部分よりも低いキャリア密度を有していてもよい。 In another aspect of the nitride semiconductor light emitting device, the surface of the n-type nitride semiconductor layer in contact with the aluminum portion has a lower carrier density than the portion of the n-type nitride semiconductor layer not in contact with the aluminum portion. You may have.
 また、本開示の他の形態は、窒化物半導体積層構造を製造する方法であって、以下の工程を具備する:(a)非極性面又は半極性面の表面を有するn型窒化物半導体層の表面を酸素プラズマで照射する工程、(b)工程(a)において酸素プラズマで照射された表面を酸に接触させる工程、及び(c)工程(b)において酸に接触された表面に、アルミニウム部分を形成する工程。 Another embodiment of the present disclosure is a method for manufacturing a nitride semiconductor multilayer structure, which includes the following steps: (a) an n-type nitride semiconductor layer having a nonpolar or semipolar surface. Irradiating the surface of the substrate with oxygen plasma, (b) contacting the surface irradiated with the oxygen plasma in step (a) with acid, and (c) contacting the surface with the acid in step (b) with aluminum. Forming a portion;
 他の形態に係る方法であって、アルミニウム部分は、アルミニウムのみからなっていてもよい。 The method according to another embodiment, wherein the aluminum portion may be made of only aluminum.
 他の形態に係る方法であって、アルミニウム部分は、n型窒化物半導体層と平行な層状を有していてもよい。 In another method, the aluminum portion may have a layer shape parallel to the n-type nitride semiconductor layer.
 他の形態に係る方法には、複数のアルミニウム部分が設けられていてもよい。 In the method according to another embodiment, a plurality of aluminum portions may be provided.
 他の形態に係る方法であって、アルミニウム部分と接しているn型窒化物半導体層の表面は、ガリウムの空孔を有していてもよい。 In another method, the surface of the n-type nitride semiconductor layer in contact with the aluminum portion may have gallium vacancies.
 他の形態に係る方法であって、アルミニウム部分と接しているn型窒化物半導体層の表面領域は、10nm以上且つ150nm以下の厚さを有していてもよい。 In another method, the surface region of the n-type nitride semiconductor layer in contact with the aluminum portion may have a thickness of 10 nm or more and 150 nm or less.
 他の形態に係る方法であって、n型窒化物半導体層は、m面の表面を有していてもよい。 In another method, the n-type nitride semiconductor layer may have an m-plane surface.
 なお、本明細書においては、m面を主面とするn型GaN層を有する窒化物半導体積層構造を例に挙げて議論する。但し、m面を主面とする他のn型窒化物半導体層を有する窒化物半導体積層構造についても同様のことがいえる。また、-r面、r面、(20-21)面、(20-2-1)面、(10-1-3)面及び(11-22)面等の半極性面、又はa面等の非極性面を主面とするn型GaN層又は他のn型窒化物半導体層を有する窒化物半導体積層構造についても同様のことがいえる。 In this specification, a nitride semiconductor multilayer structure having an n-type GaN layer having an m-plane as a main surface will be described as an example. However, the same can be said for a nitride semiconductor multilayer structure having another n-type nitride semiconductor layer having an m-plane as a main surface. Also, semipolar planes such as -r plane, r plane, (20-21) plane, (20-2-1) plane, (10-1-3) plane and (11-22) plane, or a plane, etc. The same can be said for a nitride semiconductor multilayer structure having an n-type GaN layer or other n-type nitride semiconductor layer whose main surface is a non-polar surface.
 ところで、m面GaN系半導体素子は、c面GaN系半導体素子と比較して顕著な効果を発揮し得るが、m面GaNに対するn側オーミック電極の形成技術は、未だ完成されていない。 By the way, although the m-plane GaN-based semiconductor element can exhibit a remarkable effect as compared with the c-plane GaN-based semiconductor element, the technology for forming the n-side ohmic electrode for the m-plane GaN has not yet been completed.
 例えば、特許文献1には、m面GaNに対するn側オーミック電極の形成はc面GaNに対するn側オーミック電極の形成と比べて困難であることが記載されている。その解決策として、m面GaNの主面に対して、例えばストライプ状にエッチングを行って該ストライプ状の側壁にc面GaNを意図的に露出させ、その露出した部分にc面GaNに有効とされるTi/Alからなる電極を形成し、その後、500℃程度の温度でシンター処理を行うという手法が記載されている。 For example, Patent Document 1 describes that formation of an n-side ohmic electrode for m-plane GaN is more difficult than formation of an n-side ohmic electrode for c-plane GaN. As a solution to this, the main surface of the m-plane GaN is etched, for example, in a stripe shape to intentionally expose the c-plane GaN on the stripe-shaped sidewall, and the exposed portion is effective for the c-plane GaN. A technique is described in which an electrode made of Ti / Al is formed, and thereafter, sintering is performed at a temperature of about 500 ° C.
 すなわち、特許文献1に記載の手法は、m面GaNに対する直接的なn側オーミック電極の形成技術ではない。この手法では、m面GaNに対してエッチングを行うので、素子の製造時のプロセスフローに制約が生じる。また、オーミック特性を得るために、500℃程度の温度のシンター処理を行うので、さらに製造プロセスに制約が生じる。 That is, the technique described in Patent Document 1 is not a direct n-side ohmic electrode formation technique for m-plane GaN. In this method, since the etching is performed on the m-plane GaN, the process flow at the time of manufacturing the device is limited. In addition, since a sintering process at a temperature of about 500 ° C. is performed in order to obtain ohmic characteristics, the manufacturing process is further restricted.
 そこで、本発明者らは、m面GaN等の非極性面又は半極性面である表面を有する窒化物半導体層に対するn側オーミック電極の形成技術を新たに開発するために鋭意検討した結果、コンタクト抵抗が極めて低いn側オーミック電極を形成できる手法を見出した。 Therefore, the present inventors have intensively studied to newly develop a technique for forming an n-side ohmic electrode for a nitride semiconductor layer having a nonpolar or semipolar surface such as m-plane GaN. The present inventors have found a method capable of forming an n-side ohmic electrode with extremely low resistance.
 (一実施形態)
 以下、一実施形態に係る窒化物半導体積層構造、それを用いた窒化物半導体発光素子及びそれを用いた光源装置について図面を参照しながら説明する。以下の図面においては、説明の簡潔化のため、実質的に同一の機能を有する構成要素を同一の参照符号で示す。なお、本開示は、以下の実施形態に限定されない。
(One embodiment)
Hereinafter, a nitride semiconductor multilayer structure according to an embodiment, a nitride semiconductor light-emitting element using the same, and a light source device using the same will be described with reference to the drawings. In the following drawings, components having substantially the same function are denoted by the same reference numerals for the sake of brevity. Note that the present disclosure is not limited to the following embodiments.
 図3(a)は本実施形態に係る窒化物半導体発光素子の断面構成を模式的に示している。図3(a)に示した窒化物半導体発光素子100は、GaN系半導体から形成される半導体デバイスであり、n型窒化物半導体層22と窒化物半導体から形成される活性層24とp型窒化物半導体層26とを含む半導体積層構造20を有している。 FIG. 3A schematically shows a cross-sectional configuration of the nitride semiconductor light emitting device according to this embodiment. A nitride semiconductor light emitting device 100 shown in FIG. 3A is a semiconductor device formed of a GaN-based semiconductor, and includes an n-type nitride semiconductor layer 22, an active layer 24 formed of a nitride semiconductor, and p-type nitride. The semiconductor multilayer structure 20 includes a physical semiconductor layer 26.
 具体的には、本実施形態に係る窒化物半導体発光素子100は、m面を主面10aとするGaN系基板10と、該GaN系基板10の主面10a上に形成された半導体積層構造20と、該半導体積層構造20におけるp型窒化物半導体層26の上に接して形成されたp側電極30と、露出されたn型窒化物半導体層22に接して形成されたn側電極40とを備えている。 Specifically, the nitride semiconductor light emitting device 100 according to this embodiment includes a GaN-based substrate 10 having an m-plane as a main surface 10a, and a semiconductor multilayer structure 20 formed on the main surface 10a of the GaN-based substrate 10. A p-side electrode 30 formed on the p-type nitride semiconductor layer 26 in the semiconductor multilayer structure 20, and an n-side electrode 40 formed on the exposed n-type nitride semiconductor layer 22. It has.
 p型窒化物半導体層26は、例えば、AlGaN(但し、d+e=1、0≦d、0<e)層である。表面改質層23は、コンタクト層であってもよい。GaN系基板10は、例えば、GaN基板である。n側電極40は、金属部であってもよい。n側電極40は、半導体積層構造20をエッチングした凹部42から露出するn型窒化物半導体層22の露出面に設けられた表面改質層23の上に形成されている。n型窒化物半導体層22は、例えば、AlGaInN(但し、U+V+W=1、0≦U、0≦W、0<Vである。)層である。 The p-type nitride semiconductor layer 26 is, for example, an Al d Ga e N (where d + e = 1, 0 ≦ d, 0 <e) layer. The surface modification layer 23 may be a contact layer. The GaN-based substrate 10 is, for example, a GaN substrate. The n-side electrode 40 may be a metal part. The n-side electrode 40 is formed on the surface modification layer 23 provided on the exposed surface of the n-type nitride semiconductor layer 22 exposed from the recess 42 obtained by etching the semiconductor multilayer structure 20. The n-type nitride semiconductor layer 22 is, for example, an Al u Ga v In w N (where U + V + W = 1, 0 ≦ U, 0 ≦ W, 0 <V) layer.
 本実施形態においては、半導体積層構造20は、m面成長によって形成されたm面半導体積層構造であり、その主面はm面である。なお、r面サファイア基板上には、a面GaNが成長するという事例もあり、成長条件によっては必ずしもGaN系基板10の主面がm面であることが必須ではない。n側電極40と接触するn型窒化物半導体層22の凹部42は、m面である表面を有する。 In this embodiment, the semiconductor multilayer structure 20 is an m-plane semiconductor multilayer structure formed by m-plane growth, and its main surface is an m-plane. There are cases where a-plane GaN grows on the r-plane sapphire substrate, and depending on the growth conditions, it is not always necessary that the main surface of the GaN-based substrate 10 is the m-plane. Recess 42 of n-type nitride semiconductor layer 22 in contact with n-side electrode 40 has a surface that is an m-plane.
 なお、本実施形態に係る窒化物半導体発光素子100は、半導体積層構造20を保持するGaN系基板10を備えているが、GaN系基板10の代わりに他の保持基板を備えていてもよい。また、保持基板が取り除かれた状態であってもよい。 The nitride semiconductor light emitting device 100 according to this embodiment includes the GaN-based substrate 10 that holds the semiconductor multilayer structure 20, but may include another holding substrate instead of the GaN-based substrate 10. Further, the holding substrate may be removed.
 図3(b)は、主面がm面である窒化物半導体の断面(基板の表面に垂直な方向の断面)における結晶構造を模式的に示している。Ga原子とN原子とは、m面に平行な同一原子面上に位置するため、m面に垂直な方向には、分極が発生しない。すなわち、m面は非極性面であり、m面に垂直な方向に成長した活性層内ではピエゾ電界が発生しない。なお、添加されたIn及びAlは、Gaのサイトに位置し、Gaを置換する。Gaの少なくとも一部がIn又はAlで置換されていても、m面に垂直な方向に分極は発生しない。 FIG. 3B schematically shows a crystal structure in a nitride semiconductor cross section (a cross section in a direction perpendicular to the surface of the substrate) of the nitride semiconductor whose main surface is the m-plane. Since Ga atoms and N atoms are located on the same atomic plane parallel to the m-plane, no polarization occurs in the direction perpendicular to the m-plane. That is, the m-plane is a nonpolar plane, and no piezo electric field is generated in the active layer grown in the direction perpendicular to the m-plane. The added In and Al are located at the Ga site and replace Ga. Even if at least part of Ga is substituted with In or Al, no polarization occurs in the direction perpendicular to the m-plane.
 m面を主面とするGaN系基板は、本明細書では「m面GaN系基板」とも称する。m面に垂直な方向に成長したm面窒化物半導体積層構造を得るには、典型的には、m面GaN基板を用い、該m面GaN基板のm面上に窒化物半導体を成長させればよい。m面GaN系基板の主面の面方位が、半導体積構造体の面方位に反映されるからである。しかし、前述したように、基板の主面がm面である必要は必ずしもなく、また、最終的なデバイスから基板が除去されていてもよい。 A GaN-based substrate having an m-plane as a main surface is also referred to as an “m-plane GaN-based substrate” in this specification. To obtain an m-plane nitride semiconductor stacked structure grown in a direction perpendicular to the m-plane, typically, an m-plane GaN substrate is used, and a nitride semiconductor can be grown on the m-plane of the m-plane GaN substrate. That's fine. This is because the plane orientation of the main surface of the m-plane GaN-based substrate is reflected in the plane orientation of the semiconductor product structure. However, as described above, the main surface of the substrate is not necessarily the m-plane, and the substrate may be removed from the final device.
 参考のために、図3(c)に、主面がc面である窒化物半導体の断面(基板の表面に垂直な方向の断面)における結晶構造を模式的に示す。Ga原子とN原子とは、c面に平行な同一原子面上に存在しない。その結果、c面に垂直な方向に分極が発生する。c面を主面とするGaN系基板を、本明細書では「c面GaN系基板」とも称する。 For reference, FIG. 3C schematically shows a crystal structure of a nitride semiconductor cross section (cross section in a direction perpendicular to the surface of the substrate) of the nitride semiconductor whose principal surface is the c plane. Ga atoms and N atoms do not exist on the same atomic plane parallel to the c-plane. As a result, polarization occurs in a direction perpendicular to the c-plane. A GaN-based substrate having a c-plane as a main surface is also referred to as a “c-plane GaN-based substrate” in this specification.
 c面GaN系基板は、GaN系半導体結晶を成長させるための一般的な基板である。上述したように、c面に平行なGaの原子層とNの原子層との位置がc軸方向に僅かにずれているため、c軸方向に沿って分極が形成される。 The c-plane GaN-based substrate is a general substrate for growing GaN-based semiconductor crystals. As described above, since the positions of the Ga atomic layer and the N atomic layer parallel to the c-plane are slightly shifted in the c-axis direction, polarization is formed along the c-axis direction.
 再び、図3(a)を参照しながら、半導体積層構造20の詳細な構造を説明する。 Again, the detailed structure of the semiconductor stacked structure 20 will be described with reference to FIG.
 GaN系基板10の主面10aの上には、半導体積層構造20がエピタキシャル成長により形成されている。半導体積層構造20は、GaN系基板10の上に形成されたn型窒化物半導体層22と、n型窒化物半導体層22の上に形成されたAlInGaN層(a+b+c=1,a≧0,b≧0,c≧0)を含む活性層24と、活性層24の上に形成されたp型窒化物半導体層26とを含んでいる。ここで、活性層24は、窒化物半導体発光素子100における電子注入領域である。 On the main surface 10a of the GaN-based substrate 10, a semiconductor multilayer structure 20 is formed by epitaxial growth. The semiconductor stacked structure 20 includes an n-type nitride semiconductor layer 22 formed on the GaN-based substrate 10 and an Al a In b Ga c N layer (a + b + c = 1) formed on the n-type nitride semiconductor layer 22. , A ≧ 0, b ≧ 0, c ≧ 0), and a p-type nitride semiconductor layer 26 formed on the active layer 24. Here, the active layer 24 is an electron injection region in the nitride semiconductor light emitting device 100.
 活性層24とp型窒化物半導体層26との間には、アンドープのGaN層を設けてもよい。p型窒化物半導体層26の上部、すなわち半導体積層構造20の上面部分は、Alの組成dが0であるGaN層から構成されていてもよい。これにより、コンタクト抵抗を低減することができる。 An undoped GaN layer may be provided between the active layer 24 and the p-type nitride semiconductor layer 26. The upper portion of the p-type nitride semiconductor layer 26, that is, the upper surface portion of the semiconductor multilayer structure 20, may be composed of a GaN layer having an Al composition d of zero. Thereby, contact resistance can be reduced.
 p型窒化物半導体層26において、Alの組成dは、厚さ方向に一様である必要はない。また、p型窒化物半導体層26において、Alの組成dが厚さ方向に連続的又は階段的に変化していてもよい。すなわち、p型窒化物半導体層26は、Alの組成dが互いに異なる複数の層が積層された多層構造を有していてもよく、ドーパントの濃度も厚さ方向に変化していてもよい。 In the p-type nitride semiconductor layer 26, the Al composition d need not be uniform in the thickness direction. In the p-type nitride semiconductor layer 26, the Al composition d may change continuously or stepwise in the thickness direction. That is, the p-type nitride semiconductor layer 26 may have a multilayer structure in which a plurality of layers having different Al compositions d are stacked, and the dopant concentration may also change in the thickness direction.
 半導体積層構造20の上には、p側電極30が形成されている。本実施形態に係るp側電極30は、銀(Ag)から形成される電極である。本実施形態においては、p側電極30は、導電型がp型のドーパントがドープされたp型窒化物半導体層26と接触している。p型窒化物半導体層26には、例えば、ドーパントとしてマグネシウム(Mg)がドープされている。Mg以外のp型ドーパントとして、例えば亜鉛(Zn)又はベリリウム(Be)等がドープされていてもよい。 A p-side electrode 30 is formed on the semiconductor multilayer structure 20. The p-side electrode 30 according to the present embodiment is an electrode formed from silver (Ag). In the present embodiment, the p-side electrode 30 is in contact with the p-type nitride semiconductor layer 26 doped with a dopant whose conductivity type is p-type. The p-type nitride semiconductor layer 26 is doped with, for example, magnesium (Mg) as a dopant. As a p-type dopant other than Mg, for example, zinc (Zn) or beryllium (Be) may be doped.
 図3(a)に示すように、本実施形態に係る構成では、GaN系基板10の上に形成されたn型窒化物半導体層22の一部を露出する凹部42が形成されている。ここで、n型窒化物半導体層22の厚さは、例えば0.2μm以上且つ2μm以下である。凹部42から露出したn型窒化物半導体層22の露出面の一部には、表面改質層23が設けられている。この露出面は、m面である。n側電極40は、露出したn型窒化物半導体層22における表面改質層23の上に表面改質層23と接触して形成されている。 As shown in FIG. 3A, in the configuration according to this embodiment, a recess 42 exposing a part of the n-type nitride semiconductor layer 22 formed on the GaN-based substrate 10 is formed. Here, the thickness of the n-type nitride semiconductor layer 22 is not less than 0.2 μm and not more than 2 μm, for example. A surface modification layer 23 is provided on a part of the exposed surface of the n-type nitride semiconductor layer 22 exposed from the recess 42. This exposed surface is an m-plane. The n-side electrode 40 is formed on the surface modified layer 23 in the exposed n-type nitride semiconductor layer 22 in contact with the surface modified layer 23.
 n型窒化物半導体層22に設けた表面改質層23は、n型窒化物半導体層22に酸素(O)プラズマを照射することにより形成されている。例えば、反応性イオンエッチング(REACTIVEION ETCHING:RIE)型のOプラズマ装置(例えば、samco社製RIE-10NR)であれば、Oの圧力を10Paとし、ガスの流量を40ml/min(標準状態)とし、RFパワーを40Wとして、30秒間のOプラズマを照射することにより、好適な表面改質層23を形成することができる。 The surface modification layer 23 provided on the n-type nitride semiconductor layer 22 is formed by irradiating the n-type nitride semiconductor layer 22 with oxygen (O 2 ) plasma. For example, in the case of a reactive ion etching (RIE) type O 2 plasma apparatus (for example, RIE-10NR manufactured by samco), the pressure of O 2 is 10 Pa and the gas flow rate is 40 ml / min (standard state). ) And an RF power of 40 W, and irradiation with O 2 plasma for 30 seconds makes it possible to form a suitable surface modified layer 23.
 n型窒化物半導体層22とn側電極40とのコンタクト抵抗の低減を図るために、表面改質層23を形成した後、形成した表面改質層23の表面に対して酸処理を行ってもよい。酸処理には、例えばフッ酸又はバッファードフッ酸を用いることができる。フッ酸又はバッファードフッ酸を用いた場合の酸処理の時間は、例えば30秒間とすることができる。 In order to reduce the contact resistance between the n-type nitride semiconductor layer 22 and the n-side electrode 40, the surface modification layer 23 is formed, and then the surface of the formed surface modification layer 23 is subjected to acid treatment. Also good. For the acid treatment, for example, hydrofluoric acid or buffered hydrofluoric acid can be used. The acid treatment time when hydrofluoric acid or buffered hydrofluoric acid is used can be set to 30 seconds, for example.
 n側電極40は、例えば、単層のアルミニウム(Al)から構成され、その厚さは、例えば、5nm以上且つ1000nm以下とすることができる。単層のAlは、例えば真空蒸着法(抵抗加熱法又は電子ビーム法等)によって堆積することができる。 The n-side electrode 40 is made of, for example, a single layer of aluminum (Al), and the thickness thereof can be, for example, 5 nm or more and 1000 nm or less. A single layer of Al can be deposited by, for example, a vacuum deposition method (such as a resistance heating method or an electron beam method).
 コンタクト抵抗のさらなる低減のため、n側電極40を形成した後にシンター処理を行ってもよい。例えば、窒素(N)雰囲気中において、半導体発光素子100に対して300℃で10分間のシンター処理を行うことにより、n側電極40をより好適なn側オーミック電極とすることができる。シンター温度は、例えば、200℃以上且つ700℃以下の範囲で任意に選択することができる。シンター温度は、300℃以上且つ600℃以下であってもよい。このシンター温度領域において、コンタクト抵抗は最低値(固有コンタクト抵抗3×10-5Ωcm)を取る。シンター温度は、300℃以下又は500℃以下であってもよい。これにより、発光素子の作製プロセスが容易となり、また、熱の影響を受けやすいm面発光素子の信頼性を向上させることができる。さらに、シンター処理は行わなくてもよい。 In order to further reduce the contact resistance, sintering may be performed after the n-side electrode 40 is formed. For example, the n-side electrode 40 can be made a more suitable n-side ohmic electrode by performing a sintering process at 300 ° C. for 10 minutes in a nitrogen (N 2 ) atmosphere. The sintering temperature can be arbitrarily selected within a range of 200 ° C. or more and 700 ° C. or less, for example. The sintering temperature may be 300 ° C. or more and 600 ° C. or less. In this sintering temperature region, the contact resistance takes the lowest value (specific contact resistance 3 × 10 −5 Ωcm 2 ). The sintering temperature may be 300 ° C. or lower or 500 ° C. or lower. As a result, the manufacturing process of the light-emitting element is facilitated, and the reliability of the m-plane light-emitting element that is easily affected by heat can be improved. Further, the sintering process may not be performed.
 本実施形態に係るn側コンタクト抵抗の低減効果は、アルミニウム(Al)原子が表面改質層23と接触することによって得られる。従って、n側電極40は必ずしも単層又は単体のAlである必要はなく、Alを主成分とする金属層、すなわちAl合金であってもよい。Alの濃度は、例えば、50質量%以上である。また、Alが表面改質層23と接触する金属多層膜であってもよい。AlはTiと比べて反射率及び熱伝導率が高いので、Al電極を用いる場合は、Ti/Al電極を用いる場合と比べて、光吸収を低減し且つ放熱性を向上させることができる。これにより、光出力を向上させることができる。 The effect of reducing the n-side contact resistance according to the present embodiment is obtained when aluminum (Al) atoms come into contact with the surface modification layer 23. Therefore, the n-side electrode 40 does not necessarily need to be a single layer or a single Al, and may be a metal layer containing Al as a main component, that is, an Al alloy. The concentration of Al is, for example, 50% by mass or more. Alternatively, a metal multilayer film in which Al is in contact with the surface modification layer 23 may be used. Since Al has a higher reflectance and thermal conductivity than Ti, when an Al electrode is used, light absorption can be reduced and heat dissipation can be improved compared to the case where a Ti / Al electrode is used. Thereby, the light output can be improved.
 なお、n側電極40は、形成される時点でAl合金を形成しなくても、n側電極40を形成した後のシンター処理において、最終的にn側電極40がAl合金となり、Al原子が表面改質層23と接触している状態となっているのであれば、本実施形態の技術範囲に属する。 Even if the n-side electrode 40 does not form an Al alloy at the time of formation, the n-side electrode 40 finally becomes an Al alloy in the sintering process after the n-side electrode 40 is formed, and Al atoms If they are in contact with the surface modification layer 23, they belong to the technical scope of this embodiment.
 例えば、後述するように、n側電極40を、厚さが10nmのチタン(Ti)とその上に厚さが500nmのアルミニウム(Al)を積層したTi/Al膜から構成する場合には、シンター処理を行わなければ、表面改質層23とTiとが直接に接触し、表面改質層23とAlとが接触していないため、オーミック特性を示さない。しかし、500℃以上の高温下でシンター処理を行うことにより、AlがTiと混ざり合って合金化し、結果としてAl原子が表面改質層23と接触する状態となる。この場合には、コンタクト抵抗が低いn側オーミック電極を実現することができる。なお、p側電極30の上及びn側電極40の上には、金属又は合金からなる他の電極層又は他の配線層が形成されていてもよい。 For example, as will be described later, when the n-side electrode 40 is composed of a Ti / Al film in which titanium (Ti) having a thickness of 10 nm and aluminum (Al) having a thickness of 500 nm are stacked thereon, a sinter is used. Unless the treatment is performed, the surface modified layer 23 and Ti are in direct contact and the surface modified layer 23 and Al are not in contact with each other. However, by performing a sintering process at a high temperature of 500 ° C. or higher, Al is mixed with Ti and alloyed, and as a result, Al atoms come into contact with the surface modification layer 23. In this case, an n-side ohmic electrode having a low contact resistance can be realized. Note that another electrode layer or another wiring layer made of a metal or an alloy may be formed on the p-side electrode 30 and the n-side electrode 40.
 m面の主面10aを有するGaN系基板10の厚さは、例えば、100μm~400μmである。基板の厚さがおよそ100μm以上であれば、ウエハの取り扱いが容易となる。なお、本実施形態に係るGaN系基板10は、GaN系材料からなるm面の主面10aを有していれば、積層構造を採っても構わない。すなわち、本実施形態に係るGaN系基板10は、少なくとも最上面である主面10aがm面である基板を含む。従って、基板の全体がGaN系であってもよく、また、他の材料との組み合わせであってもよい。 The thickness of the GaN-based substrate 10 having the m-plane main surface 10a is, for example, 100 μm to 400 μm. If the thickness of the substrate is approximately 100 μm or more, handling of the wafer becomes easy. Note that the GaN-based substrate 10 according to the present embodiment may have a laminated structure as long as it has an m-plane main surface 10a made of a GaN-based material. That is, the GaN-based substrate 10 according to this embodiment includes a substrate in which at least the main surface 10a that is the uppermost surface is an m-plane. Therefore, the entire substrate may be GaN-based or a combination with other materials.
 本実施形態に係る活性層24は、例えば、Ga0.9In0.1Nからなる井戸層と、GaNからなるバリア層とが交互に積層されたGaInN/GaNからなる多重量子井戸(MQW)構造を有している。ここで、井戸層及びバリア層の厚さは、それぞれが例えば9nmであり、活性層24の厚さは、例えば81nmである。 The active layer 24 according to the present embodiment is, for example, a multiple quantum well (MQW) made of GaInN / GaN in which well layers made of Ga 0.9 In 0.1 N and barrier layers made of GaN are alternately stacked. It has a structure. Here, the thicknesses of the well layer and the barrier layer are each 9 nm, for example, and the thickness of the active layer 24 is 81 nm, for example.
 活性層24の上には、p型窒化物半導体層26が形成されている。p型窒化物半導体層26の厚さは、例えば0.2μm以上且つ2μm以下である。なお、上述したように、活性層24とp型窒化物半導体層26との間には、アンドープのGaN層を設けてもよい。 A p-type nitride semiconductor layer 26 is formed on the active layer 24. The thickness of the p-type nitride semiconductor layer 26 is, for example, not less than 0.2 μm and not more than 2 μm. As described above, an undoped GaN layer may be provided between the active layer 24 and the p-type nitride semiconductor layer 26.
 また、p型窒化物半導体層26の上に、例えば、p型のGaN層を形成することも可能である。p型のGaN層の上に、p-GaNからなるコンタクト層を形成し、該コンタクト層の上に、p側電極30を形成することも可能である。なお、GaNからなるコンタクト層を、p型窒化物半導体層26とは別の半導体層であるとする代わりに、p型窒化物半導体層26の一部であると考えてもよい。 Further, for example, a p-type GaN layer can be formed on the p-type nitride semiconductor layer 26. A contact layer made of p + -GaN may be formed on the p-type GaN layer, and the p-side electrode 30 may be formed on the contact layer. Note that the contact layer made of GaN may be considered as a part of the p-type nitride semiconductor layer 26 instead of being a semiconductor layer different from the p-type nitride semiconductor layer 26.
 本実施形態に係る窒化物半導体発光素子100は、このままの状態で光源装置として用いてもよい。しかし、波長変換のための蛍光物質を分散した樹脂材等と組み合わせれば、波長帯域が拡大した光源装置、例えば白色光源装置として使用され得る。 The nitride semiconductor light emitting device 100 according to this embodiment may be used as a light source device in this state. However, when combined with a resin material or the like in which a fluorescent material for wavelength conversion is dispersed, it can be used as a light source device with an expanded wavelength band, such as a white light source device.
 図4は光源装置の一例の断面構成を模式的に示している。図4に示す光源装置は、図3(a)に示す本実施形態に係る窒化物半導体発光素子100と、該窒化物半導体発光素子100から放射された光の波長を、より長い波長に変換する蛍光体(例えば、YAG:YttriumAlumninum Garnet)が分散された樹脂層200とを備えている。窒化物半導体発光素子100は、表面に配線パターン210が形成された保持部材220の上に固着されている。また、保持部材220の上には、窒化物半導体発光素子100を囲むように反射部材240が配置され固着されている。樹脂層200は、反射部材240の内側に、窒化物半導体発光素子100を覆うように形成されている。 FIG. 4 schematically shows a cross-sectional configuration of an example of the light source device. The light source device shown in FIG. 4 converts the nitride semiconductor light emitting device 100 according to this embodiment shown in FIG. 3A and the wavelength of light emitted from the nitride semiconductor light emitting device 100 into a longer wavelength. And a resin layer 200 in which a phosphor (for example, YAG: Yttrium Aluminum Garnet) is dispersed. The nitride semiconductor light emitting device 100 is fixed on a holding member 220 having a wiring pattern 210 formed on the surface thereof. On the holding member 220, a reflecting member 240 is disposed and fixed so as to surround the nitride semiconductor light emitting element 100. The resin layer 200 is formed inside the reflecting member 240 so as to cover the nitride semiconductor light emitting element 100.
 以上、実施形態の一例である窒化物半導体発光素子100として、LED素子について述べてきたが、n側電極40におけるコンタクト抵抗の低減効果は、LED素子以外の発光素子、例えば半導体レーザ素子においても得ることができる。また、この効果は、発光素子に限られず、例えばトランジスタ又は受光素子等のデバイスにおいても、当然に得ることができる。 As described above, the LED element has been described as the nitride semiconductor light emitting element 100 as an example of the embodiment, but the effect of reducing the contact resistance in the n-side electrode 40 is also obtained in a light emitting element other than the LED element, for example, a semiconductor laser element. be able to. Further, this effect is not limited to the light emitting element, and can naturally be obtained in a device such as a transistor or a light receiving element.
 ところで、m面半導体の主面又は表面は、m面に対して完全に平行な面である必要はなく、m面から所定の角度で傾斜していてもよい。傾斜角度は、窒化物半導体層における主面の法線と傾斜していないm面の法線とが形成する角度により決定される。m面窒化物半導体層における主面又は表面は、傾斜していないm面から、c軸方向及びa軸方向によって表されるベクトルの方向に向かって傾斜することができる。傾斜角度θの絶対値は、c軸方向において5°以下であってもよく、1°以下であってもよい。また、a軸方向において5°以下であってもよく、1°以下であってもよい。すなわち、本発明においては、「m面」は、±5°の範囲内で、傾斜していないm面から所定の方向に傾斜している面を含む。このような傾斜角度の範囲内であれば、窒化物半導体層の主面又は表面は全体的にm面から傾斜しているが、微視的には多数のm面領域が露出していると考えられる。これにより、m面から絶対値で5°以下の角度で傾斜している面は、m面と同様の性質を有すると考えられる。 Incidentally, the main surface or surface of the m-plane semiconductor does not have to be a plane that is completely parallel to the m-plane, and may be inclined at a predetermined angle from the m-plane. The tilt angle is determined by the angle formed by the normal of the main surface in the nitride semiconductor layer and the normal of the non-tilted m-plane. The main surface or surface of the m-plane nitride semiconductor layer can be inclined from the non-inclined m-plane toward the vector direction represented by the c-axis direction and the a-axis direction. The absolute value of the inclination angle θ may be 5 ° or less or 1 ° or less in the c-axis direction. Further, it may be 5 ° or less or 1 ° or less in the a-axis direction. That is, in the present invention, the “m-plane” includes a plane inclined in a predetermined direction from the non-inclined m-plane within a range of ± 5 °. Within such a tilt angle range, the main surface or surface of the nitride semiconductor layer is entirely tilted from the m-plane, but a large number of m-plane regions are exposed microscopically. Conceivable. Thereby, it is considered that the surface inclined at an angle of 5 ° or less from the m-plane has the same properties as the m-plane.
 また、-r面、r面、(20-21)面、(20-2-1)面、(10-1-3)面及び(11-22)面等の半極性面、並びにa面についても同様のことがいえる。従って、本発明においては、「-r面」、「r面」「(20-21)面」、「(20-2-1)面」、「(10-1-3)面」及び「(11-22)面」、並びに「a面」は、傾斜していないこれらの面から±5°の範囲内で所定の方向に傾斜している面を含む。 In addition, about the -r plane, the r plane, the (20-21) plane, the (20-2-1) plane, the (10-1-3) plane and the (11-22) plane, and the a-plane The same can be said for. Accordingly, in the present invention, the “−r plane”, “r plane”, “(20-21) plane”, “(20-2-1) plane”, “(10-1-3) plane” and “( The “11-22) plane” and the “a plane” include a plane inclined in a predetermined direction within a range of ± 5 ° from these non-inclined planes.
 次に、本実施形態に係る窒化物半導体積層構造について、本開示に至った経緯をも含めて、さらに詳細に説明する。 Next, the nitride semiconductor multilayer structure according to this embodiment will be described in more detail, including the background to the present disclosure.
 非特許文献1には、GaN(従来のGaNであるため、c面GaNを指すと考えられる。)に対するn側電極の材料として、アルミニウム(Al)を適用できると記載されている。また、GaNに対するn側電極の材料として、Alを適用できることは特許文献2にも記載されている。 Non-Patent Document 1 describes that aluminum (Al) can be applied as a material of an n-side electrode for GaN (considering c-plane GaN because it is conventional GaN). Patent Document 2 also describes that Al can be applied as a material for the n-side electrode for GaN.
 そこで、本発明者らは、まず、基礎検討実験として、m面GaNに対するn側電極材料として、アルミニウム(Al)を適用して、その電気特性を評価した。Alの膜厚は500nmとし、シンター処理を行う場合は窒素雰囲気中で行い、シンター処理時間は10分間とした。 Therefore, the present inventors first applied aluminum (Al) as an n-side electrode material for m-plane GaN as a basic study experiment, and evaluated its electrical characteristics. The film thickness of Al was 500 nm. When the sintering process was performed, it was performed in a nitrogen atmosphere, and the sintering process time was 10 minutes.
 図5(a)及び図5(b)に、m面GaNに設けるn側電極の電極材料としてAlを用いて、20mAの電流を印加した場合の電気特性の結果を示す。図5(c)には、電気特性の評価手法の概略構成を示している。図5(c)に示すように、m面GaN層50の主面上には、厚さが500nmで、縦が200μm、横が100μmの平面長方形状の2つのn側電極51を互いに20μmだけ離して形成している。電流源53と接続されたプローブ針55をn側電極51にそれぞれ接触させ、電流源53と並列接続された電圧計54を用いて、n側電極51の電流-電圧特性を評価した。図5(a)はn側電極51同士の間に20mAの電流を印加したときのn側電極51間の電圧とシンター温度との関係を表している。図5(b)はn側電極51間の電流-電圧特性をシンター温度ごとに表している。なお、今回の評価で使用した評価装置の測定限界電圧は10Vであるため、10Vを越えるデータは参考値である。本明細書においては、特に断わらない限り、n側電極の電気特性の評価は上述の方法により行っている。 5 (a) and 5 (b) show the results of electrical characteristics when a current of 20 mA is applied using Al as the electrode material of the n-side electrode provided on the m-plane GaN. FIG. 5C shows a schematic configuration of an electrical property evaluation method. As shown in FIG. 5C, on the main surface of the m-plane GaN layer 50, two n-side electrodes 51 each having a planar rectangular shape with a thickness of 500 nm, a length of 200 μm, and a width of 100 μm are only 20 μm from each other. Formed apart. The probe needle 55 connected to the current source 53 was brought into contact with the n-side electrode 51, and the current-voltage characteristics of the n-side electrode 51 were evaluated using a voltmeter 54 connected in parallel with the current source 53. FIG. 5A shows the relationship between the voltage between the n-side electrodes 51 and the sintering temperature when a current of 20 mA is applied between the n-side electrodes 51. FIG. 5B shows current-voltage characteristics between the n-side electrodes 51 for each sintering temperature. Since the measurement limit voltage of the evaluation apparatus used in this evaluation is 10V, data exceeding 10V is a reference value. In this specification, unless otherwise specified, the electrical characteristics of the n-side electrode are evaluated by the method described above.
 図5(a)及び図5(b)から明らかなように、特別な処理を施すことなく、m面GaNの表面にn側電極材料としてアルミニウム(Al)を用いた場合は、オーミック特性が得られないことが判明した。シンター処理も試みたが、特性は悪化し、オーミック特性化する兆候は全く見られなかった。このように、m面GaNに対しては、c面GaNに使用されるAlをn側電極材料としてそのまま適用しても、オーミック電極は形成できないことが明らかとなった。 As is clear from FIGS. 5A and 5B, ohmic characteristics can be obtained when aluminum (Al) is used as the n-side electrode material on the surface of m-plane GaN without any special treatment. It turned out not to be. Sintering was also attempted, but the properties deteriorated and there was no sign of ohmic properties. Thus, it has been clarified that an ohmic electrode cannot be formed for m-plane GaN even if Al used for c-plane GaN is directly applied as an n-side electrode material.
 そこで、オーミック特性を得るために、n側電極材料をアルミニウム(Al)から他の金属へ変更することが考えられる。例えば、c面GaNに設けるn側電極材料であるチタン(Ti)/アルミニウム(Al)(特許文献2を参照。)をm面GaNに用いることが考えられる。本発明者らは、c面GaNに設けるn側電極材料として、Ti/Alをm面GaNにそのまま適用して電気特性を評価した。m面GaNの主面上に、Ti膜及びAl膜を順次堆積した。ここで、Ti膜の膜厚は10nmとし、Al膜の膜厚は500nmとした。シンター処理をする場合は、窒素雰囲気中で行い、シンター処理時間は10分間とした。 Therefore, in order to obtain ohmic characteristics, it is conceivable to change the n-side electrode material from aluminum (Al) to another metal. For example, it is conceivable to use titanium (Ti) / aluminum (Al) (see Patent Document 2), which is an n-side electrode material provided on c-plane GaN, for m-plane GaN. The present inventors applied Ti / Al as it is to m-plane GaN as an n-side electrode material provided on c-plane GaN, and evaluated the electrical characteristics. A Ti film and an Al film were sequentially deposited on the main surface of the m-plane GaN. Here, the thickness of the Ti film was 10 nm, and the thickness of the Al film was 500 nm. When the sintering process was performed, it was performed in a nitrogen atmosphere, and the sintering process time was 10 minutes.
 図6(a)及び図6(b)に、m面GaNにTi/Alを適用したn側電極に、20mAの電流を印加した場合の電気特性の結果を示す。ここで、Ti膜の膜厚は10nmであり、Al膜の膜厚は500nmである。シンター処理を500℃~600℃という高温領域で行うことにより、ある程度のn側オーミック電極を形成することはできた。しかし、さらなるコンタクト抵抗の低減が求められる。すなわち、m面GaNを発光デバイスとして用いる最大のメリットの1つは、大電流密度領域においてピエゾ電界に起因する出力低下が抑制されることである。このため、c面GaNでは使用されない大電流密度領域で動作させることを考慮すると、さらなるコンタクト抵抗の低減が重要となる。 6 (a) and 6 (b) show the results of electrical characteristics when a current of 20 mA is applied to an n-side electrode in which Ti / Al is applied to m-plane GaN. Here, the thickness of the Ti film is 10 nm, and the thickness of the Al film is 500 nm. A certain amount of n-side ohmic electrode could be formed by performing the sintering process in a high temperature region of 500 ° C. to 600 ° C. However, further reduction of contact resistance is required. That is, one of the greatest merits of using m-plane GaN as a light-emitting device is that a decrease in output due to a piezoelectric field is suppressed in a large current density region. For this reason, in consideration of operating in a large current density region not used in c-plane GaN, it is important to further reduce contact resistance.
 ここで、本実施形態の、m面GaNに対してコンタクト抵抗を低減したn側オーミック電極を形成するための構成及びその製造方法について、図7(a)及び図7(b)を参照しながら説明する。 Here, referring to FIGS. 7A and 7B, a configuration and a manufacturing method thereof for forming an n-side ohmic electrode with reduced contact resistance with respect to m-plane GaN according to the present embodiment. explain.
 まず、図7(a)に示すように、m面GaN層50に対してOプラズマを選択的に照射して、m面GaN層50の上部に表面改質層52を形成する。例えば、RIE型のOプラズマ装置(例えば、samco社製RIE-10NR)であれば、Oの圧力を10Paとし、ガスの流量を40ml/min(標準状態)とし、RFパワーを40Wとして、30秒間のOプラズマを照射することにより、好適な表面改質層52を形成することができる。本実施形態においては、Oプラズマをm面GaN層50の全面に照射するのではなく、n側電極の形成領域にのみ照射している。具体的には、レジスト膜によって、n側電極の形成領域を除く部分を覆っている。なお、これに代えて、m面GaN層50の表面全体にOプラズマを照射してもよい。 First, as shown in FIG. 7A, the m-plane GaN layer 50 is selectively irradiated with O 2 plasma to form a surface modification layer 52 on the m-plane GaN layer 50. For example, in the case of an RIE type O 2 plasma apparatus (for example, RIE-10NR manufactured by samco), the pressure of O 2 is 10 Pa, the gas flow rate is 40 ml / min (standard state), and the RF power is 40 W. A suitable surface modification layer 52 can be formed by irradiating O 2 plasma for 30 seconds. In the present embodiment, the entire surface of the m-plane GaN layer 50 is not irradiated with O 2 plasma, but only the n-side electrode formation region is irradiated. Specifically, the resist film covers a portion excluding the n-side electrode formation region. Instead of this, the entire surface of the m-plane GaN layer 50 may be irradiated with O 2 plasma.
 続いて、表面改質層52の表面に酸処理を施す。例えば、酸処理には、フッ酸又はバッファードフッ酸を用いることができる。フッ酸又はバッファードフッ酸を用いた場合の酸処理時間は、例えば30秒間とすることができる。 Subsequently, the surface of the surface modification layer 52 is subjected to an acid treatment. For example, hydrofluoric acid or buffered hydrofluoric acid can be used for the acid treatment. The acid treatment time when using hydrofluoric acid or buffered hydrofluoric acid can be set to 30 seconds, for example.
 次に、図7(b)に示すように、表面改質層52の上に電極材料としてAlを堆積する。例えば、Al膜は、真空蒸着法(抵抗加熱法又は電子ビーム法等)によって堆積することができる。これにより、表面改質層52とAl原子とが接触する状態となる。電極材料としては、必ずしもAl単体である必要はなく、Alを主成分とする金属層、すなわちAl合金であってもよい。 Next, as shown in FIG. 7B, Al is deposited on the surface modification layer 52 as an electrode material. For example, the Al film can be deposited by a vacuum evaporation method (such as a resistance heating method or an electron beam method). Thereby, it will be in the state which the surface modification layer 52 and Al atom contact. The electrode material is not necessarily made of Al alone, but may be a metal layer containing Al as a main component, that is, an Al alloy.
 図8(a)及び図8(b)に、本実施形態に係る「Oプラズマ照射+フッ酸処理+Al」により形成されたn側電極の、20mAの電流印加時のn電気特性を示している。Al膜の膜厚は、500nmとしている。図8(a)及び図8(b)から分かるように、シンター処理を行わなくても、m面GaNに対して良好なn側オーミック電極が形成されている。また、窒素雰囲気中の200℃以上且つ700℃以下の温度で10分間のシンター処理を行うことにより、さらにコンタクト抵抗は低減している。シンター温度は、300℃以上且つ600℃以下であってもよい。このシンター温度領域においてコンタクト抵抗は最低値(固有コンタクト抵抗3×10-5Ωcm)を示した。なお、固有コンタクト抵抗の値は、伝送路行列(TLM)法を用いて別途評価した。 FIGS. 8A and 8B show the n electrical characteristics of the n-side electrode formed by “O 2 plasma irradiation + hydrofluoric acid treatment + Al” according to this embodiment when a current of 20 mA is applied. Yes. The thickness of the Al film is 500 nm. As can be seen from FIGS. 8A and 8B, a good n-side ohmic electrode is formed on the m-plane GaN without performing the sintering process. Further, the contact resistance is further reduced by performing a sintering process for 10 minutes at a temperature of 200 ° C. or more and 700 ° C. or less in a nitrogen atmosphere. The sintering temperature may be 300 ° C. or more and 600 ° C. or less. In this sintering temperature region, the contact resistance showed the lowest value (specific contact resistance 3 × 10 −5 Ωcm 2 ). The value of the specific contact resistance was separately evaluated using a transmission line matrix (TLM) method.
 比較のため、図9に、本実施形態「Oプラズマ照射+フッ酸処理+Al」によるn側電極の電気特性(図8に相当)、Alを適用した場合のn側電極の電気特性(図5に相当)、及びTi/Alを適用した場合のn側電極の電気特性(図6に相当)の結果をそれぞれ示している。図9により、本実施形態に係るn側電極には、極めて大きな優位性があることは明らかである。 For comparison, FIG. 9 shows the electrical characteristics of the n-side electrode (corresponding to FIG. 8) according to this embodiment “O 2 plasma irradiation + hydrofluoric acid treatment + Al”, and the electrical characteristics of the n-side electrode when Al is applied (FIG. 9). 5), and the electrical characteristics of the n-side electrode when Ti / Al is applied (corresponding to FIG. 6). From FIG. 9, it is clear that the n-side electrode according to the present embodiment has a great advantage.
 本実施形態においては、n側電極用のAl膜に対するシンター処理を行わなくてもよい。また、シンター処理を通常と比べて低い温度、例えば300℃以下、又は500℃以下の温度で行っても、コンタクト抵抗が低いn側オーミック電極を形成することができる。これにより、デバイス製造のプロセスフローに係る設計の自由度が極めて大きくなる。また、本発明者らの検討によれば、c面GaNと比較して、m面GaNは熱の影響を受けやすい。このようなm面GaNに対してシンター処理を行わなくても、コンタクト抵抗が低いn側オーミック電極を形成できることの意義は極めて大きい。 In this embodiment, the sintering process for the Al film for the n-side electrode may not be performed. Even if the sintering process is performed at a temperature lower than usual, for example, 300 ° C. or lower, or 500 ° C. or lower, an n-side ohmic electrode having a low contact resistance can be formed. This greatly increases the degree of freedom of design related to the device manufacturing process flow. Also, according to the study by the present inventors, m-plane GaN is more susceptible to heat than c-plane GaN. It is very significant that an n-side ohmic electrode with low contact resistance can be formed without performing sintering on such m-plane GaN.
 図10は本実施形態に係る窒化物半導体発光素子、ここではLED素子の電流-電圧特性を示している。図10から分かるように、上述したn側電極を窒化物半導体発光素子に適用することにより、動作電圧の大幅な低減及び電気特性のばらつきの大幅な低減が実現されている。 FIG. 10 shows the current-voltage characteristics of the nitride semiconductor light emitting device according to this embodiment, here the LED device. As can be seen from FIG. 10, by applying the above-described n-side electrode to the nitride semiconductor light emitting device, a significant reduction in operating voltage and a significant variation in electrical characteristics are realized.
 このように、本実施形態に係るn側電極を実際にデバイスに適用することにより、そのデバイス特性を大幅に向上できることが実証された。 Thus, it was demonstrated that the device characteristics can be significantly improved by actually applying the n-side electrode according to the present embodiment to a device.
 次に、本実施形態に係るn側電極が当業者にとって容易に想到できないことを、以下に大きく2つに分けて説明する。 Next, the fact that the n-side electrode according to the present embodiment cannot be easily conceived by those skilled in the art will be described below in two broad categories.
 <第1の想到困難性>
 第1の想到困難性として、図5に示したように、m面GaNに設けるn側電極材料として、アルミニウム(Al)は全く適用できないとの実験結果及び心証を得ていたにも拘わらず、Oプラズマの照射により表面が改質したm面GaNに対しては、逆にAlにおいてのみ、顕著な効果を発現することを発見したということが挙げられる。
<First difficult difficulty>
As the first conceived difficulty, as shown in FIG. 5, as the n-side electrode material provided on the m-plane GaN, although the experimental results and evidence that aluminum (Al) cannot be applied at all have been obtained, For m-plane GaN whose surface has been modified by irradiation with O 2 plasma, conversely, it has been found that a remarkable effect is manifested only in Al.
 通常の技術者であれば、m面GaNに対してn側電極材料としてAlを検討し、これが適用できないという実験結果を得れば、その後の検討においては、m面GaNに対するn側電極材料としてAlを候補から外すのは当然と思われる。 If a normal engineer examines Al as an n-side electrode material for m-plane GaN and obtains an experimental result that this cannot be applied, in the subsequent examination, as an n-side electrode material for m-plane GaN, It seems natural to remove Al from the candidate.
 しかし、本発明者らは、あえて、n側電極材料としてAlを用い、Oプラズマの照射により表面を改質したm面GaNにAl原子が接触することによって、極めて低いコンタクト抵抗を得ることができた。  However, the present inventors dare to obtain extremely low contact resistance by using Al as the n-side electrode material and contacting Al atoms with m-plane GaN whose surface has been modified by O 2 plasma irradiation. did it.
 (比較実験1)
 比較実験1として、図11(a)及び図11(b)に、m面GaNに対してOプラズマの照射及びフッ酸処理を行ってその表面を改質した後に、c面GaNに設けるn側電極材料のTi/Alを堆積し、20mAの電流を印加した場合のn側電極の電気特性を示す。
(Comparative Experiment 1)
As a comparative experiment 1, in FIGS. 11 (a) and 11 (b), n-plane GaN is irradiated with O 2 plasma and hydrofluoric acid treatment to modify its surface, and then provided on the c-plane GaN. The electrical characteristics of the n-side electrode when a side electrode material of Ti / Al is deposited and a current of 20 mA is applied are shown.
 図11(a)及び図11(b)からは、シンター処理を行わない場合及び400℃程度までのシンター処理を行う場合においては、オーミック特性が全く得られておらず、たとえm面GaNに表面改質層を形成したとしても、表面改質層と接触する金属がチタン(Ti)では効果を得られないことが分かる。 From FIGS. 11A and 11B, no ohmic characteristics are obtained when the sintering process is not performed and when the sintering process is performed up to about 400 ° C. It can be seen that even if the modified layer is formed, an effect cannot be obtained if the metal in contact with the surface modified layer is titanium (Ti).
 温度が500℃以上且つ600℃以下の高温のシンター温度領域においては、Ti/Alの場合でも、アルミニウム(Al)と同様の効果を示しているかのように見える。しかし、これは高温のシンター処理によって、Ti/Alの金属同士の間での固相拡散又は合金化等が生じたことに起因する。その結果、Al原子がTi膜を突き破り、m面GaNの表面改質層とAl原子とが接触している状態となっている。このことは、次の検証結果により明らかである。 In the high-temperature sintering temperature region where the temperature is 500 ° C. or more and 600 ° C. or less, even in the case of Ti / Al, it looks as if it shows the same effect as aluminum (Al). However, this is due to solid phase diffusion or alloying between Ti / Al metals caused by high temperature sintering. As a result, Al atoms break through the Ti film, and the surface modification layer of m-plane GaN and Al atoms are in contact with each other. This is clear from the following verification result.
 図12(a)は、シンター処理の有無、及びシンター処理の温度を3通りに変えた試料に対して、m面GaN層50の裏面から光学顕微鏡観察を行った写真である。具体的には、図12(b)に示すように、m面GaN層50の主面に対してOプラズマの照射及びフッ酸処理を行って、その表面に表面改質層52を形成し、その後、Ti/Alからなるn側電極51を形成した。その後、シンター処理を行わない試料と、400℃、500℃及び600℃の各温度下でシンター処理をそれぞれ行った試料とにおいて、m面GaN層50の裏面から光学顕微鏡により観察を行った。ここで、Ti膜の膜厚は10nmとし、Al膜の膜厚は500nmとしている。 FIG. 12A is a photograph of an optical microscope observed from the back surface of the m-plane GaN layer 50 with respect to a sample in which the presence or absence of sintering treatment and the temperature of sintering treatment were changed in three ways. Specifically, as shown in FIG. 12B, the main surface of the m-plane GaN layer 50 is irradiated with O 2 plasma and hydrofluoric acid to form a surface modification layer 52 on the surface. Thereafter, an n-side electrode 51 made of Ti / Al was formed. Thereafter, the sample not subjected to the sintering process and the sample subjected to the sintering process at temperatures of 400 ° C., 500 ° C., and 600 ° C. were observed with an optical microscope from the back surface of the m-plane GaN layer 50. Here, the thickness of the Ti film is 10 nm, and the thickness of the Al film is 500 nm.
 図12(a)に示すように、シンター処理を行わない試料は、Tiが表面改質層52と全面的に接触している。ところが、500℃以上の高温シンター処理を行うことにより、n側電極51を構成するAl原子が、固相拡散又は合金化等によってTi膜と混ざり合ってTi膜を突き破り、表面改質層52と接触する状態となっていることが明確に分かる。600℃のシンター処理を行った場合では、Al原子がTi膜のほぼ全面を突き破り、両原子が混ざり合って合金化し、m面GaN層50との界面のほぼ全面がAl原子と接触している状態となっていることが分かる。 As shown in FIG. 12A, in the sample not subjected to the sintering process, Ti is in contact with the surface modification layer 52 entirely. However, by performing a high-temperature sintering process at 500 ° C. or higher, Al atoms constituting the n-side electrode 51 are mixed with the Ti film by solid phase diffusion or alloying to break through the Ti film, It can be clearly seen that they are in contact. In the case where the sintering process is performed at 600 ° C., Al atoms break through almost the entire surface of the Ti film, both atoms are mixed and alloyed, and almost the entire surface of the interface with the m-plane GaN layer 50 is in contact with the Al atoms. It turns out that it is in a state.
 (比較実験2)
 比較実験2として、図13(a)及び図13(b)に、Oプラズマの照射及びフッ酸処理を行った後に、チタン(Ti)のみからなるn側電極を形成し、20mAの電流を印加した場合の電気特性を調べた結果を示す。シンター処理を行わない場合は、Ti/Alからなるn側電極におけるシンター処理を行わない試料の場合と同様に、GaNと接触する金属はTiであるため、その電気特性は、Ti/Alからなるn側電極の場合と全く同一であった。しかし、500℃以上の高温シンター処理を行った場合は、Ti/Alからなるn側電極の場合とは異なり、オーミック特性を全く示さず、高抵抗のままであった。
(Comparative experiment 2)
As Comparative Experiment 2, in FIG. 13 (a) and FIG. 13 (b), after performing O 2 plasma irradiation and hydrofluoric acid treatment, an n-side electrode made of only titanium (Ti) was formed, and a current of 20 mA was applied. The result of having investigated the electrical property at the time of applying is shown. When the sintering process is not performed, the metal in contact with GaN is Ti, as in the case of the sample not performing the sintering process on the n-side electrode made of Ti / Al, and thus its electrical characteristics are composed of Ti / Al. It was exactly the same as the case of the n-side electrode. However, when the high temperature sintering treatment at 500 ° C. or higher was performed, unlike the case of the n-side electrode made of Ti / Al, the ohmic characteristics were not shown at all, and the resistance remained high.
 (比較実験3)
 比較実験3として、図14(a)及び図14(b)に、Oプラズマの照射及びフッ酸処理を行った後に、種々の電極材料を堆積し、20mAの電流を印加した場合の電気特性を調べた結果を示す。
(Comparative Experiment 3)
As comparative experiment 3, in FIGS. 14 (a) and 14 (b), electrical characteristics when various electrode materials are deposited and a current of 20 mA is applied after O 2 plasma irradiation and hydrofluoric acid treatment are performed. The result of having investigated is shown.
 通常の「金属-半導体界面接合理論」では、仕事関数の値が小さい金属ほどn側電極材料として適する。これにより、オーミック特性を得るには、半導体における仕事関数の値、この場合はm面GaNにおける仕事関数の値よりも小さい仕事関数を持つ電極材料を選択する必要がある。前述の非特許文献2によれば、n型のm面GaNの仕事関数は3.7eVである。従って、n側電極材料として3.7eVよりも小さい仕事関数を持つ電極材料、すなわち図14で示した検討実験のなかでは、仕事関数の値が3.66eVのマグネシウム(Mg)がn側電極材料として最適であると思われる。 In the usual “metal-semiconductor interface junction theory”, a metal having a smaller work function value is more suitable as an n-side electrode material. Thus, in order to obtain ohmic characteristics, it is necessary to select an electrode material having a work function smaller than the work function value in the semiconductor, in this case, the work function value in the m-plane GaN. According to Non-Patent Document 2 described above, the work function of n-type m-plane GaN is 3.7 eV. Therefore, as an n-side electrode material, an electrode material having a work function smaller than 3.7 eV, that is, in the examination experiment shown in FIG. 14, magnesium (Mg) having a work function value of 3.66 eV is n-side electrode material. Seems to be optimal.
 しかしながら、図14(a)及び図14(b)からは、Mgをn側電極材料とした場合よりも、仕事関数の値が4.28eVのAlをn側電極材料とした場合の方が、電気特性が顕著に優れることが分かる。 However, from FIG. 14 (a) and FIG. 14 (b), the case where Al having a work function value of 4.28 eV is used as the n-side electrode material is better than the case where Mg is used as the n-side electrode material. It can be seen that the electrical characteristics are remarkably excellent.
 上記の結果は、単純な「金属-半導体界面接合理論」からは論理的に導くことができない。すなわち、表面を改質したm面GaNとAl原子との組み合わせが非常に特異的であることを示す。 The above results cannot be logically derived from a simple “metal-semiconductor interface junction theory”. That is, it shows that the combination of m-plane GaN with modified surface and Al atoms is very specific.
 このように、比較実験1、比較実験2及び比較実験3により、Oプラズマの照射及びフッ酸処理によって表面を改質したm面GaNとAl原子との組み合わせが特異的であることが明確となった。すなわち、本発明者らは、Al原子が表面改質されたm面GaNと接触していない場合は、コンタクト抵抗が極めて高くなり、Al原子が表面改質されたm面GaNと接触する場合は、コンタクト抵抗が極めて低いn側オーミック電極を実現できることを発見した。 Thus, it is clear from Comparative Experiment 1, Comparative Experiment 2, and Comparative Experiment 3 that the combination of m-plane GaN and Al atoms whose surfaces have been modified by O 2 plasma irradiation and hydrofluoric acid treatment is specific. became. That is, when the Al atoms are not in contact with the surface-modified m-plane GaN, the contact resistance becomes extremely high, and when the Al atoms are in contact with the surface-modified m-plane GaN, It was discovered that an n-side ohmic electrode with extremely low contact resistance can be realized.
 <第2の想到困難性>
 第2の想到困難性として、Oプラズマの照射を行った後に、酸処理を追加することにより、コンタクト抵抗をさらに低減したということが挙げられる。
<Second difficult difficulty>
The second conceivable difficulty is that contact resistance is further reduced by adding acid treatment after the O 2 plasma irradiation.
 特許文献4においては、c面GaNに設けるn側電極の形成技術として、Oプラズマの照射を行った後に、Ti/Alを蒸着するという方法を開示している。ここで、Oプラズマを照射する目的は、Oプラズマの照射によって、GaNの最表面に酸素(O)ドープ層を形成することである。ここで、Oドープ層とは、GaNにOがドナーとして導入されたGaNとOとの化合物層である。すなわち、ドナーとして寄与するO原子によって、GaNの最表面に高濃度のn型のキャリア層を形成することが期待されている。従って、最表面のキャリア密度を増大することによって、n側電極のコンタクト抵抗を低減するという技術は広く知られている。 In Patent Document 4, as a technique for forming an n-side electrode provided on c-plane GaN, a method of depositing Ti / Al after performing O 2 plasma irradiation is disclosed. Here, the purpose of irradiating with O 2 plasma is to form an oxygen (O) doped layer on the outermost surface of GaN by irradiating with O 2 plasma. Here, the O-doped layer is a compound layer of GaN and O in which O is introduced into GaN as a donor. That is, it is expected that a high concentration n-type carrier layer is formed on the outermost surface of GaN by O atoms contributing as donors. Therefore, a technique for reducing the contact resistance of the n-side electrode by increasing the carrier density on the outermost surface is widely known.
 この従来の技術常識に基づけば、GaNの最表面のOドープ層が重要であるため、Oドープ層を除去するような表面処理、すなわちOプラズマを照射した後に、GaNの表面に対して酸処理を施すことは全くもって理に反する。特許文献4においては、Oプラズマを照射した後に酸処理を施すという検討をも行っている。この場合は、予想通り、n側電極の電気特性が悪化したとの実験結果を得ており、これにより、Oプラズマを照射した後の酸処理は全面的に否定されている。このように、Oプラズマを照射した後の酸処理は、通常の技術常識としてはあり得ない。 Based on this conventional technical common sense, the O-doped layer on the outermost surface of GaN is important. Therefore, after surface treatment for removing the O-doped layer, that is, after irradiating O 2 plasma, the surface of GaN is treated with an acid. It is totally unreasonable to apply processing. In patent document 4, the examination of performing acid treatment after irradiating O 2 plasma is also performed. In this case, as expected, an experimental result was obtained that the electrical characteristics of the n-side electrode deteriorated, and as a result, acid treatment after irradiation with O 2 plasma was completely denied. Thus, acid treatment after irradiation with O 2 plasma is not possible as normal technical common sense.
 しかしながら、本発明者らは、Oプラズマを照射した後のGaNの表面に対して酸処理を施している。しかも、酸のなかでも酸素化合物を除去する能力が極めて高いフッ酸(HF)を用いての酸処理である。従来の技術常識では、このような酸処理を行えば、GaNの最表面近傍のOドープ層が除去されてしまい、電気特性は大きく悪化すると考えられる。これに対し、本発明者らは、Oプラズマを照射した後のGaNの表面にフッ酸処理を行うことにより、フッ酸処理の前と比べてコンタクト抵抗が低下するn側電極を実現できるということを見出した。 However, the present inventors perform acid treatment on the surface of GaN after being irradiated with O 2 plasma. Moreover, the acid treatment is performed using hydrofluoric acid (HF), which has an extremely high ability to remove oxygen compounds among acids. According to conventional common general knowledge, if such an acid treatment is performed, the O-doped layer in the vicinity of the outermost surface of GaN is removed, and the electrical characteristics are considered to be greatly deteriorated. On the other hand, the present inventors can realize an n-side electrode having a contact resistance lower than that before hydrofluoric acid treatment by performing hydrofluoric acid treatment on the surface of GaN after being irradiated with O 2 plasma. I found out.
 図15(a)及び図15(b)に、Oプラズマなし、Oプラズマ照射、及びOプラズマ照射+フッ酸処理の、それぞれの試料において、電極材料にAlを用いたn側電極の電気特性の結果を示す。ここでのシンター処理は、温度が400℃で10分間とした。Oプラズマの照射により表面が改質されたm面GaNの上に、Al膜を堆積するという組み合わせによって顕著な効果が表れることは、これまで説明してきた通りである。 15 (a) and 15 (b) show an n-side electrode using Al as the electrode material in each sample without O 2 plasma, O 2 plasma irradiation, and O 2 plasma irradiation + hydrofluoric acid treatment. The result of an electrical property is shown. Here, the sintering process was performed at a temperature of 400 ° C. for 10 minutes. As described above, a remarkable effect is exhibited by the combination of depositing an Al film on m-plane GaN whose surface has been modified by O 2 plasma irradiation.
 ここで注目すべきことは、Oプラズマを照射した後に、フッ酸による酸処理を行うことによって、電圧がさらに一桁近くも低減しており、すなわち、コンタクト抵抗のさらなる低減が実現されているということである。これは、特許文献4とは全く逆の結果であり、さらには、通常の技術常識からも理論的には導くことができない。 What should be noted here is that the voltage is further reduced by almost an order of magnitude by performing acid treatment with hydrofluoric acid after irradiation with O 2 plasma, that is, further reduction of contact resistance is realized. That's what it means. This is a result opposite to that of Patent Document 4 and cannot be theoretically derived from ordinary technical common sense.
 [メカニズムについて]
 m面GaN対してコンタクト抵抗が極めて低いn側オーミック電極が実現されるメカニズムを解明するために、各種の分析及び評価を行った。
[About the mechanism]
In order to elucidate the mechanism by which an n-side ohmic electrode with extremely low contact resistance with respect to m-plane GaN is realized, various analyzes and evaluations were performed.
 二次イオン質量分析計(Secondary Ion-microprobeMass Spectrometer:SIMS)を用いて、Oプラズマを照射する前後、及びフッ酸処理を行う前後におけるGaNの表面近傍の元素の濃度変化を分析した。 Using a secondary ion mass spectrometer (SIMS), changes in the concentration of elements near the surface of GaN before and after the O 2 plasma irradiation and before and after hydrofluoric acid treatment were analyzed.
 図16(a)は、Oプラズマを照射せずに、Al膜を蒸着した第1の試料における酸素(O)の濃度及び炭素(C)の濃度を、GaN層の深さ方向にプロットしたグラフである。なお、Al膜とGaN層との界面を深さ0と定義し、GaN層側を正方向とした。すなわち、横軸における負側はAl膜(電極)中の位置を示し、正側はGaN層中の位置を示している。 FIG. 16A plots the oxygen (O) concentration and the carbon (C) concentration in the depth direction of the GaN layer in the first sample in which the Al film was deposited without irradiating the O 2 plasma. It is a graph. The interface between the Al film and the GaN layer was defined as depth 0, and the GaN layer side was defined as the positive direction. That is, the negative side on the horizontal axis indicates the position in the Al film (electrode), and the positive side indicates the position in the GaN layer.
 図16(b)は、Oプラズマを照射した後に、Al膜を蒸着した第2の試料におけるOの濃度とCの濃度とを、GaN層の深さ方向にプロットしたグラフである。Oプラズマの照射によって、O原子が増加し、一方でC原子が減少していることが分かる。 FIG. 16B is a graph in which the O concentration and the C concentration in the second sample in which the Al film is deposited after the O 2 plasma irradiation are plotted in the depth direction of the GaN layer. It can be seen that O atoms increase while C atoms decrease due to the O 2 plasma irradiation.
 図16(c)は、Oプラズマの照射及びフッ酸処理を行った後に、Al膜を蒸着した第3の試料におけるOの濃度及びCの濃度を、GaN層の深さ方向にプロットしたグラフである。Cの濃度はOプラズマの照射後から変化していないが、Oプラズマの照射で増加したO原子がフッ酸処理によって除去されていることが分かる。 FIG. 16C is a graph in which the concentration of O and the concentration of C in the third sample in which an Al film is deposited after O 2 plasma irradiation and hydrofluoric acid treatment are plotted in the depth direction of the GaN layer. It is. C concentration has not changed after the irradiation of the O 2 plasma, it can be seen that O atoms which is increased by irradiation of O 2 plasma is removed by hydrofluoric acid treatment.
 図16(b)から分かるように、Oプラズマの照射によってC原子が除去されていることから、Oプラズマの照射によるGaN層の表面におけるカーボン(C)汚染の除去、すなわち不純物による電位障壁の除去が、n側電極のオーミック特性化及びコンタクト抵抗の低減の1つの要因となっている可能性が考えられる。 As can be seen from FIG. 16 (b), the since the C atoms have been removed by irradiation of O 2 plasma, the removal of carbon (C) contamination in the surface of the GaN layer due to irradiation with O 2 plasma, i.e. the potential barrier due to impurity It is conceivable that the removal of this is one factor in the ohmic characteristics of the n-side electrode and the reduction in contact resistance.
 また、 図16(c)から分かるように、フッ酸処理の後に、O原子が除去されている。これは、n側電極の電気特性がフッ酸処理後の方が処理前と比べて良好であったという実験結果から、除去されたO原子は「Oドープ層」に起因するのではなく、電位障壁として寄与する表面酸化膜又は表面アモルファス等に起因すると考えられる。ここで、表面酸化膜又は表面アモルファスは、いずれもGaと表記される。 Further, as can be seen from FIG. 16C, O atoms are removed after the hydrofluoric acid treatment. This is because, from the experimental results that the electrical characteristics of the n-side electrode were better after the hydrofluoric acid treatment than before the treatment, the removed O atoms were not caused by the “O-doped layer” but the potential. This is considered to be caused by a surface oxide film or a surface amorphous film that contributes as a barrier. Here, both the surface oxide film and the surface amorphous are expressed as Ga x O y .
 次に、Oプラズマの照射によるOドープ層の形成の有無を明確にするために、GaN層の表面近傍におけるキャリア密度の深さ方向分布を容量-電圧(C-V)評価法を用いて調べた。 Next, in order to clarify whether or not an O-doped layer is formed by O 2 plasma irradiation, the depth direction distribution of the carrier density in the vicinity of the surface of the GaN layer is determined using a capacitance-voltage (CV) evaluation method. Examined.
 図17(a)は、Oプラズマを照射しないm面GaNである第1の試料、Oプラズマを照射したm面GaNである第2の試料、並びにOプラズマの照射及びフッ酸処理を行ったm面GaNである第3の試料のそれぞれにおいて、キャリア密度(N-N)をGaN層の深さ方向にプロットしたグラフである。第2の試料からは、Oプラズマの照射によってGaN層の表面近傍、すなわち表面からおよそ150nmまでの領域のキャリア密度が減少していることが分かる。また、第3の試料からは、Oプラズマを照射した後に、フッ酸処理を行ってもキャリア密度はほぼ不変であることが分かる。 FIG. 17 (a), the first sample is a m-plane GaN is not irradiated with O 2 plasma, the second sample of O 2 plasma is irradiated m-plane GaN, as well as O 2 plasma exposure, and hydrofluoric acid treatment of the in each went third sample is a m-plane GaN, a plot of carrier density (N D -N a) in the depth direction of the GaN layer. From the second sample, it can be seen that the carrier density in the vicinity of the surface of the GaN layer, that is, the region from the surface to about 150 nm is reduced by the O 2 plasma irradiation. Further, it can be seen from the third sample that the carrier density is almost unchanged even when hydrofluoric acid treatment is performed after the O 2 plasma is irradiated.
 特許文献4に記載されるように、もし、Oプラズマの照射によってOドープ層が形成されているのであれば、Oプラズマを照射した後のGaN層の表面近傍におけるキャリア密度は増加するはずである。さらに、特許文献4に記載されるように、プラズマ照射の後の酸処理によって、Oドープ層が除去されるのであれば、フッ酸処理の後においてはキャリア密度は元に戻るはずである。 As described in Patent Document 4, if, as long as the O-doped layer is formed by irradiation of O 2 plasma, should the carrier density increases near the surface of the GaN layer after irradiation with O 2 plasma It is. Further, as described in Patent Document 4, if the O-doped layer is removed by the acid treatment after the plasma irradiation, the carrier density should return to the original after the hydrofluoric acid treatment.
 しかしながら、本実施形態に係る実験結果が示すように、m面GaN層に対してOプラズマを照射してもキャリア密度は増加するどころか、逆に減少している。また、その後のフッ酸処理によってもキャリア密度はほとんど不変である。これらの結果は、m面GaN層に対してOプラズマを照射しても、Oドープ層は形成されないことを意味する。従って、特許文献4に記載されているc面GaNに対するOプラズマの照射の場合とは起こっている物理現象が本質的に異なっていることを強く示唆する。 However, as the experimental result according to the present embodiment, let alone be irradiated with O 2 plasma with respect to m-plane GaN layer carrier density is increased, it is reduced to the contrary. Also, the carrier density is almost unchanged by the subsequent hydrofluoric acid treatment. These results mean that the O-doped layer is not formed even if the m-plane GaN layer is irradiated with O 2 plasma. Therefore, it strongly suggests that the physical phenomenon occurring is substantially different from the case of irradiation of O 2 plasma to c-plane GaN described in Patent Document 4.
 図17(b)は、Oプラズマを照射した第2の試料、並びにOプラズマの照射及びフッ酸処理を行った第3の試料のそれぞれのキャリア密度を、Oプラズマを照射しない第1の試料のキャリア密度で規格化した、すなわち、キャリア密度の比の値を示したグラフである。例えば、m面GaN層の表面から深さが90nmの位置においては、キャリア密度が、第1の試料と比べておよそ0.6倍に減少していることが分かる。 FIG. 17 (b), a second sample was irradiated with O 2 plasma, and O 2 plasma irradiation and the respective carrier densities of the third sample subjected to hydrofluoric acid treatment, first without irradiating the O 2 plasma It is the graph which normalized the carrier density of the sample of, ie, showed the value of ratio of carrier density. For example, it can be seen that the carrier density is reduced by about 0.6 times compared to the first sample at a position where the depth is 90 nm from the surface of the m-plane GaN layer.
 キャリア密度の減少の要因は定かではないが、例えば1つの物理モデルとして、Oプラズマの照射によってm面GaN層の表面近傍に結晶欠陥が形成され、その形成された結晶欠陥がドナーキャリアをトラップするために、キャリア密度が減少すると考えることができる。 Although the cause of the decrease in carrier density is not clear, for example, as one physical model, crystal defects are formed near the surface of the m-plane GaN layer by O 2 plasma irradiation, and the formed crystal defects trap donor carriers. Therefore, it can be considered that the carrier density decreases.
 次に、Oプラズマの照射による結晶欠陥の形成の有無を明らかにするために、m面GaN層の表面に対してフォトルミネッセンスによる評価を行った。 Next, in order to clarify the presence or absence of the formation of crystal defects by irradiation with O 2 plasma, the surface of the m-plane GaN layer was evaluated by photoluminescence.
 図18は、Oプラズマを照射しない第1の試料、Oプラズマを照射した第2の試料、並びにOプラズマの照射及びフッ酸処理を行った第3の試料のそれぞれに対して、フォトルミネッセンス評価(PL評価)を行った結果を示している。Oプラズマを照射した第2の試料の場合は、GaNにおけるバンド端発光が一桁程度弱くなるという結果を得た。この結果は、非発光中心として作用し得る結晶欠陥がOプラズマの照射により形成されたことを示唆する。ここで、GaNにおける代表的な結晶欠陥である窒素空孔に起因する波長が500nm~600nmの波長領域にはイエロールミネッセンスが観測されていない。このことから、窒素空孔以外の何らかの複合欠陥が形成されている可能性が高い。また、第3の試料である、Oプラズマの照射後にフッ酸処理を行っても、PLスペクトルは不変であることから、フッ酸処理によっては、結晶欠陥領域は除去されていないことが分かる。 Figure 18 is a first sample not irradiated with O 2 plasma, a second sample was irradiated with O 2 plasma, and for each of the third sample subjected to irradiation and hydrofluoric acid treatment of the O 2 plasma, photo The result of performing luminescence evaluation (PL evaluation) is shown. In the case of the second sample irradiated with O 2 plasma, the band edge emission in GaN was reduced by about one digit. This result suggests that crystal defects that can act as non-luminescent centers were formed by O 2 plasma irradiation. Here, no yellow luminescence is observed in the wavelength region of 500 nm to 600 nm due to nitrogen vacancies which are typical crystal defects in GaN. From this, it is highly possible that some complex defects other than nitrogen vacancies are formed. In addition, even if hydrofluoric acid treatment is performed after irradiation of O 3 plasma, which is the third sample, the PL spectrum is unchanged, so that it can be seen that the crystal defect region is not removed by hydrofluoric acid treatment.
 以上の実験結果から、GaN層の表面にOプラズマを照射することにより、GaN層の表面近傍に結晶欠陥が形成されたと考えられる。本発明者らは、結晶欠陥準位を介在したトンネル電流によって、m面GaNに対して良好なn側オーミック電極が実現されるというメカニズムを模索している。しかし、たとえOプラズマの照射によってm面GaN層の表面を改質しても、そこにAl原子が接触していなければ全く効果が発現しないため、現段階ではこのモデルによって全てを説明することはできない。効果の発現のために、なぜAl原子が必須であるのかを解明することが重要である。 From the above experimental results, it is considered that crystal defects were formed near the surface of the GaN layer by irradiating the surface of the GaN layer with O 2 plasma. The present inventors have sought a mechanism that a good n-side ohmic electrode is realized with respect to m-plane GaN by a tunnel current through which a crystal defect level is interposed. However, even if the surface of the m-plane GaN layer is modified by irradiation with O 2 plasma, no effect will be produced unless Al atoms are in contact therewith. I can't. It is important to elucidate why Al atoms are essential for the manifestation of effects.
 ここで改めて、Oプラズマの照射によってGaN表面近傍に形成される「表面改質層」について定義する。 Here, the “surface modified layer” formed in the vicinity of the GaN surface by the O 2 plasma irradiation is defined again.
 図18に示したフォトルミネッセンスの評価から、表面改質層は結晶欠陥を含むと考えられる。結晶欠陥密度は、1つの結晶欠陥が1つのキャリアをトラップすると仮定した場合に、図17(a)を参照すれば、例えばGaN層の表面から深さが90nmの位置ではキャリア密度が0.7×1017cm-3だけ減少していることから、この領域での結晶欠陥密度は0.7×1017cm-3と考えられる。しかしながら、Oプラズマの照射がGaN層の表面に与える影響が解明されていない以上、結晶欠陥密度を断定することは難しい。 From the evaluation of photoluminescence shown in FIG. 18, it is considered that the surface modified layer contains crystal defects. When it is assumed that one crystal defect traps one carrier, referring to FIG. 17A, for example, the carrier density is 0.7 nm at a depth of 90 nm from the surface of the GaN layer. Since it is decreased by × 10 17 cm −3 , the crystal defect density in this region is considered to be 0.7 × 10 17 cm −3 . However, it is difficult to determine the crystal defect density as long as the influence of O 2 plasma irradiation on the surface of the GaN layer has not been elucidated.
 本実施形態においては、表面改質層は、Oプラズマを照射しない場合のキャリア密度よりも低いキャリア密度を持つ領域として定義する。より具体的には、例えば、Oプラズマを照射しない場合のキャリア密度の0.9倍以下のキャリア密度を持つ領域と定義することができる。キャリア密度の減少は、結晶欠陥に起因して引き起こされていると考えている。例えば、1つの結晶欠陥が1つのキャリアをトラップすると仮定すれば、ドナー密度の1割の結晶欠陥密度の形成によって、キャリア密度の比の値は0.9となる。 In the present embodiment, the surface modified layer is defined as a region having a carrier density lower than the carrier density when not irradiated with O 2 plasma. More specifically, for example, it can be defined as a region having a carrier density of 0.9 times or less of the carrier density when not irradiated with O 2 plasma. It is believed that the decrease in carrier density is caused by crystal defects. For example, assuming that one crystal defect traps one carrier, the value of the carrier density ratio becomes 0.9 by forming a crystal defect density of 10% of the donor density.
 また、表面改質層の厚さは、Oプラズマを照射しない場合のキャリア密度よりも低いキャリア密度を持つ領域までの深さとして定義する。より具体的には、例えば、キャリア密度の比の値が、上述の0.9となる部分までの深さと定義することができる。このように定義すると、本実施形態においては、図17(b)から、表面改質層の厚さはおよそ120nmである。 Further, the thickness of the surface modification layer is defined as the depth to a region having a carrier density lower than the carrier density when not irradiated with O 2 plasma. More specifically, for example, it can be defined as the depth to the portion where the value of the carrier density ratio becomes 0.9 as described above. If it defines in this way, in this embodiment, the thickness of a surface modification layer is about 120 nm from FIG.17 (b).
 一般に、半導体層にプラズマを照射した場合は、照射された半導体層の表面から10nm程度は何らかの直接的な影響があると言われている。従って、表面改質層の厚さは、例えば、10nm程度であってもよい。もちろん、本実施形態の120nmのように、10nm以上であってもよい。また、10nm以下であっても、表面改質層が形成されていれば、表面改質層とAl原子とが接触することによるコンタクト抵抗の低減効果を適切に得ることができる。 Generally, when a semiconductor layer is irradiated with plasma, it is said that about 10 nm from the surface of the irradiated semiconductor layer has some direct influence. Therefore, the thickness of the surface modification layer may be about 10 nm, for example. Of course, it may be 10 nm or more like 120 nm in the present embodiment. Even when the thickness is 10 nm or less, if the surface modification layer is formed, the contact resistance reduction effect due to the contact between the surface modification layer and the Al atoms can be appropriately obtained.
 最後に、本実施形態の特徴を総括する。コンタクト抵抗が小さいオーミック電極を形成するには、電極を形成する最表面のキャリア密度を増大させる手法が広く一般的に用いられている。例えば、半導体層の最表面にドーパントを高濃度にドープすることにより高キャリア密度層を形成し、その上に電極を形成するという手法である。しかしながら、本実施形態においては、通常の技術常識とは逆に、最表面のキャリア密度が減少したm面GaN、すなわち表面を改質したm面GaNの上に電極を形成する。 Finally, the features of this embodiment will be summarized. In order to form an ohmic electrode having a small contact resistance, a technique for increasing the carrier density on the outermost surface on which the electrode is formed is widely used. For example, there is a technique of forming a high carrier density layer by doping a dopant at a high concentration on the outermost surface of a semiconductor layer and forming an electrode thereon. However, in the present embodiment, contrary to normal technical common sense, an electrode is formed on m-plane GaN having a reduced carrier density on the outermost surface, that is, m-plane GaN having a modified surface.
 本実施形態の他の特徴は、表面改質層と接触する電極材料がアルミニウム(Al)又はアルミニウム(Al)を主成分とする金属において特に顕著な効果を発現するということである。本発明者らの実験によれば、Oプラズマを照射しないm面GaNに対してAl電極を設けた場合は、非常に高いコンタクト抵抗となった。従って、m面GaNに対してAlを適用することは全く不適当であると思われた。しかしながら、表面を改質したm面GaNに対し、あえてAl電極を設けたところ、他の金属から形成される電極では得られなかった顕著な効果が得られた。 Another feature of the present embodiment is that the electrode material in contact with the surface modified layer exhibits a particularly remarkable effect in a metal mainly composed of aluminum (Al) or aluminum (Al). According to the experiments by the present inventors, when an Al electrode was provided for m-plane GaN that was not irradiated with O 2 plasma, the contact resistance was very high. Therefore, it seemed quite inappropriate to apply Al to m-plane GaN. However, when an Al electrode was provided for m-plane GaN whose surface was modified, a remarkable effect that could not be obtained with an electrode formed from another metal was obtained.
 本実施形態のさらなる特徴は、Oプラズマを照射してその表面を改質したm面GaN層に対して酸処理を行っている点である。特許文献4にも示されているように、通常の技術常識では、Oプラズマを照射した後に酸処理を行えば、Oドープ層が除去されるためにキャリア密度が高い領域が除去されてしまい、n側電極の特性は悪化する。しかしながら、本実施形態においては、逆に、酸処理を行うことによって、さらなるコンタクト抵抗の低減を実現することができる。 A further feature of this embodiment is that the m-plane GaN layer whose surface has been modified by irradiation with O 2 plasma is subjected to acid treatment. As shown in Patent Document 4, in general technical common sense, if an acid treatment is performed after irradiating O 2 plasma, an O-doped layer is removed, and thus a region having a high carrier density is removed. The characteristics of the n-side electrode deteriorate. However, in the present embodiment, on the contrary, the contact resistance can be further reduced by performing the acid treatment.
 本実施形態に係る「Oプラズマ照射により表面改質したm面GaN」と「Al原子」との組み合わせという構成についての、真のメカニズムの解明には至っていない。これまで述べてきたメカニズム以外の他の本質的なメカニズムによって本開示が実現している可能性も十分にあり得る。しかしながら、「Oプラズマ照射により表面改質したm面GaN」と「Al原子」という特別な組み合わせにおいて高い再現性をもって顕著な効果が発現する。 The true mechanism of the combination of “m-plane GaN surface-modified by O 2 plasma irradiation” and “Al atoms” according to the present embodiment has not yet been elucidated. It is possible that the present disclosure may be realized by other essential mechanisms other than those described above. However, a remarkable effect is exhibited with high reproducibility in a special combination of “m-plane GaN surface-modified by O 2 plasma irradiation” and “Al atoms”.
 上述した通り、n側電極の材料がAl単体(すなわちAlの濃度が100%の金属)の場合、良好なコンタクト抵抗を得られる。しかし、この効果は、表面改質したm面GaNとAl原子との接触により得られるので、n側電極の材料は必ずしもAl単体である必要はない。Alを主成分とする金属であってもよい。すなわち、n側電極の材料は、Alを主成分としAl以外の原子を不純物レベルで含んでいる金属であってもよい。また、全体の90質量%以上をAl原子で占めている金属であってもよい。また、全体の半分以上(すなわち50質量%以上)をAl原子で占めている金属であってもよい。さらに言えば、たとえ電極材料のAlの濃度が50質量%未満であったとしても、Al原子が表面改質したm面GaNと接触している状況が実現されていれば、原理的には本実施形態の効果は発現すると考えられる。従って、電極材料のAlの濃度に拘わらず、Al原子が表面改質したm面GaNと接触している状況が実現されていれば、本開示の範囲内に含まれる。 As described above, when the material of the n-side electrode is Al alone (that is, a metal having an Al concentration of 100%), good contact resistance can be obtained. However, since this effect is obtained by contact between the surface-modified m-plane GaN and Al atoms, the material of the n-side electrode does not necessarily need to be Al alone. A metal mainly composed of Al may be used. That is, the material of the n-side electrode may be a metal containing Al as a main component and atoms other than Al at the impurity level. Moreover, the metal which occupies 90 mass% or more of the whole with the Al atom may be sufficient. Moreover, the metal which occupies more than half (namely, 50 mass% or more) of the whole with Al atom may be sufficient. Furthermore, even if the concentration of Al in the electrode material is less than 50% by mass, if the situation where Al atoms are in contact with the surface-modified m-plane GaN is realized, in principle The effect of the embodiment is considered to be manifested. Therefore, it is included in the scope of the present disclosure if a situation in which Al atoms are in contact with the surface-modified m-plane GaN is realized regardless of the Al concentration of the electrode material.
 n側電極の材料がAl合金である場合は、例えばAlSi又はAlSiCu等であってもよい。これらのAl合金をn側電極に用いることにより、コンタクト抵抗の低減に加えて、電極の信頼性を向上することも期待できる。この場合、Alの濃度は98質量%以上、Si及びCuの濃度は2質量%以下であってもよい。 When the material of the n-side electrode is an Al alloy, for example, AlSi or AlSiCu may be used. Use of these Al alloys for the n-side electrode can be expected to improve the reliability of the electrode in addition to reducing the contact resistance. In this case, the Al concentration may be 98% by mass or more, and the Si and Cu concentrations may be 2% by mass or less.
 図19は熱処理前のGa原子の深さ方向のプロファイルを表している。ここでは、二次イオン質量分析計(Secondary ion mass spectrometry :SIMS)によるGaの元素分析の結果を表している。表面からの深さが200nm付近に破線で示した位置がAl電極とn-GaNとの界面に相当する。酸素プラズマ処理を行わない場合(○印)と比較して、酸素プラズマ処理を行った場合(■印)、及び酸素プラズマ処理後にBHF(バッファードフッ酸)により処理を行った場合(▲印)では、Al電極とn-GaNとの界面におけるGa原子の濃度が増大していることが観測される。一方、深さが250nmから300nm付近においては、n-GaN中のGa原子の濃度は、酸素プラズマ処理を行った場合、及び酸素プラズマ処理後にBHFにより処理を行った場合に減少していることが観測される。この結果から、酸素プラズマ処理を行った場合及び酸素プラズマ処理後にBHFにより処理を行った場合は、n-GaNからGa原子がAl電極とn-GaNとの界面に拡散すると考えられる。これは、Ga原子の拡散によって、n-GaNにGaの空孔が形成されていることを示唆している。 FIG. 19 shows a profile in the depth direction of Ga atoms before the heat treatment. Here, the result of elemental analysis of Ga by a secondary ion mass spectrometer (Secondary ion mass spectrometer: SIMS) is shown. The position indicated by a broken line near the depth of 200 nm from the surface corresponds to the interface between the Al electrode and n-GaN. Compared to the case where oxygen plasma treatment is not performed (○ mark), when oxygen plasma treatment is performed (■ mark), and after oxygen plasma treatment using BHF (buffered hydrofluoric acid) (▲ mark) Then, it is observed that the concentration of Ga atoms at the interface between the Al electrode and n-GaN is increased. On the other hand, when the depth is in the vicinity of 250 nm to 300 nm, the concentration of Ga atoms in n-GaN decreases when oxygen plasma treatment is performed and when treatment with BHF is performed after oxygen plasma treatment. Observed. From this result, it is considered that Ga atoms diffuse from the n-GaN to the interface between the Al electrode and n-GaN when the oxygen plasma treatment is performed and when the treatment is performed with BHF after the oxygen plasma treatment. This suggests that Ga vacancies are formed in n-GaN due to the diffusion of Ga atoms.
 図20は500℃の温度で10分間のシンター処理を行ったときの結果を表している。図20に示すように、シンター処理前においてAl電極とn-GaNとの界面に拡散したGa原子は、Al電極側にさらに拡散しており、パイルアップは見られない。しかし、深さが250nm付近においては、n-GaNにおけるGa原子の濃度は、酸素プラズマ処理を行った場合(■印)、及び酸素プラズマ処理後にGHFにより処理を行った場合(▲印)に減少していることが分かる。この結果からも、Ga原子の拡散によって、n-GaNにGaの空孔が形成されていることが示唆される。 FIG. 20 shows the result when a sintering process is performed at a temperature of 500 ° C. for 10 minutes. As shown in FIG. 20, Ga atoms diffused at the interface between the Al electrode and n-GaN before the sintering process are further diffused to the Al electrode side, and no pile-up is observed. However, at a depth of about 250 nm, the concentration of Ga atoms in n-GaN decreases when oxygen plasma treatment is performed (marked with ■) and when treated with GHF after oxygen plasma treatment (marked with ▲). You can see that This result also suggests that Ga vacancies are formed in n-GaN due to the diffusion of Ga atoms.
 図21は、プラズマパワー、酸素流量及びプラズマ処理時間を変化させた場合の、n側電極を構成するテストパターン同士の間の100mAの通電時における電圧の変化を示している。図中にn側電極のテストパターンの配置を示す。ここでの電極間の距離は20μmである。本実験では、これら2つのn側電極同士の間の電圧を測定しており、その電圧はn側電極におけるコンタクト抵抗を反映する。電圧が低い場合は、コンタクト抵抗が低いことを示唆する。まず、プラズマの処理時間が異なる場合を比較する。第1の処理(I)として、プラズマパワーを10W、酸素流量を30ml/min(0℃,1atm)及び処理時間を30sとする。第2の処理(II)として、プラズマパワーを10W、酸素流量を30ml/min(0℃,1atm)及び処理時間を300sとする。第1の処理(I)と第2の処理(II)とを比較すると、第2の処理(II)の方が電圧が低いことが分かる。これは、n側電極のコンタクト抵抗が酸素プラズマの処理時間を増大することにより減少することを示している。さらに、プラズマパワーが異なる場合を比較する。ここでは、第1の処理と、第3の処理(III)であるプラズマパワーを40W、酸素流量を30ml/min(0℃,1atm)及び処理時間を30sの場合とを比較すると、第3の処理(III)の方が電圧が低いことが分かる。これも、n側電極のコンタクト抵抗が酸素プラズマにおけるプラズマパワーを増大することにより減少することを示している。さらに、酸素流量が異なる場合を比較する。ここでは、第3の処理(III)と、第4の処理(IV)であるプラズマパワーを40W、酸素流量を10ml/min(0℃,1atm)及び処理時間を30sの場合とを比較すると、第3の処理(III)の方が電圧が低いことが分かる。これも、n側電極のコンタクト抵抗が酸素プラズマ処理における酸素流量を増大することにより減少することを示している。 FIG. 21 shows a change in voltage during energization of 100 mA between the test patterns constituting the n-side electrode when the plasma power, the oxygen flow rate, and the plasma processing time are changed. The arrangement of the n-side electrode test pattern is shown in the figure. The distance between the electrodes here is 20 μm. In this experiment, the voltage between these two n-side electrodes is measured, and the voltage reflects the contact resistance at the n-side electrode. A low voltage suggests a low contact resistance. First, a case where plasma processing times are different is compared. As the first treatment (I), the plasma power is 10 W, the oxygen flow rate is 30 ml / min (0 ° C., 1 atm), and the treatment time is 30 s. As the second treatment (II), the plasma power is 10 W, the oxygen flow rate is 30 ml / min (0 ° C., 1 atm), and the treatment time is 300 s. Comparing the first process (I) and the second process (II), it can be seen that the voltage of the second process (II) is lower. This indicates that the contact resistance of the n-side electrode is decreased by increasing the processing time of the oxygen plasma. Furthermore, the case where plasma power differs is compared. Here, when the first process is compared with the third process (III) when the plasma power is 40 W, the oxygen flow rate is 30 ml / min (0 ° C., 1 atm), and the process time is 30 s, It can be seen that the voltage is lower in the process (III). This also indicates that the contact resistance of the n-side electrode decreases with increasing plasma power in oxygen plasma. Furthermore, the case where oxygen flow rates differ is compared. Here, comparing the third process (III) and the fourth process (IV) with a plasma power of 40 W, an oxygen flow rate of 10 ml / min (0 ° C., 1 atm) and a processing time of 30 s, It can be seen that the voltage is lower in the third process (III). This also indicates that the contact resistance of the n-side electrode is decreased by increasing the oxygen flow rate in the oxygen plasma treatment.
 以上をまとめると、プラズマパワーを増大すること、酸素流量を増大すること、及び処理時間を増大することにより、n側電極のコンタクト抵抗が減少する。プラズマパワーを増大すること、酸素流量を増大すること、及び処理時間を増大することは、n-GaN層に、プラズマ処理よって与える物理的スパッタによる衝撃エネルギーを増大させることに他ならない。図19及び図20の元素分析の結果と併せて考えると、n-GaN層にプラズマ処理よってGaの空孔が形成され、Gaの空孔濃度が高くなると共に、コンタクト抵抗が減少することを示している。 In summary, the contact resistance of the n-side electrode decreases by increasing the plasma power, increasing the oxygen flow rate, and increasing the processing time. Increasing the plasma power, increasing the oxygen flow rate, and increasing the processing time is nothing but increasing the impact energy by physical sputtering imparted to the n-GaN layer by the plasma processing. 19 and 20 together with the results of elemental analysis, it is shown that Ga vacancies are formed in the n-GaN layer by plasma treatment, the Ga vacancies increase, and the contact resistance decreases. ing.
 これと同様な傾向を示す結果を図22に示す。図22はプラズマの投入パワーとコンタクト抵抗値との関係を表している。プラズマパワーを10Wから40W付近まで増大すると、コンタクト抵抗の減少が観測される。プラズマパワーが120W程度までは、極めて良好な低コンタクト抵抗を示す。しかしながら、プラズマパワーが120Wを超えて増大すると、逆にコンタクト抵抗が増加に転じる。すなわち、プラズマパワーは、40Wから120W付近に最適な値が存在する。これは、プラズマパワーが極めて低い場合は、Gaの空孔濃度が低く、コンタクト抵抗が低減できないと考えられる。一方、プラズマパワーが高すぎて、衝撃エネルギーが大きくなりすぎると、Gaの空孔以外の欠陥、例えば窒素空孔及びその複合欠陥等の濃度が増大して、Gaの空孔による効果がこれらの欠陥によってスクリーニングされて、コンタクト抵抗が増加すると考えられる。 The results showing the same tendency are shown in FIG. FIG. 22 shows the relationship between plasma input power and contact resistance value. When the plasma power is increased from 10 W to around 40 W, a decrease in contact resistance is observed. Very good low contact resistance is exhibited up to a plasma power of about 120 W. However, when the plasma power increases beyond 120 W, the contact resistance starts to increase. That is, the plasma power has an optimum value in the vicinity of 40W to 120W. This is considered that when the plasma power is extremely low, the Ga vacancy concentration is low and the contact resistance cannot be reduced. On the other hand, if the plasma power is too high and the impact energy is too high, the concentration of defects other than Ga vacancies, such as nitrogen vacancies and their composite defects, will increase, and the effect of Ga vacancies Screening for defects is thought to increase contact resistance.
 図23は、図3に示す領域Aを拡大して表している。 FIG. 23 shows the area A shown in FIG. 3 in an enlarged manner.
 図23に示すように、本実施形態に係る窒化物半導体積層構造は、n側電極40、及び非極性面又は半極性面を持つ表面改質層23を有するn型窒化物半導体層22を具備する。n側電極40は、アルミニウム部分40aを具備する。アルミニウム部分40aは、n型窒化物半導体層22の表面と接している。図19から図22及びその説明により明らかなように、表面改質層23に形成されたGaの空孔のために、アルミニウム部分40aと接しているn型窒化物半導体層22の表面改質層23における窒素(N)原子の濃度は、アルミニウム部分40aと接しているn型窒化物半導体層22の表面改質層23におけるガリウム(Ga)原子の濃度よりも高い。 As shown in FIG. 23, the nitride semiconductor multilayer structure according to this embodiment includes an n-side electrode 40 and an n-type nitride semiconductor layer 22 having a surface modification layer 23 having a nonpolar surface or a semipolar surface. To do. The n-side electrode 40 includes an aluminum portion 40a. Aluminum portion 40 a is in contact with the surface of n-type nitride semiconductor layer 22. As apparent from FIGS. 19 to 22 and the description thereof, the surface modified layer of the n-type nitride semiconductor layer 22 in contact with the aluminum portion 40a due to Ga vacancies formed in the surface modified layer 23. The concentration of nitrogen (N) atoms in 23 is higher than the concentration of gallium (Ga) atoms in the surface modification layer 23 of the n-type nitride semiconductor layer 22 in contact with the aluminum portion 40a.
 ここで、Gaの空孔を有する表面下記質層23は、10nm以上且つ150nm以下の厚さを有していてもよい。 Here, the following surface layer 23 having Ga vacancies may have a thickness of 10 nm or more and 150 nm or less.
 図23においては、n側電極40は、アルミニウム部分40a及びその上に形成された金属部40bから構成されている。アルミニウム部分40aは、アルミニウム(Al)のみから形成されていてもよい。金属部40bもまた、アルミニウム(Al)のみから形成することができる。言い換えれば、n側電極40の全体がアルミニウムのみから形成することができる。但し、金属部40bは、アルミニウム以外の金属から形成することができる。このような金属の例は、白金(Pt)、ニッケル(Ni)、金(Au)、チタン(Ti)、又はパラジウム(Pd)である。 In FIG. 23, the n-side electrode 40 is composed of an aluminum portion 40a and a metal portion 40b formed thereon. The aluminum part 40a may be formed only from aluminum (Al). The metal part 40b can also be formed only from aluminum (Al). In other words, the entire n-side electrode 40 can be formed only from aluminum. However, the metal part 40b can be formed from metals other than aluminum. Examples of such metals are platinum (Pt), nickel (Ni), gold (Au), titanium (Ti), or palladium (Pd).
 図23に示すように、アルミニウム部分40aと金属部40bとは、層状をなし、且つその界面はn型窒化物半導体層22に対して平行又はほぼ平行であってもよい。言い換えれば、層状を有するアルミニウム部分40aが、層状を有する金属部40b及びn型窒化物半導体層22の間に挟まれていてもよい。但し、金属部40bは、n型窒化物半導体層22と接していない。 23, the aluminum portion 40a and the metal portion 40b may be layered, and the interface thereof may be parallel or substantially parallel to the n-type nitride semiconductor layer 22. In other words, the aluminum portion 40 a having a layer shape may be sandwiched between the metal portion 40 b having a layer shape and the n-type nitride semiconductor layer 22. However, the metal portion 40 b is not in contact with the n-type nitride semiconductor layer 22.
 図24は、図23に示す構成の第1変形例を示している。図24に示すように、アルミニウム合金部40cを、アルミニウム部分40a及び金属部40bの間に形成してもよい。例えば、アルミニウム部分40aの一部及び金属部40の一部が、アルミニウム部分40aと金属部40bとの界面において合金化され、アルミニウム合金部40cが形成される場合がある。アルミニウム合金部40cは、アルミニウム-白金(AlPt)合金、アルミニウム-ニッケル(AlNi)合金、アルミニウム-金(AlAu)合金、アルミニウム-チタン(AlTi)合金、又はアルミニウム-パラジウム(AlPd)合金により形成することができる。アルミニウム合金部40cもまた、層状を有していてもよい。 FIG. 24 shows a first modification of the configuration shown in FIG. As shown in FIG. 24, the aluminum alloy part 40c may be formed between the aluminum part 40a and the metal part 40b. For example, a part of the aluminum part 40a and a part of the metal part 40 may be alloyed at the interface between the aluminum part 40a and the metal part 40b to form the aluminum alloy part 40c. The aluminum alloy portion 40c is formed of an aluminum-platinum (AlPt) alloy, an aluminum-nickel (AlNi) alloy, an aluminum-gold (AlAu) alloy, an aluminum-titanium (AlTi) alloy, or an aluminum-palladium (AlPd) alloy. Can do. The aluminum alloy portion 40c may also have a layer shape.
 図25及び図26は、第2変形例及び第3変形例を示している。図25及び図26に示すように、それぞれ、複数個に分割されたアルミニウム部分40aをn型窒化物半導体層22の表面改質層23の上に接するように形成してもよい。言い換えれば、第2変形例及び第3変形例に係る構成においては、金属部40b又はアルミニウム合金部40cが、複数のアルミニウム部分40aを覆うように、n型窒化物半導体層22の表面改質層23と接していてもよい。 25 and 26 show a second modification and a third modification. As shown in FIGS. 25 and 26, a plurality of divided aluminum portions 40a may be formed on the surface modification layer 23 of the n-type nitride semiconductor layer 22, respectively. In other words, in the configuration according to the second modification and the third modification, the surface modification layer of the n-type nitride semiconductor layer 22 so that the metal portion 40b or the aluminum alloy portion 40c covers the plurality of aluminum portions 40a. 23 may be in contact.
 本発明は、例えば、LED素子等の発光素子に利用し得る。 The present invention can be used for light emitting elements such as LED elements, for example.
10  GaN系基板
10a 主面
20  半導体積層構造
22  n型窒化物半導体層
23  表面改質層
24  活性層
26  p型窒化物半導体層
30  p側電極
40  n側電極
40a アルミニウム部分
40b 金属部
40c アルミニウム合金部
42  凹部
50  m面GaN層
51  n側電極
52  表面改質層
53  電流源
54  電圧計
55  プローブ針
100 窒化物半導体発光素子
200 樹脂層
210 配線パターン
220 保持部材
240 反射部材
DESCRIPTION OF SYMBOLS 10 GaN-type board | substrate 10a Main surface 20 Semiconductor laminated structure 22 N type nitride semiconductor layer 23 Surface modification layer 24 Active layer 26 P type nitride semiconductor layer 30 P side electrode 40 N side electrode 40a Aluminum part 40b Metal part 40c Aluminum alloy Portion 42 Recess 50 m-plane GaN layer 51 n-side electrode 52 surface modification layer 53 current source 54 voltmeter 55 probe needle 100 nitride semiconductor light emitting element 200 resin layer 210 wiring pattern 220 holding member 240 reflecting member

Claims (26)

  1.  窒化物半導体発光素子であって、以下を具備する:
     n側電極、
     p側電極、
     非極性面又は半極性面の表面を有するn型窒化物半導体層、
     前記p側電極に電気的に接続されたp型窒化物半導体層、及び
     前記n型窒化物半導体層及びp型窒化物半導体層の間に挟まれた活性層、ここで、
     n側電極は、アルミニウム部分を具備し、
     前記アルミニウム部分は、n型窒化物半導体層の表面と接しており、
     前記アルミニウム部分と接しているn型窒化物半導体層の表面における窒素原子の濃度は、前記アルミニウム部分と接しているn型窒化物半導体層の表面におけるガリウム原子の濃度よりも高い。
    A nitride semiconductor light emitting device comprising:
    n-side electrode,
    p-side electrode,
    An n-type nitride semiconductor layer having a nonpolar or semipolar surface,
    A p-type nitride semiconductor layer electrically connected to the p-side electrode, and an active layer sandwiched between the n-type nitride semiconductor layer and the p-type nitride semiconductor layer, wherein
    The n-side electrode comprises an aluminum portion,
    The aluminum portion is in contact with the surface of the n-type nitride semiconductor layer,
    The concentration of nitrogen atoms on the surface of the n-type nitride semiconductor layer in contact with the aluminum portion is higher than the concentration of gallium atoms on the surface of the n-type nitride semiconductor layer in contact with the aluminum portion.
  2.  請求項1に記載の窒化物半導体発光素子であって、
     前記アルミニウム部分は、アルミニウムのみからなる。
    The nitride semiconductor light emitting device according to claim 1,
    The aluminum portion is made of only aluminum.
  3.  請求項1に記載の窒化物半導体発光素子であって、
     前記アルミニウム部分は、前記n型窒化物半導体層と平行な層状を有する。
    The nitride semiconductor light emitting device according to claim 1,
    The aluminum portion has a layer shape parallel to the n-type nitride semiconductor layer.
  4.  請求項2に記載の窒化物半導体発光素子であって、
     前記アルミニウム部分は、前記n型窒化物半導体層と平行な層状を有する。
    The nitride semiconductor light emitting device according to claim 2,
    The aluminum portion has a layer shape parallel to the n-type nitride semiconductor layer.
  5.  請求項1に記載の窒化物半導体発光素子であって、
     複数の前記アルミニウム部分が設けられている。
    The nitride semiconductor light emitting device according to claim 1,
    A plurality of the aluminum portions are provided.
  6.  請求項1に記載の窒化物半導体発光素子であって、
     前記アルミニウム部分と接しているn型窒化物半導体層の表面は、ガリウムの空孔を有する。
    The nitride semiconductor light emitting device according to claim 1,
    The surface of the n-type nitride semiconductor layer in contact with the aluminum portion has gallium vacancies.
  7.  請求項1に記載の窒化物半導体発光素子であって、
     前記アルミニウム部分と接しているn型窒化物半導体層の表面領域は、10nm以上且つ150nm以下の厚さを有する。
    The nitride semiconductor light emitting device according to claim 1,
    The surface region of the n-type nitride semiconductor layer in contact with the aluminum portion has a thickness of 10 nm or more and 150 nm or less.
  8.  請求項1に記載の窒化物半導体発光素子であって、
     前記n型窒化物半導体層は、m面の表面を有する。
    The nitride semiconductor light emitting device according to claim 1,
    The n-type nitride semiconductor layer has an m-plane surface.
  9.  請求項1に記載の窒化物半導体発光素子であって、
     前記アルミニウム部分と接しているn型窒化物半導体層の表面は、前記アルミニウム部分と接していないn型窒化物半導体層の部分よりも低いキャリア密度を有する。
    The nitride semiconductor light emitting device according to claim 1,
    The surface of the n-type nitride semiconductor layer that is in contact with the aluminum portion has a lower carrier density than the portion of the n-type nitride semiconductor layer that is not in contact with the aluminum portion.
  10.  窒化物半導体積層構造であって、以下を具備する:
     n側電極、及び
     非極性面又は半極性面の表面を有するn型窒化物半導体層、ここで、
     n側電極は、アルミニウム部分を具備し、
     前記アルミニウム部分は、n型窒化物半導体層の表面と接しており、
     前記アルミニウム部分と接しているn型窒化物半導体層の表面における窒素原子の濃度は、前記アルミニウム部分と接しているn型窒化物半導体層の表面におけるガリウム原子の濃度よりも高い。
    A nitride semiconductor multilayer structure comprising:
    an n-type nitride semiconductor layer having an n-side electrode and a nonpolar or semipolar surface, wherein
    The n-side electrode comprises an aluminum portion,
    The aluminum portion is in contact with the surface of the n-type nitride semiconductor layer,
    The concentration of nitrogen atoms on the surface of the n-type nitride semiconductor layer in contact with the aluminum portion is higher than the concentration of gallium atoms on the surface of the n-type nitride semiconductor layer in contact with the aluminum portion.
  11.  請求項10に記載の窒化物半導体積層構造であって、
     前記アルミニウム部分は、アルミニウムのみからなる。
    The nitride semiconductor multilayer structure according to claim 10,
    The aluminum portion is made of only aluminum.
  12.  請求項10に記載の窒化物半導体積層構造であって、
     前記アルミニウム部分は、前記n型窒化物半導体層と平行な層状を有する。
    The nitride semiconductor multilayer structure according to claim 10,
    The aluminum portion has a layer shape parallel to the n-type nitride semiconductor layer.
  13.  請求項11に記載の窒化物半導体積層構造であって、
     前記アルミニウム部分は、前記n型窒化物半導体層と平行な層状を有する。
    The nitride semiconductor multilayer structure according to claim 11,
    The aluminum portion has a layer shape parallel to the n-type nitride semiconductor layer.
  14.  請求項10に記載の窒化物半導体積層構造であって、
     複数の前記アルミニウム部分が設けられている。
    The nitride semiconductor multilayer structure according to claim 10,
    A plurality of the aluminum portions are provided.
  15.  請求項10に記載の窒化物半導体積層構造であって、
     前記アルミニウム部分と接しているn型窒化物半導体層の表面は、ガリウムの空孔を有する。
    The nitride semiconductor multilayer structure according to claim 10,
    The surface of the n-type nitride semiconductor layer in contact with the aluminum portion has gallium vacancies.
  16.  請求項10に記載の窒化物半導体積層構造であって、
     前記アルミニウム部分と接しているn型窒化物半導体層の表面領域は、10nm以上且つ150nm以下の厚さを有する。
    The nitride semiconductor multilayer structure according to claim 10,
    The surface region of the n-type nitride semiconductor layer in contact with the aluminum portion has a thickness of 10 nm or more and 150 nm or less.
  17.  請求項10に記載の窒化物半導体積層構造であって、
     前記n型窒化物半導体層は、m面の表面を有する。
    The nitride semiconductor multilayer structure according to claim 10,
    The n-type nitride semiconductor layer has an m-plane surface.
  18.  請求項10に記載の窒化物半導体積層構造であって、
     前記アルミニウム部分と接しているn型窒化物半導体層の表面は、前記アルミニウム部分と接していないn型窒化物半導体層の部分よりも低いキャリア密度を有する。
    The nitride semiconductor multilayer structure according to claim 10,
    The surface of the n-type nitride semiconductor layer that is in contact with the aluminum portion has a lower carrier density than the portion of the n-type nitride semiconductor layer that is not in contact with the aluminum portion.
  19.  窒化物半導体積層構造を製造する方法であって、以下の工程を具備する:
     (a)非極性面又は半極性面の表面を有するn型窒化物半導体層の表面を酸素プラズマで照射する工程、
     (b)工程(a)において酸素プラズマで照射された表面を酸に接触させる工程、及び
     (c)工程(b)において酸に接触された表面に、アルミニウム部分を形成する工程。
    A method for manufacturing a nitride semiconductor multilayer structure comprising the following steps:
    (A) irradiating the surface of the n-type nitride semiconductor layer having a nonpolar or semipolar surface with oxygen plasma;
    (B) a step of bringing the surface irradiated with oxygen plasma in step (a) into contact with an acid; and (c) a step of forming an aluminum portion on the surface in contact with the acid in step (b).
  20.  請求項19に記載の方法であって、
     前記アルミニウム部分は、アルミニウムのみからなる。
    20. The method according to claim 19, comprising
    The aluminum portion is made of only aluminum.
  21.  請求項19に記載の方法であって、
     前記アルミニウム部分は、前記n型窒化物半導体層と平行な層状を有する。
    20. The method according to claim 19, comprising
    The aluminum portion has a layer shape parallel to the n-type nitride semiconductor layer.
  22.  請求項20に記載の方法であって、
     前記アルミニウム部分は、前記n型窒化物半導体層と平行な層状を有する。
    The method of claim 20, comprising:
    The aluminum portion has a layer shape parallel to the n-type nitride semiconductor layer.
  23.  請求項19に記載の方法であって、
     複数の前記アルミニウム部分が設けられている。
    20. The method according to claim 19, comprising
    A plurality of the aluminum portions are provided.
  24.  請求項19に記載の方法であって、
     前記アルミニウム部分と接しているn型窒化物半導体層の表面は、ガリウムの空孔を有する。
    20. The method according to claim 19, comprising
    The surface of the n-type nitride semiconductor layer in contact with the aluminum portion has gallium vacancies.
  25.  請求項19に記載の方法であって、
     前記アルミニウム部分と接しているn型窒化物半導体層の表面領域は、10nm以上且つ150nm以下の厚さを有する。
    20. The method according to claim 19, comprising
    The surface region of the n-type nitride semiconductor layer in contact with the aluminum portion has a thickness of 10 nm or more and 150 nm or less.
  26.  請求項19に記載の方法であって、
     前記n型窒化物半導体層は、m面の表面を有する。
    20. The method according to claim 19, comprising
    The n-type nitride semiconductor layer has an m-plane surface.
PCT/JP2013/001120 2012-03-07 2013-02-26 Nitride semiconductor laminate structure, nitride semiconductor light emitting element provided with nitride semiconductor laminate structure, and method for producing nitride semiconductor laminate structure WO2013132783A1 (en)

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JP2021129014A (en) * 2020-02-13 2021-09-02 株式会社デンソー Method for manufacturing nitride semiconductor device

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JP2015038968A (en) * 2013-07-19 2015-02-26 パナソニックIpマネジメント株式会社 Nitride semiconductor light emitting element and manufacturing method thereof
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