JPS6362326A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6362326A JPS6362326A JP20814686A JP20814686A JPS6362326A JP S6362326 A JPS6362326 A JP S6362326A JP 20814686 A JP20814686 A JP 20814686A JP 20814686 A JP20814686 A JP 20814686A JP S6362326 A JPS6362326 A JP S6362326A
- Authority
- JP
- Japan
- Prior art keywords
- polysilicon film
- film
- impurity
- polysilicon
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 12
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 50
- 229920005591 polysilicon Polymers 0.000 claims abstract description 50
- 239000012535 impurity Substances 0.000 claims abstract description 28
- 238000000034 method Methods 0.000 claims abstract description 25
- 238000001312 dry etching Methods 0.000 claims abstract description 5
- 238000010438 heat treatment Methods 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 5
- 238000001035 drying Methods 0.000 claims 1
- 229920005989 resin Polymers 0.000 abstract description 11
- 239000011347 resin Substances 0.000 abstract description 10
- 238000001020 plasma etching Methods 0.000 abstract description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052710 silicon Inorganic materials 0.000 abstract description 3
- 239000010703 silicon Substances 0.000 abstract description 3
- 239000000758 substrate Substances 0.000 abstract description 3
- 238000000137 annealing Methods 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- KZNMRPQBBZBTSW-UHFFFAOYSA-N [Au]=O Chemical compound [Au]=O KZNMRPQBBZBTSW-UHFFFAOYSA-N 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910001922 gold oxide Inorganic materials 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 238000007665 sagging Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製造方法に関し、特にポリシリコ
ン膜をステップ状にドライエツチングするための半導体
装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device by dry etching a polysilicon film in steps.
ポリシリコン＋ｌｌｉを抵抗として用いる場合の加工方
法として、例えば、反応性イオンエツチング（ＲＩＥ）
方法が知られている。従来のかかる半導体装置の製造方
法の一例について、第２図を参照して説明する。As a processing method when using polysilicon+lli as a resistor, for example, reactive ion etching (RIE)
method is known. An example of a conventional method for manufacturing such a semiconductor device will be described with reference to FIG.
まず、第２図（＆）のように、酸化膜２の形成されたシ
リコン基板１上にポリシリコンＡＩ！３を、ＣＶＤ法又
はＰＶＤ法を用いて形成する。First, as shown in FIG. 2 (&), polysilicon AI! 3 is formed using a CVD method or a PVD method.
次に１第２図の）のように、ポリシリコン膜３の抵抗率
を下げるために、イオン注入法を用いて不純物（例えば
ボロン、リン等）ｔポリシリコン膜３の表面（参照番号
４の部分）に注入する。次に、第２図（Ｃ）のように、
樹脂＠６を、抵抗として残す部分のみに選択的く形成し
た後、反応性イオンエツチング法を用いて、樹脂膜６ｔ
−マスクにしてポリシリコン膜３を選択的に除去する。Next, in order to lower the resistivity of the polysilicon film 3, impurities (e.g., boron, phosphorus, etc.) are added to the surface of the polysilicon film 3 (reference number 4) as shown in Figure 2). part). Next, as shown in Figure 2 (C),
After selectively forming the resin @6 only on the portion to be left as a resistor, the resin film 6t is etched using a reactive ion etching method.
- Selectively remove polysilicon film 3 using a mask.
次に１第２図（ｄ）のように、樹脂膜６′ｆ：除去した
後、ＣＶＤ法などを用いて酸化ａｎ成長しポリシリコン
族３（参照番号４の部分を含む）を覆う。最後に、９０
０℃以上の高温度でアニールすることによシ、第２図（
ｅ）に示すように、はぼ均一に不純物がドーピングされ
たポリシリコン膜５が得られる。Next, as shown in FIG. 2(d), after removing the resin film 6'f, an oxide film is grown using CVD or the like to cover the polysilicon group 3 (including the portion designated by reference number 4). Finally, 90
By annealing at a high temperature of 0°C or higher,
As shown in e), a polysilicon film 5 doped with impurities is obtained almost uniformly.
上述した従来の半導体装置の製造方法においては、不純
物をイオン注入したポリシリコン膜３を反応性イオンエ
ツチングすると、そのエツチング断面がくの字形になっ
てしまうため、酸化膜７を成長してポリシリコンＨＱ３
に覆うと、酸化膜７の断面形状８がオーバーハング状に
なってしまう。In the conventional semiconductor device manufacturing method described above, when the polysilicon film 3 into which impurities have been ion-implanted is subjected to reactive ion etching, the etched cross section becomes dogleg-shaped.
If the oxide film 7 is covered with an overhang, the cross-sectional shape 8 of the oxide film 7 will become overhang-like.
その結果、後の電極形成工程に於いてメタル膜などがこ
の段差部に残ってしまい、この段差がｔ＆間に位置して
いる場合は電極ショートになってしまい、また、残った
メタル膜がはがれてしまって外観不良を誘発してしまう
という欠点がある。As a result, in the subsequent electrode formation process, metal films, etc. remain on this step, and if this step is located between t&, an electrode short circuit may occur, and the remaining metal film may peel off. This has the disadvantage that it may cause a poor appearance.
一方、オーバハング形状をなくすためにドライエツチン
グを行う前にポリシリコン膜３を熱処理する方法も考え
られている。その方法について、第３図を参照して説明
する。On the other hand, a method has also been considered in which the polysilicon film 3 is heat treated before dry etching in order to eliminate the overhang shape. The method will be explained with reference to FIG.
まず、第３図（ａ）のように、酸化Ｍ２の形成されたシ
リコン基板１上にポリシリコン膜３を、ＣＶＤ法又はＰ
ＶＤ法を用いて形成する。次に、第３図０）の、よりに
、イオン注入法を用いて不純物をポリシリコン３の表面
に注入する。次に、第３図（Ｃ）のように、例えば９５
０℃〜１０００℃の比較的高温度で熱処理を行うことに
よって不純物全ポリシリコンｍ３中に拡散させてほぼ均
一な不純物を含んだポリシリコンｊ１ｇ５ｔ−得る。次
に、第３図（４のように、樹脂膜６をマスクとしてポリ
シリコン膜５を、反応性イオンエツチング法を用いて加
工する。次に、第３図（６）のように、樹脂膜６を除去
した後、酸化膜７を成長しポリシリコン膜５を覆う。First, as shown in FIG. 3(a), a polysilicon film 3 is deposited on a silicon substrate 1 on which oxide M2 is formed using a CVD method or a polysilicon film 3.
It is formed using the VD method. Next, as shown in FIG. 30), impurities are implanted into the surface of polysilicon 3 using the ion implantation method. Next, as shown in FIG. 3(C), for example, 95
By performing heat treatment at a relatively high temperature of 0 DEG C. to 1000 DEG C., impurities are diffused into the entire polysilicon m3 to obtain polysilicon j1g5t- containing substantially uniform impurities. Next, as shown in FIG. 3 (4), the polysilicon film 5 is processed using the reactive ion etching method using the resin film 6 as a mask. Next, as shown in FIG. 3 (6), the polysilicon film 5 is etched. After removing the polysilicon film 6, an oxide film 7 is grown to cover the polysilicon film 5.
しかし乍ら、このようにして得られたポリシリコン膜５
のエツチング断面形状はオーバハング状になっていない
が、段差が大きいため、覆った酸化膜７の断面形状９が
垂直又はタレオーバハング状になってしまって、やはシ
同様の不良を誘発する欠点がある。However, the polysilicon film 5 obtained in this way
Although the cross-sectional shape of etching does not have an overhang shape, since the step is large, the cross-sectional shape 9 of the covered oxide film 7 becomes a vertical or sagging overhang shape, which has the disadvantage of inducing defects similar to those of . be.
本発明の半導体装置の製造方法は、ポリシリコン狡の上
層部のみに不純物を添加する工程と、前記不純物が前記
ポリシリコン膜の下層部に拡散しないように熱処理を行
う工程と、前記熱処理をされた前記ポリシリコンＮをド
ライエッチングにより選択的に除去する１橘と含有して
いる。The method for manufacturing a semiconductor device of the present invention includes a step of adding an impurity only to the upper layer of the polysilicon film, a step of performing heat treatment to prevent the impurity from diffusing into the lower layer of the polysilicon film, and a step of adding an impurity to the lower layer of the polysilicon film. The polysilicon N is selectively removed by dry etching.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例を説明するための工程順の縦
断面図である。FIG. 1 is a vertical cross-sectional view of the process order for explaining one embodiment of the present invention.
まず、第１図（ａ）のように、［化膜２の形成されたシ
リコン基板ｌ上にポリシリコン族３を、ＣＶＤ法又はＰ
ＶＤ法を用いて形成する。次に、第１図（ｂ）のように
、イオン注入法を用いて不純物（例えばボロン、リン等
）をポリシリコン膜３の表面（参照番号４０部分）Ｋ注
入する。次に、第１図（ｃ）のように、イオン注入され
た不純物が拡散しＫくい温度、６００℃〜８００℃に於
いて熱処理を行う。First, as shown in FIG.
It is formed using the VD method. Next, as shown in FIG. 1(b), impurities (for example, boron, phosphorus, etc.) are implanted into the surface (reference number 40) of the polysilicon film 3 using an ion implantation method. Next, as shown in FIG. 1(c), heat treatment is performed at a temperature of 600 DEG C. to 800 DEG C., at which the ion-implanted impurities diffuse.
この熱処理の方法としては炉型アニールあるいはランプ
アニールを用いてもかまわない。より高温であっても、
不純物が拡散してしまわないような短時間であればよい
。この熱処理を行いポリシリコン膜３の参照番号４の部
分の不純物を活性化させることによシ、不純物のないポ
リシリコン膜３の層と不純物かドーピングされたポリシ
リコン膜５の層との２つの層に分ける。次に、第１図（
ｄ）のように、樹脂膜６を、抵抗として残す部分のみに
選択的に形成した後、反応性イオンエツチング法を用い
て、樹脂膜６ｔ−マスクにしてポリシリコン膜ａ、５ｔ
−選択的に除去する。As a method for this heat treatment, furnace annealing or lamp annealing may be used. Even at higher temperatures,
It is sufficient that the time is short enough to prevent impurities from diffusing. By performing this heat treatment and activating the impurities in the portion of the polysilicon film 3 with reference number 4, two layers are formed: a layer of the polysilicon film 3 without impurities and a layer of the polysilicon film 5 doped with impurities. Divide into layers. Next, Figure 1 (
As shown in d), after selectively forming the resin film 6 only on the portion to be left as a resistor, using the reactive ion etching method, the polysilicon films a and 5t are etched using the resin film 6t as a mask.
-Selective removal.
この時、反応性イオンエツチングのエツチング条件とし
て、不純物がドーピングされたポリシリコン膜５とポリ
シリコン膜３とのエツチング速度比が２以上得られる条
件でエツチングする。例えば、真空度が比較的悪い条件
８０ｍＴｏｒｒ以上に於いてＣＣ１ａと０２ の混合
ガス全周いてエツチングする。次に、第１図（ｅ）のよ
うに、樹脂膜６を除去した後、ＣＶＤ法などを用いて酸
化膜７金成長しポリシリコン膜３，５を覆い、最後に高
温度（９００℃以上）に於いてアニールすることによシ
はぼ均一に不純物がドーピングされたポリシリコン膜５
を得る。At this time, the etching conditions for the reactive ion etching are such that the etching rate ratio between the polysilicon film 5 doped with impurities and the polysilicon film 3 is 2 or more. For example, under relatively poor vacuum conditions of 80 mTorr or more, a mixed gas of CC1a and 02 is etched all around. Next, as shown in FIG. 1(e), after removing the resin film 6, a gold oxide film 7 is grown using a CVD method or the like to cover the polysilicon films 3 and 5, and finally at a high temperature (over 900°C). ) The polysilicon film 5 is almost uniformly doped with impurities by annealing in
get.
以上説明したように本発明によれば、安定してポリシリ
コン膜ｔｌ−２段にエツチングすることができるので、
例えば第１図（ｅ）に示すように、酸化膜７の断面形状
１０が非常によくなシ、後の電極形成工程に於いてメタ
ル残シの発生しない半導体装置が得られるという効果が
ある。As explained above, according to the present invention, the polysilicon film tl-2 can be etched stably.
For example, as shown in FIG. 1(e), if the cross-sectional shape 10 of the oxide film 7 is very good, it is possible to obtain a semiconductor device in which no metal residue is generated in the subsequent electrode forming process.
第１図（ＩＩＬ）〜（ｅ）は、本発明の一実施例を説明
するための工程順の縦断面図、
第２図（ａ）〜（ｅ）ならびに第３図（〜〜（＝）は、
従来の半導体装置の製造方法の二つの例のそれぞれを説
明するための工程順の縦断面図である。
１・・・・・・シリコン基板、２・・・・・・酸化膜、
３・５・・・・・・ポリシリコン膜、６・・・・・・樹
脂膜、７・・・・・・酸化膜、８・９・１０・・・・・
・酸化膜の断面形状。
、＼
代理人 弁理士 内 原 晋
′ｆＪＩ 図
万Ｚ図FIGS. 1(IIL) to (e) are vertical sectional views in the order of steps for explaining one embodiment of the present invention, FIGS. 2(a) to (e), and FIGS. teeth,
FIG. 2 is a vertical cross-sectional view showing the order of steps for explaining two examples of a conventional method for manufacturing a semiconductor device. 1... Silicon substrate, 2... Oxide film,
3.5...Polysilicon film, 6...Resin film, 7...Oxide film, 8.9.10...
・Cross-sectional shape of oxide film. ,＼ Agent Patent Attorney Susumu Uchihara'fJI
Claims (4)
工程と、前記不純物が前記ポリシリコン膜の下層部に拡
散しないように熱処理を行う工程と、前記熱処理をされ
た前記ポリシリコン膜をドライエッチングにより選択的
に除去する工程とを有することを特徴とする半導体装置
の製造方法。(1) A process of adding impurities only to the upper layer of the polysilicon film, a process of performing heat treatment to prevent the impurities from diffusing into the lower layer of the polysilicon film, and drying the polysilicon film that has been subjected to the heat treatment. 1. A method of manufacturing a semiconductor device, comprising the step of selectively removing by etching.
した特許請求の範囲第１項記載の半導体装置の製造方法
。(2) The method for manufacturing a semiconductor device according to claim 1, wherein the heat treatment is performed at a temperature of 600°C to 800°C.
しない短時間で前記熱処理を行うようにした特許請求の
範囲第１項記載の半導体装置の製造方法。(3) The method of manufacturing a semiconductor device according to claim 1, wherein the heat treatment is performed in a short time so that the impurities do not diffuse into the lower layer of the polysilicon film.
しない前記ポリシリコン膜とのエッチング速度比が２以
上得られる条件で前記ドライエッチングを行うようにし
た特許請求の範囲第１項記載の半導体装置の製造方法。(4) The semiconductor device according to claim 1, wherein the dry etching is performed under conditions that provide an etching rate ratio of 2 or more between the polysilicon film to which the impurity is added and the polysilicon film to which the impurity is not added. manufacturing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20814686A JPS6362326A (en) | 1986-09-03 | 1986-09-03 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20814686A JPS6362326A (en) | 1986-09-03 | 1986-09-03 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6362326A true JPS6362326A (en) | 1988-03-18 |
Family
ID=16551397
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20814686A Pending JPS6362326A (en) | 1986-09-03 | 1986-09-03 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6362326A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03281115A (en) * | 1990-03-30 | 1991-12-11 | Mitsubishi Materials Corp | Throw-away type cutting tool |
| JPH0512027U (en) * | 1991-06-07 | 1993-02-19 | 三菱マテリアル株式会社 | Throw-away side cutter |
| US5393682A (en) * | 1993-12-13 | 1995-02-28 | Taiwan Semiconductor Manufacturing Company | Method of making tapered poly profile for TFT device manufacturing |
| JP2011215404A (en) * | 2010-03-31 | 2011-10-27 | Toppan Printing Co Ltd | Photo mask blank and method for manufacturing the same |
-
1986
- 1986-09-03 JP JP20814686A patent/JPS6362326A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03281115A (en) * | 1990-03-30 | 1991-12-11 | Mitsubishi Materials Corp | Throw-away type cutting tool |
| JPH0512027U (en) * | 1991-06-07 | 1993-02-19 | 三菱マテリアル株式会社 | Throw-away side cutter |
| US5393682A (en) * | 1993-12-13 | 1995-02-28 | Taiwan Semiconductor Manufacturing Company | Method of making tapered poly profile for TFT device manufacturing |
| JP2011215404A (en) * | 2010-03-31 | 2011-10-27 | Toppan Printing Co Ltd | Photo mask blank and method for manufacturing the same |
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