JPS60111466A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To eliminate the need for allowance on the alignment of a photograph, and to increase the density of a bipolar IC while minimizing a stepped section in the surface by determining the positional relationship of the boring of diffusion windows for isolation, a sinker and a base through one-time photographic treatment. CONSTITUTION:An silicon oxide film (SiO2) and an silicon nitride film (SiN) are formed on the surface of a wafer 1, to which a buried layer 2 and an epitaxial layer 3 are formed, in a stratiform manner in succession, and other nitride films and the oxide film are removed while leaving the nitride films in an isolation region, a sinker region and a base region forming zone. The surfaces from which the nitride films are removed are oxidized selectively to shape thick oxide films. Photographic treatment is executed, SiN on an isolation-region forming surface and a sinker-region surface is removed, and the isolation region 4 and the sinker region 5 are formed. Likewise, the nitride film on the base zone is removed, and a base region 6 is formed and an emitter region 7 is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing semiconductor devices such as monolithic bipolar ICs, and particularly relates to an optimal method for forming base regions, isolation regions, and sinker regions suitable for miniaturization and high density. The present invention aims to improve the overall characteristics of the device, and also to reduce the difference in surface level of the surface protective film, etc., thereby improving quality, yield, etc. This will be explained below using the drawings. Figure 1 is a schematic process diagram showing the conventional manufacturing method of this type of bipolar IC transistor. An example of a semiconductor substrate in which an N layer 3 serving as a collector region is formed using Al) is shown. Next, a silicon oxide film Sin is formed on the entire surface of the woofer 3, a window is opened for forming an isolation region, and a P-type impurity (boron) is deposited from this window. (b) Next to the figure, a silicon oxide film (SiOy) for a diffusion mask is newly formed on at least the exposed P surface, and after opening a window for forming a sinker region, an n-phosphorus impurity (phosphorus) is deposited. do. (01
Next, a diffusion process is performed to form an isolation region 4 and a sinker region 5 (in order to lower the collector resistance, a high concentration n-type region connecting the buried layer and the Si surface is formed. In other words, the N layer 3 is replaced with P
Form islands of N layer 3 separated by . (Fig. d1, after photo processing, normal base and emitter diffusion is performed on the island to form a base region 6 and an emitter region 7, and then a protective film 9 (phosphor glass, etc.) is formed, contact patterning, and wiring patterning. and complete the transistor. (
Fig. e) and Fig. (f) show a partially enlarged view of the structure (the buried layer 2 and sinker region 5 are omitted in the figure). The dotted lines in the figure indicate the woofer 1 (separation layer 4) and the collector region. 3 (buried layer 2, sinker region 5) and base region 6 when a reverse bias voltage is applied, respectively. When the depletion layer comes into contact between the woofer 1 and the base, so-called punch-through occurs and breaks down. In other words, according to the conventional method, since the separation (corresponding to the substrate), sinker, and base diffusion window photos are taken independently, an error occurs due to the alignment accuracy of the left and right photos (as shown in figure f1).
HA) (usually 2-3 mm). That is, an unbalance in breakdown voltage occurs inside the element, and this breakdown voltage is determined by a narrow portion of the depletion layer, which has a major drawback of causing a drop in breakdown voltage. On the other hand, in order to eliminate the above-mentioned drawbacks and ensure the specified withstand voltage, it is necessary to give the pattern enough leeway, but as mentioned above, if there are only 4 photo alignments each for embedding, sinker, separation, and base, there is not enough leeway. Nearly 10m is required.

This is a major cause of hindering the increase in the density of bipolar ICs. Furthermore, in the above method, an oxide film is added every time a photograph is taken, resulting in extremely large differences in level.

As a result, metallization tends to cause disconnections, which reduces yield and reliability.

The present invention solves the above-mentioned drawbacks by determining the positional relationship of the separation, sinker, and base diffusion window openings in a single photo process, thereby eliminating the need for alignment margins for photos and making it possible to achieve high density bipolar ICs. The purpose of this invention is to provide a method of making it possible to reduce the surface level difference and minimizing the level difference on the surface.

The present invention includes (a) a step of sequentially laminating a silicon oxide film and a silicon nitride film on one surface of a semiconductor substrate;

(b) A step of leaving the silicon nitride film on the two or more diffusion region formation areas of the semiconductor substrate and removing the other silicon nitride film or the silicon nitride film and the silicon oxide film.

(c) forming a silicon oxide film on the surface of the semiconductor substrate from which the silicon nitride film has been removed;

b) removing the silicon nitride film and silicon oxide film on one diffusion region forming area of the semiconductor substrate;

A step of diffusing impurities from the exposed surface to form a first diffusion region.

(e) After forming a silicon oxide film on the diffusion region (first) surface of the semiconductor substrate, remove the silicon nitride film and silicon oxide film on other diffusion region formation areas, and diffuse impurities from the exposed surface. forming another diffusion region.

It is characterized by including the above G) to (E)).

Examples will be described below. FIG. 2 is a schematic cross-sectional view of each step showing an embodiment of the present invention. First, (1) A semiconductor substrate is prepared which is substantially the same as a conventional substrate in which a wafer 1 is provided with a buried layer 2 and a shrimp layer 3. (Fig. 2a) ■ Next, a silicon oxide film (8i0J) and a silicon nitride film (SiN) are sequentially formed in layers on the wafer surface, and then a nitride film is formed on the isolation region, sinker region, and base region forming area on the wafer surface. Remove the other nitride film (8i N) and oxide film (8io, ), leaving the nitride film (8i N). (8i0. may be left.) Fig. 2 (+)) The removed surface is selectively oxidized to form a thick oxide film (Sin). Figure 2 (
c) ■ Next, photo processing for separation is performed to reduce the 8iN of the separation area forming surface.
For example, plasma etching removes Sin. Figure 2(d). The alignment margin for the photos at this time is +
d) The distance should be within the range of distances B and B' in the figure.

(2) Next, using the remaining SiN film, 8IO, and film as a mask, boron is deposited in the window-opened separation region by, for example, a vapor phase diffusion method using BNj. FIG. 2(e) Note that 8iN hardly allows boron to pass through, but 8i0. Since BSG has some boron on the surface, this B5G1 is selectively removed (
(e.g., a non-nitrogen-oxygen P-etch solution) and reoxidize.

■ Next, the SIN on the surface of the sinker region was removed using the same method to expose the substrate S1.
N-type impurities are deposited by vapor phase diffusion from Cl2. (
(FIG. 2f) (1) Next, the separation region 4 and sinker region 5 are formed by diffusing the fft layer and the sinker region Kawanami lamination described above. (Fig. 2g) ■ The nitride film on the base area was removed in the same manner as above to form the base area 6, and the emitter area 7 was further formed, contact windows were opened, and wiring patterning was performed to complete the process. .

(Fig. 2h) According to this manufacturing method, the positional relationship of the separation, sinker, and base regions is determined by the accuracy of the initial 8iN film photomask itself, which is about 02 to 05 μm or less. Therefore, there is no need to take a margin.

It is possible to design the depletion layer to the limit of the width determined by the withstand voltage, making it possible to increase the density. Also, for each diffusion, Sj
Selective etching of O, (P2O, BSG) and reoxidation are repeated, and the area that requires contact window opening is 8.
Since the substrate was covered with iN, the structure was such that the substrate was pushed up, and the oxide film was thin. As a result, there are advantages in that the entire surface is smooth with few steps, and contact windows can be easily opened. Incidentally, when the conventional separation and base distance (f-A in Fig. 1), which was designed to be 25 μm, was changed to 20 μm, the yield decreased significantly in the conventional method, but on the contrary, the yield improved in Kempo. It was confirmed that the decrease in yield in the conventional method was due to a decrease in breakdown voltage due to punch-through of the depletion layer, and the improvement in yield in the single method was due to a smoother surface and a reduction in AI wiring defects.

In the above example, an example was explained in which each region was formed through a normal deposition and diffusion process using a silicon oxide film and a nitride film as a diffusion mask, but it could also be performed using an ion implanter. can. However, in this case, it is preferable to use an oxide film and a resist as a diffusion mask, implant boron or phosphorus, and perform heat treatment if necessary.

As is clear from the above explanation, according to the present invention, self-alignment of each region can be achieved within the accuracy of one photo processing, so that the characteristics of each unit element are uniform, the overall characteristics of the element are improved, and the overall characteristics of the element are improved. It has great practical effects, such as improved yield.

[Brief explanation of drawings]

Figures 1 (a) to (f) are cross-sectional views showing conventional examples by process, Q
- Figures 2 (, j to (h) are cross-sectional views showing one embodiment of the present invention by process. In the figure, 1 is a semiconductor woofer, 12 is a buried layer, 3 is an epitaxial growth layer, and 4 is a separated layer. 5 is a sinker region, 6 is a base region. 7 is an emitter region, Sin is a silicon oxide film, SiN
is a silicon nitride film. Patent applicant Shindengen Kogyo Co., Ltd. 10- Kusa Toguchi

Claims (2)

[Claims] (1) (a) Step of sequentially laminating a silicon oxide film and a silicon nitride film on one surface of a semiconductor substrate. (b) A step of leaving the silicon nitride film on the two or more diffusion region formation areas of the semiconductor substrate and removing the other silicon nitride film or the silicon nitride film and the silicon oxide film. (c) forming a silicon oxide film on the surface of the semiconductor substrate from which the silicon nitride film has been removed; b) removing the silicon nitride film and the silicon oxide film on the one diffusion region formation area of the semiconductor substrate and diffusing impurities from the exposed surface to form a first diffusion region; (e) After forming a silicon oxide film on the diffusion region (first) surface of the semiconductor substrate, remove the silicon nitride film and silicon oxide film on other diffusion region formation areas, and diffuse impurities from the surface that has been sprayed out. to form another diffusion region. A method of manufacturing a semiconductor device including the above (a) to (e). (2) The method for manufacturing a semiconductor device according to claim (1), wherein the diffusion region forming area is a base region, an isolation region, or a base region, an isolation region, and a sinker region.