JPS5884443A - Manufacture of semiconductor ic - Google Patents

Abstract

PURPOSE:To unnecessitate a fine resist film pattern for a conventional base region formation resulting in the nearly complete elimination of defects of emitter collector short circuits, by patterning the large and simple resist film pattern in the earlier process before the formation of element isolation region. CONSTITUTION:After forming an n<+> type buried layer 12 on a p type Si substrate 11, an n type epitaxial layer 13 is grown. Next, the resist film 14 is patterned on the grown epitaxial layer 13, with it as a mask, P ions are implanted in high density from the upper surface, and succeedingly it is applied to a heat treatment resulting in the formation of an n<+> type region 15. The dosage is approx. 10<13>-10<14>/cm<2>, and this region occupies a wide region including the forming region for element isolation region and serves as a collector connection layer. The depth is set to approx. 2[mum]. Next, caustic potash (KoH) solution is used for etching it into a V-groove form, thereafter an SiO2 film 16 is formed on the internal surface, and the inside is filled with a polycrystalline Si 17 resulting in the formation of a V-groove element isolation region 18.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor integrated circuit (IC), and particularly to a novel method for forming a collector contact region and a space region.

It is well known that forming a V-groove-shaped inter-element isolation band provides insulation isolation and has the advantage of reducing parasitic capacitance, and is widely used. A conventional manufacturing method for forming a V-groove separation band and forming a Bybov type semiconductor device will be described. A schematic process sequence diagram is shown in FIGS. 1 to 8.

That is, as shown in FIG.
Form n small buried layers 2 on top, and n! ! Y shrimp! Kishay
After growing the layer 8, ① groove-shaped etching grooves are formed, and the inner surface thereof is filled with polycrystalline silicon 5 through a silicon dioxide (Si, O8) film 4 to form ③ groove-shaped separation zones 6. As shown in FIG. 2, a resist film 7 is patterned on the upper surface thereof, boron ions are implanted, and a p-type base region 8 is formed by heat treatment. Next, as shown in FIG. 8, an n-type emitter region 9 and an n+ type collector contact region 10 are formed using the same lithography technique.

However, recently, memory cells such as #KRAM have become highly integrated, and memory cells such as #KRAM are formed with high density, resulting in many pattern defects. For example, in the first manufacturing process, if the resist film 7 is patterned and the resist film pattern remains in the paste region 8, boron ions will not be implanted there, and then the emitter region 9 and the resist film pattern will remain in the paste region 8. If a collector contact region IO is formed, an emitter-collector short circuit will occur. Figure 4 illustrates this, and is an example of an emitter-collector short circuit where only the dotted circular part in Figure 8 is shown.By the way, if such an emitter-collector short circuit occurs, it will be a fatal defect in the IC and will cause it to malfunction. or the emitter-collector leakage current increases. The present invention is aimed at eliminating the occurrence of such defects.
The feature is that after growing an epitaxial layer of the opposite conductivity type on an 81 substrate of one conductivity type, a high concentration impurity layer of the opposite conductivity type is implanted or diffused into the region including the isolation band formation region to form a collector connection layer. The present invention proposes a manufacturing method that includes a step of forming a V-groove-shaped isolation band between elements, and then injecting or diffusing impurities of one conductivity type over the entire surface to form a space region, as shown in the drawings below. An example will be described in more detail with reference to .

6 to 8 show step-by-step sectional views of the manufacturing method according to the present invention. First, as shown in FIG.
After forming the n-type buried layer 12 on the substrate 11, an n-type epitaxial layer 18 is grown. The n-type epitaxial layer has a thickness of 2 to 3 [μm], but on the buried layer 12,
High-temperature growth causes creeping and diffusion. Next, a resist film 14 is grown on top of the epitaxial μ layer 13 grown in this manner.
Using this as a mask, phosphorus ions are implanted from the upper surface at a high concentration, followed by heat treatment to form the n-type region 15. The dose amount is about 10<13> to 10<1 >C, and the region occupies a wide area including the isolation band formation region and becomes a collector connection layer. and the depth is 2
Make it about [μ shoulder] level.

Next, as shown in FIG. 6, a caustic IJ (KoH) solution was used to etch a V-groove shape, and then 8108 was etched on the inner surface.
A film 16 is generated, the inside is filled with polycrystalline silicon 17,
(2) The groove-shaped inter-element isolation zone 18 is formed by a known forming method similar to the conventional method. In addition, this inter-element separation band is formed in the n-type region 16 as described above, but it is done by partially removing the n-type region 15, which has a relatively large pattern, and reducing the size of the collector connection layer. It is intended for high density.

Next, as shown in FIG. 7, boron ions are implanted into the entire surface from the top surface, followed by heat treatment to form a film with a thickness of 5000-6000.
A p-type base region 19 is formed. In that case, since the n-type region 15 is formed in a highly doped layer, the p-type implanted region 15 is
The type boron is canceled out, and it becomes an n-type region, which is internally connected to the n-type epitaxial layer 3 (collector region), but since the surface is exposed, it functions as a collector connection layer.

Next, as shown in FIG. 8, phosphorus ions are implanted using a resist film (not shown) to form an n+ type emitter region 20, but at the same time, the collector contact region is implanted as in the conventional method. 21 is also formed in the collector connection layer lb. This is for the purpose of reducing contact resistance. Note that the depth of these emitter regions 20 and collector contact regions 21 is 8,000 to 4,000 depths.

As is clear from the manufacturing method of the above embodiments, the present invention is a method in which a large and simple pattern of the resist film 14 is pattern-jung in an initial step before forming an isolation zone, and a total of 9 highly accurate patterns are formed. However, the conventional fine resist film 7 pattern for forming the pace region becomes unnecessary. Therefore.

It is possible to almost eliminate defects such as bow vines and collector short circuits.

That is, in the present invention, the occurrence of defects can be prevented by omitting the photo process for forming the paste.
In the process of forming grooves, ■ a protrusion is formed on the groove, and this protrusion is removed by ■ contacting after groove formation.) Scratch the mask at the stage of alignment at the time of Ig exposure, and remove unwanted areas. It is necessary to avoid the photo process for forming the paste after forming the V-groove, which would result in opening a window. Similarly, it is possible to form the n-type region 15 after forming the groove, but this should be avoided for the reasons mentioned above.

Therefore, the present invention provides an I
In the manufacturing method of C, it goes without saying that similar results can be obtained even if a pattern is formed that does not include the entire area of the separation zone between the quality elements, but only a part of it.

[Brief explanation of drawings]

1 to 8 are sectional views in the order of the conventional manufacturing process, FIG. 4 is a sectional view showing the problems thereof, and FIGS. 5 to 8 are sectional views in the order of the manufacturing process according to the present invention. In the figure, 1.11 is a p-type S1 substrate, 2 and 12 are n+ type buried layers, 3 and 13 are n-type epitaxial layers, 6°18 is a V-groove isolation zone between elements, 7.14 is a resist film, and 8 , 19 is p
A mold base region, 9.20 an emitter region, 10.21 a collector contact region, and 15 a collector connection layer. 21st! 1st 4th v! 1 Figure 5 Figure 7 Figure 8

Claims (1)

[Claims] ■In a method of manufacturing a semiconductor integrated circuit having a groove-shaped isolation band between elements, after growing an epitaxial μ layer of a y-conductivity type on a -conductivity mVycon substrate, a region containing an isolation band formation region is provided with an opposite conductivity. By implanting or diffusing high-concentration impurities,
It should be noted that the process includes the steps of forming a collector connection layer, and then forming a groove-shaped inter-element isolation zone, and then injecting or diffusing impurities of one conductivity type into the entire surface to form a space region. Features: A method for manufacturing semiconductor integrated circuits.