JPS6211504B2 - - Google Patents
Info
- Publication number
- JPS6211504B2 JPS6211504B2 JP53142373A JP14237378A JPS6211504B2 JP S6211504 B2 JPS6211504 B2 JP S6211504B2 JP 53142373 A JP53142373 A JP 53142373A JP 14237378 A JP14237378 A JP 14237378A JP S6211504 B2 JPS6211504 B2 JP S6211504B2
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- conductivity type
- semiconductor substrate
- layer
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000000758 substrate Substances 0.000 claims description 8
- 239000004065 semiconductor Substances 0.000 claims description 7
- 238000000034 method Methods 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 239000012535 impurity Substances 0.000 claims description 2
- 230000001590 oxidative effect Effects 0.000 claims 1
- 229910052796 boron Inorganic materials 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- -1 boron ions Chemical class 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000010301 surface-oxidation reaction Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Formation Of Insulating Films (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Recrystallisation Techniques (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Element Separation (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法に関し、詳しく
は、セルフアライン（自己整合）によつて、バイ
ポーラ集積回路（IC）の埋込層段付けと、分離
酸化膜下のチヤンネルストツパーのイオン打込み
を容易に、歩留りよく行なう製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and more particularly, the present invention relates to a method for manufacturing a semiconductor device. The present invention relates to a manufacturing method for easily performing ion implantation of a stopper with good yield.
第１図は本発明の一実施例を示す工程図であ
る。 FIG. 1 is a process diagram showing an embodiment of the present invention.
ｐ型のSi基板１の表面の所望領域に、酸化膜あ
るいはレジスト膜をマスクにしてｎ型の高濃度領
域２を拡散あるいはイオン打込みによつて形成す
る（第１図ａ）。イオン打込みの場合はドーズ量
は、１×1015cm-2〜５×1016cm-2の範囲、拡散の
場合は表面濃度は１×1019cm-3以上とすることが
適当である。n+層２を形成後900℃以下の低温で
表面酸化を行なう。たとえば800℃で60分間水蒸
気中で酸化すると、n+領域２上には約3000Åの
酸化膜３、それ以外の部分（p-基板上）には約
300Åの酸化膜４が形成される。この高濃層２と
低濃度層１上の酸化膜形成速度の差は酸化温度が
低い程大きいが実用上は、700〜900℃程度が適当
である。酸化膜形成後の断面は第１図ｂのように
なる。次いで、酸化膜４を介して基板１の表面領
域へホウ素を１×1013〜２×1014cm-2だけイオン
打込みを行なう。このようにすると、第１図ｃに
示すように酸化膜４の下の基板１の表面領域に薄
いｐ型層５が形成される。一方高濃度ｎ型埋込層
２は厚い酸化膜３によつて覆われているので、ｎ
型埋込層２の表面にはホウ素の打込みがなされな
い。むろん、ホウ素打込層５の形成にはレジスト
マスクを用いてもよいが、用いない方がセルフア
ライン効果で歩留が向上する。ホウ素の打込後、
表面の酸化膜を３，４をすべて除去し、基板１上
にエピタキシヤル層６を生成させる。このように
すると、第１図ｄに示すような断面構造が得ら
れ、この後に、ホウ素打込み層５の上のエピタキ
シヤル層６の中に分離酸化膜を形成することによ
り、ホウ素打込み層５がチヤンネルストツパーと
して有効に働く。 An n-type high concentration region 2 is formed in a desired region of the surface of a p-type Si substrate 1 by diffusion or ion implantation using an oxide film or a resist film as a mask (FIG. 1a). In the case of ion implantation, it is appropriate that the dose be in the range of 1×10 15 cm -2 to 5×10 16 cm -2 , and in the case of diffusion, the surface concentration should be 1×10 19 cm -3 or more. After forming the n + layer 2, surface oxidation is performed at a low temperature of 900°C or less. For example , when oxidized in water vapor at 800°C for 60 minutes, an oxide film 3 of approximately 3000 Å is formed on the n + region 2, and approximately
An oxide film 4 of 300 Å is formed. The difference in the rate of oxide film formation on the high concentration layer 2 and the low concentration layer 1 increases as the oxidation temperature decreases, but for practical purposes, approximately 700 to 900°C is appropriate. The cross section after the oxide film is formed is as shown in FIG. 1b. Next, boron ions are implanted into the surface region of the substrate 1 through the oxide film 4 at an amount of 1×10 13 to 2×10 14 cm −2 . In this way, a thin p-type layer 5 is formed in the surface region of the substrate 1 under the oxide film 4, as shown in FIG. 1c. On the other hand, since the high concentration n-type buried layer 2 is covered with a thick oxide film 3, the n-type buried layer 2 is covered with a thick oxide film 3.
No boron is implanted into the surface of the mold embedding layer 2. Of course, a resist mask may be used to form the boron implanted layer 5, but the self-alignment effect improves the yield by not using a resist mask. After implanting boron,
All of the oxide films 3 and 4 on the surface are removed, and an epitaxial layer 6 is formed on the substrate 1. In this way, a cross-sectional structure as shown in FIG. Works effectively as a channel stopper.
以上のような素子製造プロセスを用いることに
より、酸化段付け工程、チヤンネルストツパー打
込み用ホト工程など数工程が短縮され、従来に比
較して歩留の向上がいちじるしい。 By using the above-described device manufacturing process, several steps such as the oxidation stage step and the channel stopper implantation photo step can be shortened, resulting in a significant improvement in yield compared to the conventional method.
また、後に続く工程のために、エピタキシヤル
層６の表面にマスク合わせ用の段７を設ける必要
があり、従来は、マスクを用いるホトエツチング
によつて、段７を形成していた。 Further, for subsequent steps, it is necessary to provide a step 7 for mask alignment on the surface of the epitaxial layer 6, and conventionally, the step 7 has been formed by photoetching using a mask.
しかし、このような従来の方法は、単に煩雑で
あるばかりでなく、マスク合わせの際のずれのた
め、正確に形成する困難であつた。 However, such conventional methods are not only complicated, but also difficult to form accurately due to misalignment during mask alignment.
一方、本発明によれば、上記のように、不純物
濃度の相異によつて酸化速度が大きく異なること
を利用し、セルフアラインによつて段付けが行な
われるので、工程が簡単であるばかりでなく、極
めて正確に段付けを行なうことが可能である。 On the other hand, according to the present invention, as mentioned above, the step is performed by self-alignment by taking advantage of the fact that the oxidation rate differs greatly depending on the impurity concentration, so the process is not only simple but also Therefore, it is possible to perform extremely accurate step-up.
第１図は本発明の実施例を示す工程図である。
１…高濃度領域、２…埋込み層、３，４…酸化
膜。
FIG. 1 is a process diagram showing an embodiment of the present invention. 1... High concentration region, 2... Buried layer, 3, 4... Oxide film.
Claims (1)
濃度の第２導電型領域を形成する工程。 (2) 上記半導体基板表面を酸化し、上記第２導電
型領域上には厚く、他の部分上には薄く、酸化
膜を形成する工程。 (3) 上記薄い酸化膜が被着されてある部分の上記
半導体基板表面に第１導電形不純物をドープす
る工程。 (4) 上記酸化膜を除去する工程。 (5) 上記半導体基板表面上にエピタキシヤル層を
生長させる工程。[Claims] 1. A method for manufacturing a semiconductor device including the following steps. (1) A step of forming a highly concentrated second conductivity type region in a desired portion of the surface of the first conductivity type semiconductor substrate. (2) A step of oxidizing the surface of the semiconductor substrate to form a thick oxide film on the second conductivity type region and a thin oxide film on other parts. (3) doping a first conductivity type impurity into a portion of the semiconductor substrate surface where the thin oxide film is deposited; (4) Step of removing the above oxide film. (5) A step of growing an epitaxial layer on the surface of the semiconductor substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14237378A JPS5568650A (en) | 1978-11-20 | 1978-11-20 | Manufacturing method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14237378A JPS5568650A (en) | 1978-11-20 | 1978-11-20 | Manufacturing method of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5568650A JPS5568650A (en) | 1980-05-23 |
| JPS6211504B2 true JPS6211504B2 (en) | 1987-03-12 |
Family
ID=15313863
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14237378A Granted JPS5568650A (en) | 1978-11-20 | 1978-11-20 | Manufacturing method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5568650A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2567281Y2 (en) * | 1991-09-25 | 1998-04-02 | 株式会社ニフコ | Glue window molding equipment |
| US5795809A (en) * | 1995-05-25 | 1998-08-18 | Advanced Micro Devices, Inc. | Semiconductor wafer fabrication process including gettering utilizing a combined oxidation technique |
-
1978
- 1978-11-20 JP JP14237378A patent/JPS5568650A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5568650A (en) | 1980-05-23 |
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