JPS59161834A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS59161834A
JPS59161834A JP58035863A JP3586383A JPS59161834A JP S59161834 A JPS59161834 A JP S59161834A JP 58035863 A JP58035863 A JP 58035863A JP 3586383 A JP3586383 A JP 3586383A JP S59161834 A JPS59161834 A JP S59161834A
Authority
JP
Japan
Prior art keywords
film
guard ring
groove
substrate
metal silicide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58035863A
Other languages
Japanese (ja)
Inventor
Norio Murakami
則夫 村上
Hiroyuki Tamura
浩之 田村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP58035863A priority Critical patent/JPS59161834A/en
Publication of JPS59161834A publication Critical patent/JPS59161834A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

PURPOSE:To eliminate the mulfunctions such as latch-up and the like by a method wherein, when a guard ring is provided on a semiconductor element, said guard ring is formed using a metal silicide, thereby enabling to form a low resistance guard ring deep in the semiconductor element substrate. CONSTITUTION:An SiO2 film 2 is coated on an Si substrate 1, an aperture is provided corresponding to a guard ring region 3, and a deep groove entering into the substrate 1 is provided by performing a reactive ion etching. Then, a metal silicide film 5 is coated on the whole surface including the groove 4 by performing a sputtering method, and the film 2 and the groove 4 are disconnected. Subsequently, a resist film 6 is to be coated. At this time, a thick resist film 6' is generated on the silicide film 5 which is buried in the groove 4 due to characteristics of the resist. Then, an etching is performed on the whole surface using O2 plasma, the film 5 located on the film 2 is removed, the film 6' is reduced in thickness, the film 2 is removed using an HF solution, the film 6' is removed using O2 plasma, and the deep silicide guard ring 5 is left in the substrate 1.

Description

【発明の詳細な説明】 （技術分野） この発明は、ガードリングを有する半導体装置の製造方
法に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a method of manufacturing a semiconductor device having a guard ring.

（従来技術） 最近、ＣＯＤや０ＭＯ８などの半導体装置においては、
素子周辺に、高濃度拡散層によるガードリングを設けて
いる。これは、ＣＯＤの場合はフィールド周辺からの電
荷の注入金、また０ＭＯ８の場合はラッチアップによる
素子の動作不良を防止する対策が必須条件であることに
よる。(Prior art) Recently, in semiconductor devices such as COD and 0MO8,
A guard ring made of a highly concentrated diffusion layer is provided around the element. This is because in the case of COD, it is essential to take measures to prevent device malfunction due to charge injection from the periphery of the field, and in case of 0MO8, due to latch-up.

これらの半導体装置に必要なガードリングは、従来、高
濃度の不純物拡散によって笑現されている。しかし、そ
の方法では、■拡散）ｔＭｉｃ半導体丞板内に深く形成
することが望ましく、そのためには長時間の熱処理が必
要であるが、熱処理を長時間行うと、拡散層の横方向へ
の拡がりが増加して集積化が不可能になる、００ＭＯ８
の場合は不純物のＰ型、Ｎ型の両者を狭い分ける必要が
ある、■拡散層自体の抵抗を光分下げることが望ましい
が、それが半導体ゆえにできなかった、などの欠点があ
る。The guard rings necessary for these semiconductor devices have conventionally been achieved by diffusion of impurities at high concentrations. However, in this method, (diffusion) it is desirable to form the tMic deep within the semiconductor board, which requires a long heat treatment, but if the heat treatment is performed for a long time, the diffusion layer will spread laterally. increases, making integration impossible, 00MO8
In the case of (1), it is necessary to narrowly separate both P-type and N-type impurities, and (2) it is desirable to lower the resistance of the diffusion layer itself by an amount of light, but this cannot be done because it is a semiconductor.

（発明の目的） この発明は上記の点に鑑みなされたもので０、従米の欠
点を解決できる半導体装置の製造方法を提供することを
目的とする。(Object of the Invention) The present invention has been made in view of the above points, and an object of the present invention is to provide a method for manufacturing a semiconductor device that can solve the disadvantages of conventional methods.

（実施例） 以下この発明の一実施例を第１図ないし第６図を８照し
て説明する。(Embodiment) An embodiment of the present invention will be described below with reference to FIGS. 1 to 6.

第１図において、１は半導体基板であシ、まず、この基
板１０表面にシリコン酸化膜２を熱酸化によシ形成する
。次に、ホトリングラフィとエツチングにニジ、ガード
リング領域３のシリコン酸化膜２を除去し開口させる。In FIG. 1, 1 is a semiconductor substrate, and first, a silicon oxide film 2 is formed on the surface of this substrate 10 by thermal oxidation. Next, the silicon oxide film 2 in the guard ring region 3 is removed by photolithography and etching to form an opening.

しかる後、シリコン酸化Ｍ２をマスクとして半導体基板
１のリアクティブイオンエツチング（ＲＩＢ）を行うこ
とによシ、前記シリコン酸化膜２の除去部（開口部）に
対応する基板１の表面部に第２図に示すように溝４（深
さ数ミクロン）を形成する。Thereafter, by performing reactive ion etching (RIB) on the semiconductor substrate 1 using the silicon oxide M2 as a mask, a second etching layer is formed on the surface portion of the substrate 1 corresponding to the removed portion (opening) of the silicon oxide film 2. As shown in the figure, grooves 4 (several microns deep) are formed.

次に、スパッタ法などにニジ金属シリサイド膜を付着さ
せる。すると、第３図に示すように、金属シリサイド膜
５は前記溝４内および前記シリコン酸化膜２上に付着す
るが、この時、溝４内の金属シリサイド膜５が完全に溝
内に没するように、さらにその金属シリサイド膜５がシ
リコン酸化膜２で断ち切られてシリコン酸化膜２上の金
属シリサイド膜５と完全に分離されるように適当に金属
シリサイド膜５の厚さとシリコン酸化膜２の厚さを制御
してやる。Next, a rainbow metal silicide film is deposited by sputtering or the like. Then, as shown in FIG. 3, the metal silicide film 5 adheres inside the trench 4 and on the silicon oxide film 2, but at this time, the metal silicide film 5 inside the trench 4 completely sinks into the trench. Further, the thickness of the metal silicide film 5 and the thickness of the silicon oxide film 2 are adjusted appropriately so that the metal silicide film 5 is cut off by the silicon oxide film 2 and completely separated from the metal silicide film 5 on the silicon oxide film 2. I'll control the thickness.

次に、第４図に示すように、レノスト膜６を全面コーテ
ィングする。すると、レジｉト膜６の性質に基づいてレ
ジスト膜厚に差異が生じ、ガードリング領域形成のため
に設けた前記縛４内の金属シリサイド膜５上には厚いレ
ジスト族６′が形成される。Next, as shown in FIG. 4, the entire surface is coated with a Renost film 6. Then, a difference occurs in the resist film thickness based on the properties of the resist film 6, and a thick resist film 6' is formed on the metal silicide film 5 in the constraint 4 provided for forming the guard ring region. .

次に、シリコン酸化膜２上の雀属シリサイド膜５が露出
するまで、レジスト膜６ｔ−０，プラズマに工りエツチ
ングする。これによりレノスト膜６は、第５図に示すよ
うに前記厚いレジスト膜６′のみが一部薄くなって残る
。Next, the resist film 6t-0 is etched using plasma until the silicide film 5 on the silicon oxide film 2 is exposed. As a result, only the thick resist film 6' of the Lenost film 6 remains partially thin, as shown in FIG.

次いで、シリコン酸化膜２上の金属シリサイド膜５をＣ
Ｆ、十〇、プラズマによシ除去する。続いて薄いＨＦ浴
液によりシリコン酸化膜２を、さらにＯ２プラズマによ
り厚いレジスト族６′を除去する。Next, the metal silicide film 5 on the silicon oxide film 2 is coated with C.
F. 10. Remove by plasma. Subsequently, the silicon oxide film 2 is removed using a thin HF bath and the thick resist group 6' is removed using O2 plasma.

すると、第６図に示すように半導体基板１内に金属ノリ
サイド膜５が没してｆ−ドリング領域を形成した構造が
得られる。Then, as shown in FIG. 6, a structure in which the metal nolicide film 5 sinks into the semiconductor substrate 1 to form an f-dring region is obtained.

次に、このガードリング領域で囲まれた領域Ａ内に能動
領域を形成する。この時、金属シリサイド膜５は商温熱
処理に光分耐えるため、通常の半導体製造工程を１史用
することも可能となる。Next, an active region is formed within region A surrounded by this guard ring region. At this time, since the metal silicide film 5 can withstand the commercial temperature heat treatment, it is possible to use the normal semiconductor manufacturing process for one cycle.

なお、以上の方法において、半導体基板１の表面に形成
される酸化膜はＣＶＤ酸化膜であってもよい。Note that in the above method, the oxide film formed on the surface of the semiconductor substrate 1 may be a CVD oxide film.

（発明の効果） 以上の一実施例ηλら明らかなように、この発明の製造
方法では、全域シリサイド膜を便用じて半導体素子のガ
ードリングを形成する。したがって、［Ｆ］半導体基板
内深くまでガードリング層を形成できる、■低抵抗のガ
ードリングである、■素子の築積化が可能である、■熱
処理に通常の半導体プロセスを使用できる、■半導体の
Ｐ型、Ｎ型を考える必蒙がないなどの利点がおる。(Effects of the Invention) As is clear from the above embodiment ηλ, in the manufacturing method of the present invention, the guard ring of the semiconductor element is formed by conveniently using the entire area silicide film. Therefore, [F] the guard ring layer can be formed deep into the semiconductor substrate, ■ it is a guard ring with low resistance, ■ it is possible to build up devices, ■ it is possible to use normal semiconductor processes for heat treatment, ■ semiconductor It has the advantage that there is no need to consider P-type and N-type.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図ないし第６図はこの発明の半導体装置の製造方法
の一実施例１ｃ説明するための断面図である。 ｌ・・・半導体基板、２・・・シリコン酸化膜、３・・
・ガードリング領域、４・・・溝、５・・・金属クリサ
イド膜、６・・・レジスト膜、６′・・・厚いレジスト
膜。 特許出願人　　沖電気工業株式会社1 to 6 are cross-sectional views for explaining an embodiment 1c of the method for manufacturing a semiconductor device according to the present invention. l...Semiconductor substrate, 2...Silicon oxide film, 3...
- Guard ring region, 4... Groove, 5... Metal creicide film, 6... Resist film, 6'... Thick resist film. Patent applicant Oki Electric Industry Co., Ltd.

Claims (1)

【特許請求の範囲】[Claims] 半導体基板の表面に酸化膜を形成した後、その酸化膜を
ガードリング形成領域のみエツチング除去する工程と、
その酸化膜の除去部に対応する前記基板表面部に溝を形
成する工程と、その溝および前記ば化膜上に分離して金
属シリサイド膜を形成する工程と、全面にレジスト膜を
塗布した後、そのレジスト膜の膜厚差を利用して、前記
溝の金属シリサイド膜上にのみレジスト膜を残す工程と
、前記酸化股上の金属シリサイド膜を除去する工程と、
その後、残存酸化膜および残存レジスト膜を除去する工
程とを具備してなる半導体装置の製造方法。After forming an oxide film on the surface of the semiconductor substrate, etching away the oxide film only in the guard ring forming area;
A step of forming a groove on the surface of the substrate corresponding to the portion from which the oxide film is removed, a step of forming a metal silicide film separately on the groove and the oxide film, and a step of coating the entire surface with a resist film. , a step of leaving a resist film only on the metal silicide film in the groove by utilizing the difference in film thickness of the resist film, and a step of removing the metal silicide film on the oxidized ridge;
Thereafter, a method of manufacturing a semiconductor device comprises a step of removing a remaining oxide film and a remaining resist film.
JP58035863A 1983-03-07 1983-03-07 Manufacture of semiconductor device Pending JPS59161834A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58035863A JPS59161834A (en) 1983-03-07 1983-03-07 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58035863A JPS59161834A (en) 1983-03-07 1983-03-07 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS59161834A true JPS59161834A (en) 1984-09-12

Family

ID=12453819

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58035863A Pending JPS59161834A (en) 1983-03-07 1983-03-07 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS59161834A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10346312A1 (en) * 2003-10-06 2005-05-04 Infineon Technologies Ag Semiconductor component with series or parallel function elements formed in relatively isolated semiconductor regions defined by insulation structure at least partially formed of a metal/silicide
JP2006086533A (en) * 2004-09-14 2006-03-30 Agere Systems Inc Guard ring for improved consistency

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10346312A1 (en) * 2003-10-06 2005-05-04 Infineon Technologies Ag Semiconductor component with series or parallel function elements formed in relatively isolated semiconductor regions defined by insulation structure at least partially formed of a metal/silicide
DE10346312B4 (en) * 2003-10-06 2015-04-09 Infineon Technologies Ag Semiconductor component with several parallel or serially interconnected functional elements
JP2006086533A (en) * 2004-09-14 2006-03-30 Agere Systems Inc Guard ring for improved consistency
US7253012B2 (en) * 2004-09-14 2007-08-07 Agere Systems, Inc. Guard ring for improved matching
US7407824B2 (en) 2004-09-14 2008-08-05 Agere Systems, Inc. Guard ring for improved matching

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