JPH01173632A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH01173632A JPH01173632A JP62329459A JP32945987A JPH01173632A JP H01173632 A JPH01173632 A JP H01173632A JP 62329459 A JP62329459 A JP 62329459A JP 32945987 A JP32945987 A JP 32945987A JP H01173632 A JPH01173632 A JP H01173632A
- Authority
- JP
- Japan
- Prior art keywords
- film
- oxide film
- oxidation
- pad oxide
- silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 239000004065 semiconductor Substances 0.000 title claims description 9
- 230000003647 oxidation Effects 0.000 claims abstract description 15
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 11
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 11
- 239000010703 silicon Substances 0.000 claims abstract description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 10
- 229920005591 polysilicon Polymers 0.000 claims abstract description 10
- 230000001590 oxidative effect Effects 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 14
- 238000005530 etching Methods 0.000 claims 1
- 241000293849 Cordylanthus Species 0.000 abstract description 7
- 229910052760 oxygen Inorganic materials 0.000 abstract description 6
- 239000001301 oxygen Substances 0.000 abstract description 6
- 150000004767 nitrides Chemical class 0.000 abstract description 4
- 239000013078 crystal Substances 0.000 abstract description 3
- 238000000059 patterning Methods 0.000 abstract description 2
- 238000001039 wet etching Methods 0.000 abstract description 2
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 13
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 13
- 238000002955 isolation Methods 0.000 description 7
- 108091006146 Channels Proteins 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- -1 boron ions Chemical class 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000009545 invasion Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野コ
この発明は高集積化が可能な素子間分離を実現する半導
体装置の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method of manufacturing a semiconductor device that realizes isolation between elements that enables high integration.
［従来の技術］
従来のＭＯ３型半導体装置における選択酸化法による素
子間分離を説明する断面図を第２図（ａ）〜（Ｃ）に示
す。第２図（ａ）において、１はシリコン単結晶半導体
基板であり、２はこの半導体基板１上に形成されたパッ
ド酸化膜、３はパッド酸化膜２の上にＣＶＤ （化学的
気相成長）法により形成された窒化シリコン膜である。[Prior Art] Cross-sectional views illustrating isolation between elements by selective oxidation in a conventional MO3 type semiconductor device are shown in FIGS. 2(a) to 2(C). In FIG. 2(a), 1 is a silicon single crystal semiconductor substrate, 2 is a pad oxide film formed on this semiconductor substrate 1, and 3 is a CVD (chemical vapor deposition) film formed on the pad oxide film 2. This is a silicon nitride film formed by a method.
第２図（ａ）の状態の基板１を第２図（ｂ）に示すよう
にアクティブ領域となる所のみに窒化シリコン膜３を残
し、エツチングする。そして残った窒化シリコン膜３を
マスクとしてボロンのイオン注入によりチャネルストッ
プ層４を形成する。The substrate 1 in the state shown in FIG. 2(a) is etched, leaving the silicon nitride film 3 only in the active region, as shown in FIG. 2(b). Then, using the remaining silicon nitride film 3 as a mask, a channel stop layer 4 is formed by implanting boron ions.
その後、第２図（Ｃ）のようにパターニングされた窒化
シリコン膜３をマスクにして、ウェット酸素雰囲気でシ
リコンを熱酸化し、膜厚３００〜１１０００ｎのフィー
ルド酸化膜５を形成する。なお、１１はアクティブ領域
、１２はフィールド領域である。Thereafter, as shown in FIG. 2C, using the patterned silicon nitride film 3 as a mask, silicon is thermally oxidized in a wet oxygen atmosphere to form a field oxide film 5 having a thickness of 300 to 11,000 nm. Note that 11 is an active area, and 12 is a field area.
［発明が解決しようとする問題点］
しかしながら、上記のような従来の方法で、素子間分離
領域を形成すると、窒化シリコン膜の下に酸化膜が侵入
し、第２図（Ｃ）に示すように、バーズビーク２１と呼
ばれる部分が生じる為、仮に２−のホトマスクを使用し
ても、仕上りフィールド幅は３〜４ＩＪｍにもなってし
まい、微細化に対して大きな障害となる問題があった。[Problems to be Solved by the Invention] However, when forming an isolation region between elements using the conventional method as described above, an oxide film invades under the silicon nitride film, resulting in a problem as shown in FIG. 2(C). Since a portion called a bird's beak 21 is generated, even if a 2-photomask is used, the finished field width will be as much as 3 to 4 IJm, which poses a problem that becomes a major hindrance to miniaturization.
この発明は、上記の問題点を解決するためになされたも
ので、従来の選択酸化法による素子間分離での窒化シリ
コン膜下へのバーズビーク侵入の問題点を除去し、微細
化に有利な半導体装置の製造方法を提供することを目的
とするものである。This invention was made to solve the above problems, and eliminates the problem of bird's beaks penetrating under the silicon nitride film when separating elements using the conventional selective oxidation method. The object of the present invention is to provide a method for manufacturing the device.
［問題点を解決するための手段］
この発明に係る半導体装置の製造方法は、単結晶シリコ
ン基板上にパッド酸化膜、耐酸化膜を形成し、これをバ
ターニングした後、これらの膜をマスクとして、シリコ
ンをウェット酸素雰囲気で熱酸化して、フィールド酸化
膜を形成した後、この一部をエツチングし、次に、全面
にポリシリコン膜を形成し、再度、熱酸化して、フィー
ルド酸化膜を形成するようにしたものである。[Means for Solving the Problems] A method for manufacturing a semiconductor device according to the present invention includes forming a pad oxide film and an oxidation-resistant film on a single crystal silicon substrate, patterning these films, and then masking these films. After thermally oxidizing silicon in a wet oxygen atmosphere to form a field oxide film, a part of this is etched, then a polysilicon film is formed on the entire surface, and thermal oxidation is performed again to form a field oxide film. It is designed to form a
［実施例］
以下、この発明の素子分離形成方法の一実施例を第１図
の■〜■に示す製造工程断面説明図の順にしたがって説
明する。[Example] Hereinafter, an example of the device isolation forming method of the present invention will be described in accordance with the manufacturing process cross-sectional explanatory diagrams shown in FIG.
■ ｌｏｔはシリコン単結晶半導体基板（以下基板と略
称する）であり、まず、この基板１０１を熱酸化して、
その表面上に１００人程程度パッド酸化膜１０２を形成
する。次にそのパッド酸化膜１０２上にＣＶＤ （化学
的気相成長）法などにより、１０００〜２０００人程度
の耐酸化膜程度わち窒化シリコン膜１０３を形成し、さ
らにその上にフォトレジスト膜１０４を形成する。■ Lot is a silicon single-crystal semiconductor substrate (hereinafter referred to as the substrate). First, this substrate 101 is thermally oxidized,
About 100 pad oxide films 102 are formed on the surface thereof. Next, on the pad oxide film 102, an oxidation-resistant film of about 1,000 to 2,000 layers, that is, a silicon nitride film 103, is formed by CVD (chemical vapor deposition), etc., and a photoresist film 104 is further formed on the pad oxide film 102. Form.
■ ■の状態の基板１０１のフォトレジスト膜１０４を
感光させ、アクティブ領域２０１を残し、フィールド領
域２０２のフォトレジスト膜１０４、及び窒化シリコン
膜１０３、及びパッド酸化膜１０２をエツチングし、パ
ターニングされた窒化シリコン膜１０３をマスクとして
、ボロンのイオン注入などによりＰ＋９のチャネル・ス
トップ層１０５を形成する。The photoresist film 104 on the substrate 101 in the state of (2) is exposed to light, the active region 201 is left, the photoresist film 104 in the field region 202, the silicon nitride film 103, and the pad oxide film 102 are etched, and the patterned nitride film 104 is etched. Using the silicon film 103 as a mask, a P+9 channel stop layer 105 is formed by boron ion implantation or the like.
■ ■の工程でパターニングされた窒化シリコン膜１０
３をマスクにして、ウェット酸素雰囲気でシリコンを熱
酸化し、膜厚２０００〜３０００人程度の比較的薄程度
ィールド酸化膜１０８を形成する。■ Silicon nitride film 10 patterned in the process of ■
Using No. 3 as a mask, silicon is thermally oxidized in a wet oxygen atmosphere to form a relatively thin field oxide film 108 having a thickness of about 2,000 to 3,000 layers.
■ ■の工程ののち、このフィールド酸化膜１０ＢをＨ
Ｆ等の溶液を用いて、１０００〜１５００人程度ウェッ
ト・程度チングし、フィールド酸化膜１０Ｂを約半分の
膜厚にするとともに、パッド酸化膜１０２を側面が露出
する様にする。■ After the process of ■, this field oxide film 10B is
Using a solution such as F, the field oxide film 10B is wetted by approximately 1,000 to 1,500 times to reduce the thickness to about half, and the side surfaces of the pad oxide film 102 are exposed.
■ ついで、全面に５００人程程度薄いポリシリコン膜
１０７をＣＶＤ （化学的気相成長）法などにより形成
する。(2) Next, a thin polysilicon film 107 of about 500 layers is formed over the entire surface by CVD (chemical vapor deposition) or the like.
■ ■の状態で再びウェット酸素雰囲気で熱酸化し、５
０００〜１００００人程度のフィールド程度膜１０８を
形成する。■ In the state of ■, thermal oxidation is carried out again in a wet oxygen atmosphere.
A field-sized film 108 of about 000 to 10,000 people is formed.
■ その後、ウェット・エツチングにより、窒化シリコ
ン膜上の酸化膜１０９、及び窒化シリコン膜１０３、及
びパッド酸化膜１０２を除去する。この工程により、ｐ
中型チャネルストップ層１０５の上にバーズビーク２１
（第２図参照）の小さいフィールド酸化膜１０８が形成
されるとともに、アクティブ領域２０１に基板１０１の
下地が露出される。(2) Thereafter, the oxide film 109 on the silicon nitride film, the silicon nitride film 103, and the pad oxide film 102 are removed by wet etching. Through this process, p
Bird's beak 21 on medium-sized channel stop layer 105
A small field oxide film 108 (see FIG. 2) is formed, and the base of the substrate 101 is exposed in the active region 201.
以後の工程は図示しないが、通常の技術を用い、アクテ
ィブ領域２０１にトランジスタを形成し、絶縁膜、配線
、保護膜等を施し、半導体装置の製造工程を完了する。Although subsequent steps are not shown, a transistor is formed in the active region 201 using a conventional technique, and an insulating film, wiring, a protective film, etc. are applied, thereby completing the manufacturing process of the semiconductor device.
なお、上記実施例においては、チャネル・ストップ層は
ｐ中型のものについて説明したが、に型チャネル・スト
ップ層の場合にも同様の方法が適用できることはいうま
でもない。In the above embodiments, the channel stop layer is described as having a p-type medium type, but it goes without saying that the same method can be applied to the case of a p-type channel stop layer.
［発明の効果］
以上のように、この発明の製造方法によれば、フィール
ド酸化を２回に分け、−度に急激な酸化をしないこと、
それによりパッド酸化膜を薄くできること、また、バタ
ーニングされたパッド酸化膜側壁をポリシリコン膜で覆
うために、ポリシリコンが、酸素の拡散防止膜として働
くとともに、ポリシリコン膜を形成しない場合に比して
、少ない時間で、より厚いフィールド酸化膜を形成でき
ることから、従来の選択酸化法で、微細化の大きな障害
となっていたバーズビークの侵入が抑制される。したが
って、この発明は装置の微細化に対して有利な素子間分
離を実現させるものであり、ＭＯ８型高集積回路装置の
製造方法に有効的に適用できる効果がある。[Effects of the Invention] As described above, according to the manufacturing method of the present invention, field oxidation is divided into two steps, and rapid oxidation is not performed twice.
This allows the pad oxide film to be made thinner, and since the sidewalls of the buttered pad oxide film are covered with a polysilicon film, the polysilicon acts as an oxygen diffusion prevention film and is compared to the case where no polysilicon film is formed. As a result, a thicker field oxide film can be formed in less time, and the invasion of bird's beaks, which has been a major obstacle to miniaturization in conventional selective oxidation methods, is suppressed. Therefore, the present invention realizes isolation between elements that is advantageous for miniaturization of devices, and has the effect that it can be effectively applied to a method of manufacturing MO8 type highly integrated circuit devices.
第１図■〜■はこの発明の方法による素子分離形成方法
の一実施例を示す製造工程説明図、第２図（ａ）〜（ｃ
）は従来の方法による素子分離形成方法の説明図である
。
図において、ｌｏｔは基板、１０２はパッド酸化膜、１
０３は窒化シリコン膜、１０４はフォトレジスト膜、１
０５はｐ中型チャネルストップ層、１０６は薄いフィー
ルド酸化膜、１０７はポリシリコン膜、１０８はフィー
ルド酸化膜、１０９はシリコン酸化膜、２０１はアクテ
ィブ領域、２０２はフィールド領域、１は基板、２はパ
ッド酸化膜、３は窒化シリコン膜、４はチャネルストッ
プ層、５はフィールド酸化膜、１１はアクティブ領域、
１２はフィールド領域、２１はバーズビークである。Figures 1 - 2 are manufacturing process explanatory diagrams showing an embodiment of the device isolation forming method according to the method of the present invention, and Figures 2 (a) to (c)
) is an explanatory diagram of a conventional method for forming element isolation. In the figure, lot is a substrate, 102 is a pad oxide film, 1
03 is a silicon nitride film, 104 is a photoresist film, 1
05 is a p medium channel stop layer, 106 is a thin field oxide film, 107 is a polysilicon film, 108 is a field oxide film, 109 is a silicon oxide film, 201 is an active region, 202 is a field region, 1 is a substrate, 2 is a pad oxide film, 3 a silicon nitride film, 4 a channel stop layer, 5 a field oxide film, 11 an active region,
12 is a field area, and 21 is a bird's beak.
Claims (1)
に順次選択的に形成する工程と、上記耐酸化膜をマスク
として熱酸化により前記シリコン基板を酸化してフィー
ルド酸化膜を形成する工程と、このフィールド酸化膜を
上記パッド酸化膜が露出するまでエッチングする工程と
、その後全面にポリシリコン膜を形成する工程と、この
ポリシリコン膜を熱酸化し厚いフィールド酸化膜を形成
する工程とを具備することを特徴とする半導体装置の製
造方法。a step of sequentially selectively forming a pad oxide film and an oxidation-resistant film on the active region on the substrate; a step of oxidizing the silicon substrate by thermal oxidation using the oxidation-resistant film as a mask to form a field oxide film; The method includes a step of etching this field oxide film until the pad oxide film is exposed, a step of forming a polysilicon film on the entire surface after that, and a step of thermally oxidizing the polysilicon film to form a thick field oxide film. A method for manufacturing a semiconductor device, characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62329459A JPH01173632A (en) | 1987-12-28 | 1987-12-28 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62329459A JPH01173632A (en) | 1987-12-28 | 1987-12-28 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01173632A true JPH01173632A (en) | 1989-07-10 |
Family
ID=18221613
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62329459A Pending JPH01173632A (en) | 1987-12-28 | 1987-12-28 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01173632A (en) |
-
1987
- 1987-12-28 JP JP62329459A patent/JPH01173632A/en active Pending
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