JPH04123432A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable formation of flat wiring by cutting grooves in an insulating film to be embedded with a conductive film below the depth of a groove and by etching away the insulating film to the depth of the conductive film. CONSTITUTION:A semiconductor substrate 1 is spread with an SiO2 film 2, and resist is spread over this film and left behind by photo lithography outside schedule for wiring formation. The SiO2 film 2 is etched by RIE to form a groove 3; then, resist is peeled off. After the SiO2 film 2 including the groove 3 is spread with Al 4 by sputtering, the Al 4 is spread with photoresist 5. Under a condition that etching speed of Al 4 is almost equal to that of photoresist 5, RIE is continued until the Al 4 of the region other than the groove 3 disappears. This makes the groove 3 filled with Al 4 to develop about a 0.1mum step between the tops of SiO2 2 and Al 4. The photoresist 5 is peeled off, so as to obtain a flat wiring layer free of the step between the filling Al 4 and the SiO2 film 2.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for forming metal wiring.

(Prior art) As semiconductor devices become smaller and larger, it is important to form interconnections between diffusion skins and metal wiring or metal wiring layers with high reliability through contact holes, which greatly improves the yield and reliability of semiconductor devices. It's starting to have an impact.

FIG. 7 is a cross-sectional view of a process for forming metal wiring in a conventional example.

For example, M is deposited to a thickness of about 500A on the insulator [102] formed on the semiconductor substrate 101. Next, after obtaining the desired resist pattern through a photolithography process, 11 active ion etching (R
Then, the resist is removed (FIG. 7(a)).

Next, on the semiconductor substrate 101, for example, a film of Sin, 102□
An insulating film of about 1 μm thick is deposited by CVD at a temperature of about 300° C. (FIG. 7(b)).

According to the method of forming metal wiring as shown above, when RIFli is applied to the red metal wiring as shown in Fig. 2(a), undercuts are created in the red metal wiring, resulting in a reverse taper shape and thinning of the wiring. There was a problem. Furthermore, as shown in FIG. 7 fb), when forming an 8i0° film on the M wiring by the CVD method, the 8i0° film is formed in an overlapping shape with respect to the N wiring. There was a problem in that a film was formed and cavities 104 (referred to as voids) were created in the Si capillary film, making it impossible to flatten it.

FIG. 8 is a cross-sectional view of a process for forming a conventional pier hole.

A first layer is formed on the insulating film 106 formed on the semiconductor substrate $105.
An M wiring @107 is formed as an N wiring.

Next, an insulating film made of 8i02 film 108 is formed on this semiconductor substrate 105 using the CVD method.

Next, using a resist pattern formed by a photolithography process as a mask, 810. The film 108 is removed by RIE to form a connection hole 109. Next, after removing the resist,
W (tungsten) 110 is deposited in this connection hole 109 by CVD.
(FIG. 8(a)).

In the method for forming a pier hole as described above, it is difficult to stop the selective growth of W on the surface of the Sin film 108, and it is difficult to stop the selective growth of W on the surface of the film 108. If W is formed above the surface of the film 108, the stress is released, so that it spreads outside the connection hole 109, and the W crystals also become granular, making the surface rough. Furthermore, when a resist is applied on this semiconductor substrate 105 and then etched back, Sin and W formed on the surface of the film 108 are removed.
Although it is removed, the roughness of the surface of W exposed in the connection hole 109 does not become small (FIG. 8(b)).

In addition, in order to prevent the surface of W from becoming rough, 8i0. When the selective growth of W is stopped below the surface of the film 108 (FIG. 9(a)), red is then sputtered to a thickness of 1 as the second layer wiring.
When deposited on the order of μm (FIG. 9(b)), this connection hole 10
A protrusion 111 and a deep groove 112 are formed at the 90 step portion. This poses a problem in the reliability of the wiring, and also in that the shape of the insulating film covering the upper layer of the second layer wiring cannot be flattened.

(Problems to be Solved by the Invention) As described above, in the conventional method of forming metal wiring, when performing RIB, there is a problem that undercuts occur in the red, resulting in a reverse tapered shape and thin lines in the wiring. There was a thunderstorm. Further, when forming a SiO film on the M wiring by CVD, an overhanging SiO film is formed on the N wiring, and the SiO film is formed on the N wiring.

There was a problem in that cavities were formed in the film and it could not be flattened.

Nineteenth, in the conventional connection hole forming method, it is difficult to control when selectively filling metal into the connection hole, and it is not possible to completely fill the connection hole with metal and flatten it.
However, if too much metal is deposited above the surface of the film, the stress is released and the grain size of the metal decreases. If metal deposition is stopped below the surface of the film, when the second layer of metal is subsequently formed, protrusions and deep grooves will occur at the step portion of the contact hole, which will leave problems with the reliability of the wiring! There was a problem in that the covering shape of the insulating film on the upper layer of the second layer wiring could not be flattened.

An object of the present invention is to provide a method for manufacturing a semiconductor device that solves these problems.

[Structure of the invention]

(Means for Solving the Problems) The present invention has been made in view of the above circumstances, and the first invention includes a step of forming a groove in an insulating film on a semiconductor substrate, and a depth of the groove. Provided is a method for manufacturing a semiconductor device, comprising the steps of embedding a conductive film below the trench, and etching away the insulating film to the depth of the conductive film buried in the trench.

Further, a second invention includes a step of forming a first wiring metal on a first insulating film on a semiconductor substrate, and a step of forming a second insulating film on the first insulating film and the first wiring metal. a step of forming;
forming a contact hole in the second insulating film on the first wiring metal; burying a second wiring metal in the contact hole below the depth of the contact hole; Provided is a method for manufacturing a semiconductor device, comprising the steps of sputter etching a second insulating film and forming a third wiring metal on the second insulating film and on the contact hole. do.

(Function) As described above, according to the present invention, a groove is formed in an insulating film, a conductive film is buried in this groove to a depth equal to or less than the depth of the groove, and the insulating film is etched away at a depth of 1 of the buried conductive film. By doing so, a flat wiring can be formed. Further, since the wiring is not formed by RIE of metal, there is no undercut in the wiring, resulting in a reverse tapered shape and thinning of the wiring.

Further, since the wiring is formed by RIE of metal and no insulating film is formed around it, the generation of voids can be prevented. Furthermore, since the metal is embedded shallower than the depth of the groove, it is possible to prevent the grain size of the metal from sagging.

(Example) Hereinafter, embodiments of the invention will be described with reference to the drawings.

FIG. 1 is a process sectional view of a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

A Sin film 2 having a thickness of about 1.5 μm is formed on a semiconductor substrate 1 by CVD (FIG. 1(a)).

Next, a resist is formed on the Sin film 2, and a photolithographic method is used to leave the resist in areas other than the area where wiring is to be formed. Next, using this resist as a mask, 5iOx
After etching the JIE 2 to a depth of about 0.5 μm by reactive ion etching (RIE) to form a groove 3, the resist is peeled off (FIG. 1(b)).

Next, after forming A24 with a thickness of about 0.4 μm on the Sin film 2 including the groove 3 by sputtering, this M
7 photoresist 5 is formed on 4 to a thickness of about 1 μm (first
Figure (C)).

Next, RIE is performed under the condition that the etching speeds of At4 and photoresist 5 are approximately equal until At4 in the portion other than the groove 3 is removed. As a result, kt4 is embedded to a depth of 0.4 μm in the groove 3 having a depth of 0.5 μm, and SIO! membrane 2
There will be a level difference of about 0.1 μm between the top of kL4 and the top of kL4. Next, the photoresist 5 is peeled off (
Figure 1(d)).

Next, Sin! Membrane 2 was etched to a thickness of about 0.1 μm using a method II, and A1.4 and 8i0. There is no step difference in the film 20, and a wiring layer with a flat structure can be obtained (FIG. 1(e)).

FIG. 2 is a cross-sectional view of a method for manufacturing a semiconductor device according to a second embodiment of the present invention.

A 5102 film 7 with a thickness of about 1 μm is formed on the semiconductor substrate 6 by the CVD method. Next, red was applied to a thickness of 0 using the sputtering method.
．． 4 μm thick (FIG. 2(a)).

Next, a resist is formed on this M, and a photolithography method is used to leave the resist in the area where wiring is to be formed. Next, use this resist as a mask to RI E LA
After forming the t-wiring 8, the resist is peeled off. Next 5i
An NT film 9 is formed to a thickness of about 1 μm by CVD, and then a resist is formed on this 8 r Os film 9, and the resist is left on the parts other than the At wiring 8 by using a photolithography method. Next, using this resist as a mask, 8i0
．． The film 9 is removed by R1:E to form a contact hole 10 and the M wiring 8 is exposed. Next, tungsten W11□
The contact hole 1θ provided on the M wiring 8 is selectively buried to a depth of about α8 μm by the 6CVD method. Since the depth of the contact hole 10 is approximately 1 μm, the 8i0° film 9 and W
There is a difference 12 of about 0.2 μm from the top of ll (FIG. 2(b)).

Next, when sputter etching is performed, the corners 12 of this difference 12. Since the film 9 is particularly etched, the corners of the film 9 have a chamfered shape (FIG. 2(C)).

Next K, A211. The thickness is approximately 0.4μ by sputtering method.
m is formed (Fig. 2(d)).

According to the method of manufacturing a semiconductor device as described above, M is deposited on the contact hole in the form of a flat film without protrusions or grooves.

FIG. 3 is a sectional view showing another example of the method of forming a groove in the first embodiment of the present invention in the order of steps.

8i0. on the semiconductor substrate 13. A film 14 is formed by a CVD method. Next, this 8i0. A resist 15 is formed on the film 14, and is left in an area where wiring is to be formed using a photolithography method. Here, for example, a positive resist 15 is used.

Positive type resist exhibits hydrophobicity, but it may be exposed to plasma containing fluorine to further increase its hydrophobicity (Figure #I3 (a)
) hmm.

Next, sea urchins were immersed in a solution of hydrosilicic acid (H, SiF,) saturated with 7 Lika (BIO,).
If the equilibrium is shifted using Sin! [An SiO film 16 can be further formed on the film 14.

At this time, since the resist 15 is hydrophobic, 8401M16 is not formed on the resist 15 (FIG. 3(b)).

Next, by peeling off the resist 15, the semiconductor substrate 1
8i0 on 3. Grooves 17 can be formed in the film 16 (FIG. 3(C)).

FIG. 4 is a sectional view showing a method for manufacturing a semiconductor device according to a third embodiment of the present invention in the order of steps.

An S t Os film 19 is formed to a thickness of about 2 μm on the semiconductor substrate 18 by the CVD method. Next, S10! A resist is formed on the film 19, and the resist 15 is placed on the area other than the area where wiring is to be formed using a photolithography method.

Next, using this resist as a mask, SiO,j[19 is etched to a depth of about 1 μm by RIFi to form a groove 2°, and the resist is peeled off. Next, a palladium layer 21t having a thickness of approximately 500λ is formed using a sputtering method (FIG. 4(a)).

Next, after coating the palladium layer 21 with a No. 7 photoresist 22, development is performed to leave the No. 7 photoresist 22 at a depth of about 0.8 μm in the groove 2o (FIG. 4(b)).

Next, by immersing this semiconductor substrate 18 in a mixed solution of nitric acid, hydrochloric acid, and acetic acid, the palladium layer 21' exposed on the Sin 3119 and on the surface of the groove 20 is removed. Next, the photoresist 22 is ashed in plasma and removed (FIG. 4(C)).

Next, copper 23 is selectively embedded only on the palladium layer 21 by immersing the semiconductor substrate 18 in sulfuric acid steel. Here, Sin is about 0 between the upper part of the film 19 and the upper part of the steel 23 wiring.
．． A step difference of 2 μm is generated (FIG. 4(d)).

Next, approximately 2.2 μm of 8105g19 was removed by RIE, and the embedded steel 23 and S10s jl
It is possible to obtain a wiring layer with a flat structure without the step 119 (FIG. 4(e)).

FIG. 5 is a cross-sectional view showing a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention in the order of process S.

8i0. on the semiconductor substrate 24. [25] is formed to a thickness of about 1 μm by the CVD method. Next, a thickness of approximately 50 mm was formed using the sputtering method.
A palladium layer 26 of OA is formed.

Next, a resist is formed on the palladium layer 26, and using photolithography, the resist 2 is applied only to the area where wiring is to be formed.
7 remains (Fig. 5(a)).

Next, the palladium layer 26 exposed on the IBSiOzg 25 is removed by immersing the semiconductor substrate 24 in a mixed solution of nitric acid, hydrochloric acid, and acetic acid (FIG. 5(b)).

Next, by the method shown in FIG. 3, 8i0. An 8i01 film 28 having a thickness of about 1 μm is further formed on the film 25, and then the resist 27 is removed. As a result of the above, the palladium layer 2 on the bottom
A groove 29 where 6 remains is formed (see Fig. 5 (
C)). .

Next, copper 30 is selectively embedded to a depth of 0.6 μm inside this groove 29 by the method shown in FIG.
In order to prevent the oxidation of 0.0, gold 31 with a thickness of about 0.2 μm is coated with copper 30.
It may be selectively formed on top by an electroless plating method. At this time, a step difference of about 0.2 μm is created between the upper part of S IOx ft 28 and the upper part of film 31 (FIG. 5(d)).

Next K, 几IBK! SiO2,l [28 about 0.2 μm
Remove the upper part of the membrane 31 and 810! PN 28
It is possible to obtain a wiring layer with a flat structure without any step on the upper part (FIG. 5(e)).

FIG. 6 is a cross-sectional view showing a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention in the order of steps.

On the semiconductor substrate 32, a thin film 33 of about 2 μm in thickness is formed by CVD. Next 8i0. A resist 34 is formed on the film 33, and a photolithography method is used to leave the resist 34 in areas other than the area where wiring is to be formed. Next (using this resist 34 as a mask, the Sin film 33 is etched to a depth of approximately 1 μm by RIE to form a groove 35. At this time,
Since the resist 34 is exposed to plasma containing fluorine, it becomes sufficiently hydrophobic (FIG. 6(a)).

Next, this semiconductor substrate 32 is immersed in an approximately 0.1% palladium chloride solution at room temperature for approximately 5 minutes to form a Si film 33.
Palladium 36 is formed on the exposed bottom of the groove 35 (FIG. 6(b)).

Next, after washing this semiconductor substrate 32 with water, it is immersed in a sulfuric acid steel solution, and copper 37 can be deposited only on the portions where radium 36 has been deposited (FIG. 6(C)).

Next, remove the resist and use HIE to remove the SiO□ film 33.
3. Embedded copper 37 and 51 by removing
The level difference in the 02 film 33 is eliminated, and a wiring layer with a flat structure can be obtained (FIG. 6(d)).

〔Effect of the invention〕

As described above, according to the present invention, a groove is formed in an insulating film, a conductive film is buried in the groove to a depth below the groove, and the insulating film is removed by etching to the depth of the buried conductive film. A flat wiring can be formed.

In addition, since the wiring is not formed by etching metal, there is no possibility that the wiring will become undercut or tapered, causing the wiring to become thinner.

Furthermore, the process of forming wiring by etching metal and forming insulation and imitations around the wiring can prevent the generation of voids. Furthermore, since the metal is embedded shallower than the depth of the groove, it is possible to prevent the grain size of the metal from sagging.

[Brief explanation of the drawing]

1 is a process cross-sectional view showing a method for manufacturing a semiconductor device according to a first embodiment of the present invention, FIG. 2 is a process cross-sectional view showing a method for manufacturing a semiconductor device according to a second example of the present invention, and FIG. 4 is a process sectional view showing a method for manufacturing a semiconductor device according to a third embodiment of the present invention; FIG. Figure 5 shows the fourth aspect of the present invention.
FIG. 6 is a process cross-sectional view showing a method for manufacturing a semiconductor device according to a fifth embodiment of the present invention. FIG. 7, FIG. 8, and FIG. 1@9 are process cross-sectional views showing a conventional method for manufacturing a semiconductor device. In the figure, 1...semiconductor substrate, 2...s i O! Membrane, 3...
・Groove, 4At, 5... Photoresist, 6... Semiconductor substrate, 7... 5in2 tear, 8... M wiring, 9...
・SiO,M. 10... Contact hole, IL ・=W, 112-
At. 12... difference. Agent Patent Attorney Rule Chika Ken Yuu) Guhehe (b) (C) (d) Figure (a) 1! :I (b) (C) Figure & ■ Go to 10. (e) Figure (a) (b) (C) (d) Figure 5 (e) Figure (b) (a) (b) Figure

Claims (4)

[Claims] (1) A step of forming a groove in an insulating film on a semiconductor substrate, a step of embedding a conductive film in this groove to a depth below the depth of the groove, and etching and removing the insulating film to the depth of the conductive film embedded in the groove. A method for manufacturing a semiconductor device, comprising the steps of: (2) The step of forming the groove includes the step of forming a resist pattern on the first insulating film provided on the semiconductor substrate in the area where the groove is planned to be formed, and the step of forming a resist pattern in a portion other than the resist pattern. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising the steps of: forming an insulating film; and removing the resist pattern. (3) The conductive film consists of two layers, and the step of embedding the conductive film includes a step of forming a first conductive film on the groove and the surface of the insulating film, and a step of forming a resist in the groove below the depth of the groove. a step of embedding, a step of removing the exposed first conductive film, and a step of selectively embedding a second conductive film into the removed portion of the resist after removing the resist. A method for manufacturing a semiconductor device according to claim 1. (4) forming a first wiring metal on the first insulating film on the semiconductor substrate; forming a second insulating film on the first insulating film and the first wiring metal; forming a contact hole in the second insulating film on the first wiring metal; embedding a second wiring metal below the depth of the contact hole; A method for manufacturing a semiconductor device, comprising the steps of sputter etching an insulating film and forming a third wiring metal on the second insulating film and on the contact hole.