JP3071810B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a metal wiring.

(Prior Art) With the miniaturization and large scale of semiconductor devices, it is important to form the interconnection between the diffusion layer and the metal wiring or the metal wiring layer with contact holes with high reliability in the yield and reliability of the semiconductor device. It has been affected.

FIG. 7 is a sectional view showing a conventional process of forming a metal wiring.

Insulating formed on the semiconductor substrate 101 on film 102 ₁ on, for example, A
l is deposited to a thickness of about 8000 mm. Next, after a desired resist pattern is obtained by a photolithography process, the resist pattern is used as a mask by reactive ion etching (RIE method).
1 is processed to form an Al wiring 103, and then the resist is removed (FIG. 7A).

Next, an insulating film made on the semiconductor substrate 101 for example of SiO ₂ film 102 _2, by CVD, about the thickness in the order of 300 ° C. temperature 1μ
m (FIG. 7 (b)).

In the method of forming a metal wiring as described above, the second method
As shown in FIG. 2A, when RIEing Al, there is a problem in that Al is undercut and becomes reverse-tapered, resulting in thinning of the wiring. Also, as shown in FIG.
By law, when forming the SiO ₂ film on the Al wiring, SiO ₂ film is formed on the overhanging manner with respect to the Al wiring, a problem that the cavity 104 (referred to as voids) can not be flattened occur during SiO ₂ film There was a point.

FIG. 8 is a sectional view showing a conventional process of forming a via hole.

An Al wiring 107 is formed as a first layer wiring on an insulating film 106 formed on a semiconductor substrate 105. Next, this semiconductor substrate 1
An insulating film made of the SiO ₂ film 108 is formed on 05 by using the CVD method. Next, using the resist pattern formed by the photolithography step as a mask, the SiO ₂ film 108 is removed by RIE to form a connection hole 109. Next, after removing the resist, W (tungsten) 110 is selectively formed in the connection hole 109 by using the CVD method (FIG. 8A).

In the method of forming a via hole as described above, W
Is difficult to stop at the surface of the SiO ₂ film 108,
When W is formed on the surface of the iO ₂ film 108 or more, the stress is released, so that the W spreads out of the connection hole 109, and the W crystal becomes granular and the surface becomes rough. Further, the semiconductor substrate 105
When etch back is performed after applying resist on top,
Although the W formed on the surface of the SiO ₂ film 108 is removed, the surface roughness of the W exposed in the connection hole 109 is not reduced.
(FIG. 8 (b)).

In the case where the selective growth of W is stopped below the surface of the SiO ₂ film 108 in order to prevent the roughening of the surface of W (FIG. 9A), Al is then sputtered as the second layer wiring. 1μm thick
When the layers are deposited to a certain extent (FIG. 9 (b)), projections 111 and deep grooves 112 are formed at the step portions of the connection holes 109. This leaves a problem in the reliability of the wiring and has a problem that the covering shape of the insulating film in the upper layer of the second wiring cannot be flattened.

(Problems to be Solved by the Invention) As described above, in the conventional method for forming a metal wiring,
When RIE is performed, there is a problem in that Al is undercut to form an inversely tapered shape, resulting in thinning of wiring. Also, further in forming the SiO ₂ film by a CVD method on the Al wiring are SiO ₂ film is formed on the overhang shape with respect to the Al wiring, a problem that a cavity in the SiO ₂ film can not be flattened occur there were.

Further, in the conventional method of forming a contact hole, selectively connect its control is difficult when embedding the metal into the pores, to be planarized completely embedded metal connection hole, SiO ₂
If the metal is deposited too much on the surface of the film, the stress is released and only the particle size of the metal occurs, and if the deposition of the metal is stopped below the surface of the SiO ₂ film, the metal of the second layer is subsequently removed. At the time of formation, a projection or a deep groove is formed at a step portion of the connection hole, leaving a problem in the reliability of the wiring, and also has a problem that the covering shape of the insulating film on the upper layer of the second wiring cannot be flattened. .

An object of the present invention is to provide a method for manufacturing a semiconductor device which solves such a problem.

[Configuration of the invention]

(Means for Solving the Problems) The present invention has been made in view of the above circumstances, and a first invention is a step of forming a groove in an insulating film on a semiconductor substrate,
A method of embedding a conductive film in the groove to a depth equal to or less than the depth of the groove; and a step of etching and removing the insulating film to a depth of the conductive film embedded in the groove. provide.

According to a second aspect of the present invention, there is provided a step of forming a first wiring metal on a first insulating film on a semiconductor substrate, and forming a second insulating film on the first insulating film and the first wiring metal. Forming a contact hole in the second insulating film on the first wiring metal, embedding a second wiring metal in the contact hole at a depth equal to or less than the depth of the contact hole, A semiconductor device comprising: a step of sputter etching the second insulating film above the contact hole; and a step of forming a third wiring metal on the second insulating film and the contact hole. And a method for producing the same.

(Function) According to the present invention, as described above, a groove is formed in an insulating film, a conductive film is buried in the groove at a depth equal to or less than the depth of the groove, and the insulating film is etched and removed to a depth of the buried conductive film. Thereby, a wiring having a flat shape can be formed. Further, since the wiring is not formed by RIE of the metal, the wiring is undercut and has an inversely tapered shape, and the wiring does not become thin. Further, since a wiring is formed by RIE of a metal and an insulating film is not formed around the wiring, generation of voids can be prevented. Further, since the metal is buried shallower than the depth of the groove, it is possible to prevent the metal particle from dripping.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a process sectional view of a method of manufacturing a semiconductor device according to a first embodiment of the present invention.

An SiO ₂ film 2 is formed on a semiconductor substrate 1 to a thickness of about 1.5 μm by a CVD method.
m (FIG. 1A).

Next, a resist is formed on the SiO ₂ film 2, and the resist is left by using a photolithography method in a region other than a region where a wiring is to be formed. Next, using the resist as a mask, the SiO ₂ film 2 is subjected to a reactive ion etching (RIE) to a depth of about 0.5.
After the groove 3 is formed by the etching of μm, the resist is removed (FIG. 1B).

Next, on the SiO ₂ film 2 including the groove 3 by using the sputtering method
After forming Al4 to a thickness of about 0.4 μm, subsequently, a photoresist 5 is formed to a thickness of about 1 μm on the Al4 (FIG. 1C).

Next, under the condition that the etching rates of Al and the photoresist 5 are almost equal, RIE is performed until Al4 in portions other than the groove 3 is eliminated.
Perform As a result, a depth of 0.4 μm in the groove 3 having a depth of 0.5 μm
Al4 is buried up to m, and a step of about 0.1 μm occurs between the uppermost portion of the SiO ₂ film 2 and the uppermost portion of Al4. Next, the photoresist 5 is stripped (FIG. 1 (d)).

Next, the SiO ₂ film 2 is etched by RIE to a thickness of about 0.1 μm to eliminate the step between the buried Al 4 and the SiO ₂ film 2 and obtain a wiring layer having a flat structure (FIG. 1E).

FIG. 2 is a sectional view showing a method of manufacturing a semiconductor device according to a second embodiment of the present invention in the order of steps.

An SiO ₂ film 7 is formed on a semiconductor substrate 6 to a thickness of about 1 by a CVD method.
μm is formed. Next, by sputtering, Al
m (FIG. 2A).

Next, a resist is formed on this Al, and the resist is left in the area where the wiring is to be formed by using a photolithography method.
Next, using this resist as a mask, RIE is performed on Al to form an Al wiring 8.
After forming the resist, the resist is peeled off. Next, the SiO ₂ film 9 is
A thickness of about 1 μm is formed by the D method, a resist is subsequently formed on the SiO ₂ film 9, and a photolithography method is used to form a resist.
The resist is left in portions other than on the Al wiring 8. Next, using this resist as a mask, the SiO ₂ film 9 is removed by RIE to form a contact hole 10 to expose the Al wiring. Then tungsten (W) 11 embedded in a depth of about 0.8μm selectively in the contact hole 10 provided on the Al wiring 8 by ₁ by CVD. Because the depth of the contact hole 10 is about 1 [mu] m, and the SiO ₂ film 9
The W11 ₁ at the top are present cross-sectional difference 12 of about 0.2 [mu] m (FIG. 2 (b)).

Then, since the corner portion 12 ₁ of the sectional difference 12 is particularly etched when performing sputter etching, a shape in which corner portions of the SiO ₂ film 9 is chamfered (FIG. 2 (c)).

Next, Al11 by ₂ sputtering to about 0.4μm formation thickness (Fig. 2 (d)).

According to the method of manufacturing a semiconductor device as described above, Al on the contact hole is deposited as a flat film having no protrusions or grooves.

FIG. 3 is a sectional view showing another embodiment of the method of forming a groove in the order of steps in the first embodiment of the present invention.

An SiO ₂ film 14 is formed on a semiconductor substrate 13 by a CVD method.
Next, a resist 15 is formed on the SiO ₂ film 14, and the resist 15 is left in a region where a wiring is to be formed by using a photolithography method. Here, for example, a positive resist 15 is used. The body type resist shows hydrophobicity, but may be exposed to plasma containing fluorine to further increase the hydrophobicity. (FIG. 3 (a)).

Next, silicic hydrofluoric acid (H ₂ SiF ₆₎ solution to a silica (SiO ₂₎ When the'll shifting the equilibrium with Al immersed wafers in a solution of saturated further on SiO ₂ film 14 SiO ₂ film 16 Can be formed. At this time, since the resist 15 is hydrophobic, the SiO ₂ film 16 is not formed on the resist 15 (FIG. 3B).

Next, the semiconductor substrate 13 is removed by removing the resist 15.
A groove 17 can be formed in the upper SiO ₂ film 16 (FIG. 3C).

FIG. 4 is a sectional view showing a method of manufacturing a semiconductor device according to a third embodiment of the present invention in the order of steps.

An SiO ₂ film 19 is formed on a semiconductor substrate 18 to a thickness of about 2 μm by a CVD method.
m. Next, a resist is formed on the SiO ₂ film 19, and the resist is left in a region other than a region where a wiring is to be formed by using a photolithography method. Next, using this resist as a mask,
The O ₂ film 19 is etched by RIE to a depth of about 1 μm to form a groove 20 and the resist is stripped. Next, a palladium layer 21 having a thickness of about 500 ° is formed by sputtering (FIG. 4A).

Next, after applying a photoresist 22 on the palladium layer 21, development is performed and the photoresist 22 is
0.8 μm is left (FIG. 4 (b)).

Next, the palladium layer 21 exposed on the SiO ₂ film 19 and the surface of the groove 20 is removed by immersing the semiconductor substrate 18 in a mixed solution of nitric acid, hydrochloric acid, and acetic acid. Next, the photoresist 22 is ashed in plasma and removed (FIG. 4 (c)).

Next, copper 23 is selectively embedded only on palladium layer 21 by immersing semiconductor substrate 18 in copper sulfate. here
There is a step of about 0.2 μm between the upper part of the SiO ₂ film 19 and the upper part of the copper 23 wiring (FIG. 4D).

Next, the SiO ₂ film 19 is etched away by about 0.2 μm by RIE, so that a step between the embedded copper 23 and the SiO ₂ film 19 is eliminated, and a wiring layer having a flat structure can be obtained (FIG. 4E). .

FIG. 5 is a sectional view showing a method of manufacturing a semiconductor device according to a fourth embodiment of the present invention in the order of steps.

An SiO ₂ film 25 is deposited on a semiconductor substrate 24 to a thickness of about 1 μm by a CVD method.
m. Next, a palladium layer 26 having a thickness of about 500 ° is formed by a sputtering method. Next, a resist is formed on the palladium layer 26, and the resist 27 is left only in the area where the wiring is to be formed by using the photolithography method (FIG. 5A).

Next, the palladium layer 26 exposed on the SiO ₂ film 25 is removed by immersing the semiconductor substrate 24 in a mixed solution of nitric acid, hydrochloric acid, and acetic acid (FIG. 5B).

Next, by the method shown in FIG. 3 to form a SiO ₂ 28 further thickness of about 1μm on the SiO ₂ film 25, followed by resist 27 is removed. The groove 29 in which the palladium layer 26 was left at the bottom
Is formed (FIG. 5 (c)).

Next, the depth shown in FIG.
0.6 μm copper 30 is selectively embedded. Thereafter, gold 31 having a thickness of about 0.2 μm may be selectively formed on copper 30 by electroless plating in order to prevent oxidation of copper 30. At this time, the SiO ₂ film 28
There is a step of about 0.2 μm between the upper part and the upper part of the gold 31 (FIG. 5 (d)).

Next, the SiO ₂ film 28 is etched away by about 0.2 μm by RIE, so that a level difference between the upper portion of the gold 31 and the upper portion of the SiO ₂ film 28 is eliminated, and a wiring layer having a flat structure can be obtained (FIG. 5E).

FIG. 6 is a sectional view showing a method of manufacturing a semiconductor device according to a fourth embodiment of the present invention in the order of steps.

An SiO ₂ film 33 is formed on a semiconductor substrate 32 to a thickness of about 2 μm by a CVD method.
m. Next, a resist 34 is formed on the SiO ₂ film 33, and the resist 34 is left using a photolithography method in a region other than a region where a wiring is to be formed. Next, using the resist 34 as a mask, the SiO ₂ film 33 is etched by about 1 μm
To form At this time, the resist 34 becomes sufficiently hydrophobic because it is exposed to the plasma containing fluorine (FIG. 6A).

Next, the semiconductor substrate 32 is immersed in an approximately 0.1% palladium chloride solution at room temperature for approximately 5 minutes to form palladium 36 at the bottom of the groove 35 where the SiO ₂ film 33 is exposed (FIG. 6B).

Next, after the semiconductor substrate 32 is washed with water and immersed in a copper sulfate solution, copper 37 can be deposited only on the portion where palladium 36 has been deposited (FIG. 6 (c)).

Next, by removing the resist and etching away the SiO ₂ film 33 by RIE, the step between the buried copper 37 and the SiO ₂ film 33 is eliminated, and a wiring layer having a flat structure can be obtained (FIG. 6 (d)). )).

〔The invention's effect〕

As described above, according to the present invention, a groove is formed in an insulating film,
A conductive film is buried in the groove at a depth equal to or less than the depth of the groove, and the insulating film is removed by etching to a depth of the buried conductive film, whereby a wiring having a flat shape can be formed.

Further, since the wiring is not formed by etching the metal, the wiring does not have an undercut and has a reverse tapered shape, and thus the wiring does not become thin. Further, voids can be prevented instead of forming a wiring by etching a metal and forming an insulating film around the wiring. Further, since the metal is buried shallower than the depth of the groove, it is possible to prevent the metal particle diameter from drooping.

[Brief description of the drawings]

FIG. 1 is a process sectional view showing a method of manufacturing a semiconductor device according to a first embodiment of the present invention. FIG. 2 is a process sectional view showing a method of manufacturing a semiconductor device according to a second embodiment of the present invention. FIG. 4 is a process sectional view showing a method for manufacturing a semiconductor device according to a modification of the first embodiment of the present invention. FIG. 4 is a process sectional view showing a method for manufacturing a semiconductor device according to the third embodiment of the present invention. FIG. 5 shows the fourth embodiment of the present invention.
FIG. 6 is a process sectional view showing the method for manufacturing the semiconductor device according to the fifth embodiment. FIG. 6 is a process sectional view showing the method for manufacturing the semiconductor device according to the fifth embodiment of the present invention. 7, 8 and 9 are process sectional views showing a method for manufacturing a conventional semiconductor device. In FIG, 1 ...... semiconductor substrate, 2 ...... SiO ₂ film, 3 ...... groove, 4 ...... A
l, 5 ... photoresist, 6 ... semiconductor substrate, 7 ... S
iO ₂ film, 8... Al wiring, 9... SiO ₂ film, 10... contact hole, 11 ₁ ... W, 11 ₂ ... Al, 12.

Claims (4)

(57) [Claims] A step of forming a groove in an insulating film on a semiconductor substrate; a step of embedding a conductive film in the groove to a depth equal to or less than the depth of the groove; Forming a groove on the first insulating film provided on the semiconductor substrate, a step of forming a resist pattern in an area where the groove is to be formed on the first insulating film provided on the semiconductor substrate, and a step other than the resist pattern Forming a second insulating film in a portion of the semiconductor device, and removing the resist pattern. 2. A step of forming a groove in an insulating film on a semiconductor substrate, a step of embedding a conductive film having a depth equal to or less than the depth of the groove, and forming the insulating film to a depth of the conductive film embedded in the groove. A step of forming a first conductive film on the surface of the groove and the insulating film; and a step of embedding the groove in the groove. Embedding a resist below the depth, removing the exposed first conductive film, and selectively embedding a second conductive film in the removed portion of the resist after removing the resist. A method of manufacturing a semiconductor device, comprising: 3. A step of forming a groove in an insulating film on a semiconductor substrate; a step of forming a first conductive film on the bottom and side surfaces of the groove so as not to bury the groove; A step of burying a second conductive film therein, wherein both the top of the first conductive film formed on the side surface of the groove and the surface of the second conductive film are lower than the surface of the insulating film. A method for manufacturing a semiconductor device, comprising: 4. The method according to claim 3, wherein the step of burying the second conductive film is a step of selectively burying copper.