JP2001102448A - Formation method for wiring - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a formation method for wiring wherein a wiring formation time is shortened by shortening a CMP process using an electroless plating method. SOLUTION: A process where an interlayer insulating film 3 is formed on a lower-layer wiring 2, a process where a connection hole 3a positioned above the lower-layer wiring 2 is provided to the interlayer insulating film 3, a process where a Cu seed layer 5 of such thickness as the connection hole 3a is not embedded is formed on the inside surface of connection hole 3a as well as the interlayer insulating film 3, a process where the Cu seed layer 5 present on the interlayer insulating film 3 is removed by CMP, a process where a Cu plated layer 6 is formed on the Cu seed layer 5 by an electroless plating method which uses a copper plating liquid so that the connection hole 3a is filled with the Cu plated layer 6, and a process where an upper-layer wiring is formed on the embedded Cu plated layer 6, are provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a wiring using an electroless plating method.

[0002]

2. Description of the Related Art FIGS. 8A to 8C are cross-sectional views showing a conventional wiring forming method.

First, as shown in FIG. 8A, an insulating film 101 is formed above a silicon substrate (not shown), and a lower wiring 102 made of Al or the like is formed on the insulating film 101. Next, an interlayer insulating film 103 made of SiO ₂ is deposited on the lower wiring 102, and a via hole 103a is formed in the interlayer insulating film 103. Thereafter, a diffusion preventing layer 104 made of a Ta-based material such as TaN is deposited in the via hole 103a and on the interlayer insulating film 103 by sputtering, and C is formed on the diffusion preventing layer 104 by sputtering.
A u seed layer 105 is deposited. The diffusion preventing layer 104 is a layer that prevents Cu in the Cu plating layer described later from diffusing into the interlayer insulating film 103. As the Cu seed layer 105, for example, a TiN film is used.

Thereafter, as shown in FIG. 8B, the Cu seed layer 1 is formed by electrolytic plating using a copper sulfate plating solution.
The Cu plating layer 106 is formed on the substrate 05.

Next, the Cu existing on the interlayer insulating film 103 is removed.
Plating layer 106, Cu seed layer 105 and diffusion prevention layer 1
04 is polished using CMP (Chemical Mechanical Polishing). As a specific method of the CMP, a method described in JP-A-10-22285 is used.
That is, a mixture of colloidal silica (SiO ₂ ), H ₂ O ₂ and glycine is used as a slurry, and this slurry is
While being applied to the processing point of the semiconductor wafer on which the u-plated layer 106 is formed, a surface having the processing point is pressed against a turntable on which a polishing cloth is laid to polish. In this way, as shown in FIG. 8C, the Cu plating layer 106 is buried in the via hole 103a.

Thereafter, the embedded Cu plating layer 106 is formed.
Then, an upper wiring (not shown) is formed on the interlayer insulating film 103.

[0007]

As described above, in the conventional wiring forming method, since the Cu plating layer 106 is formed on the entire semiconductor wafer using the electrolytic plating method, the Cu plating layer 106 exists on the interlayer insulating film 103. CMP of Cu plating layer 106
Need to be removed. The amount of shaving of the Cu plating layer by the CMP depends on the wiring structure and the like, but is often shaved by about 1 μm. Since the polishing rate of CMP is about 7000 angstroms / min, the polishing time needs at least about 1 minute. Therefore, if the electrolytic plating method is used, CM
Since the P step requires time, it is required to reduce the time required for the CMP step.

The present invention has been made in view of the above circumstances, and has as its object to reduce the time required for forming a wiring by shortening the CMP process using an electroless plating method. It is to provide a method.

[0009]

In order to solve the above-mentioned problems, a method of forming a wiring according to the present invention comprises the steps of forming an insulating film on a lower wiring, and forming the insulating film on the lower wiring. Providing a connection hole; forming a Cu seed layer on the inner surface of the connection hole and on the insulating film with a thickness that does not embed the connection hole;
Removing the seed layer by CMP, forming a Cu plating layer on the Cu seed layer by an electroless plating method using a copper plating solution, and embedding the Cu plating layer in the connection hole; Forming an upper wiring on the obtained Cu plating layer.

In the above method for forming a wiring, the Cu seed layer existing on the insulating film is removed by CMP.
By leaving a Cu seed layer only in the connection hole and forming a Cu plating layer on the Cu seed layer by an electroless plating method, the Cu plating layer is embedded in the connection hole.
For this reason, the shaving amount in the CMP process can be reduced. Therefore, the time required for the CMP step can be reduced, and the wiring formation time can be reduced.

Preferably, the method for forming a wiring according to the present invention further includes a step of forming a Cu diffusion preventing layer between the insulating film and the Cu seed layer.

According to the method of forming a wiring according to the present invention, there is provided a step of forming an insulating film on a lower wiring, and a step of forming a connection hole formed in the insulating film on the lower wiring by forming a connection hole on the lower wiring. A step of providing a hole, a step of forming a groove in the insulating film, the groove being connected to the connection hole and forming an upper layer wiring; and forming a groove on the connection hole inner surface, the groove inner surface and the insulating film. In addition, Cu of a thickness that does not bury the connection holes
Forming a seed layer; and forming C on the insulating film.
removing the u seed layer by CMP, and electroless plating using a copper plating solution to deposit Cu on the Cu seed layer.
Forming a plating layer to bury a Cu plating layer in the connection hole and the groove.

In the above method for forming a wiring, the Cu seed layer present on the insulating film is removed by CMP.
A Cu seed layer is left only in the connection hole and the trench,
By forming a Cu plating layer on the seed layer by an electroless plating method, the Cu plating layer is embedded in the connection holes and the grooves. Thus, the connection plug and the upper layer wiring are formed. For this reason, the shaving amount in the CMP process can be reduced. Therefore, the time required for the CMP step can be reduced, and the wiring formation time can be reduced.

[0014]

Embodiments of the present invention will be described below with reference to the drawings.

FIGS. 1A to 1C are cross-sectional views showing a method for forming a wiring according to a first embodiment of the present invention.

First, as shown in FIG. 1A, an insulating film 1 is formed above a silicon substrate (not shown), and a lower wiring 2 made of Al or the like is formed on the insulating film 1. next,
An interlayer insulating film 3 made of SiO ₂ or the like is deposited on the lower wiring 2 by a CVD (Chemical Vapor Deposition) method or the like. Thereafter, a resist film (not shown) is applied on the interlayer insulating film 3, and the resist film is exposed and developed to form a resist pattern (not shown) on the interlayer insulating film 3. Next, via hole 3a is formed in interlayer insulating film 3 by etching interlayer insulating film 3 using this resist pattern as a mask.

Thereafter, the resist pattern is peeled off, and a diffusion preventing layer 4 made of a high melting point metal is deposited in the via hole 3a and on the interlayer insulating film 3 by sputtering or the like. C by sputtering etc.
A u seed layer 5 is deposited. The diffusion preventing layer 4 is a layer that prevents Cu in the Cu plating layer described later from diffusing into the interlayer insulating film 3. The thickness of each of the diffusion prevention layer 4 and the Cu seed layer 5 is such that the via hole 3a is not buried.

Next, as shown in FIG. 1B, the Cu seed layer 5 and the diffusion preventing layer 4 existing on the interlayer insulating film 3 are polished by using CMP. As a specific method of the CMP, the slurry is applied to the semiconductor wafer on which the Cu seed layer 5 is formed, and the processed surface is pressed against a turntable on which a polishing cloth is laid to be polished. Thereby, the Cu seed layer 5 is left only in the via hole 3a. CM at this time
The amount of shaving by P is about 2000 angstroms, and the polishing time is about 20 seconds.

Thereafter, as shown in FIG. 1C, a Cu plating layer 6 is formed on the Cu seed layer 5 using an electroless plating method, so that the Cu plating layer 6 is formed in the via hole 3a.
Is embedded. Here, the electroless plating method is a method in which a semiconductor wafer is immersed in a copper plating solution to form a Cu plating layer 6 only on the Cu seed layer 5.

Next, an upper wiring (not shown) is formed on the buried Cu plating layer 6 and the interlayer insulating film 3.

According to the first embodiment, after the Cu seed layer 5 is formed only in the via hole 3a by performing CMP, the Cu plating layer 6 is formed on the Cu seed layer 5 by an electroless plating method. ing. For this reason, the shaving amount in the CMP process can be reduced as compared with the conventional wiring forming method. Specifically, while the shaving amount is about 1 μm in the conventional wiring forming method, the shaving amount can be set to about 2000 Å in the present embodiment. Therefore, the polishing time is about 20 seconds, and the time required for the CMP process can be reduced, thereby shortening the wiring formation time.

2 to 7 are sectional views showing a method for forming a Cu dual damascene wiring according to a second embodiment of the present invention.

First, as shown in FIG. 2, an insulating film 11 is formed above a silicon substrate (not shown), and a lower wiring 12 made of Al or the like is formed on the insulating film 11. Next, an interlayer insulating film 13 made of SiO ₂ or the like is deposited on the lower wiring 12 by a CVD method or the like. Thereafter, a resist film is applied on the interlayer insulating film 13, and the resist film is exposed and developed to form a first resist pattern 14 on the interlayer insulating film 13. Next, the interlayer insulating film 13 is etched using the first resist pattern 14 as a mask, so that the contact holes 13 are formed in the interlayer insulating film 13.
a is formed. This connection hole 13a is a hole for forming a plug.

Thereafter, as shown in FIG. 3, the first resist pattern 14 is removed. Next, a second resist pattern 15 is formed on the interlayer insulating film 13 by applying a resist film on the interlayer insulating film 13 and exposing and developing the resist film.

Thereafter, as shown in FIG. 4, the trench 13b is formed in the interlayer insulating film 13 by etching the interlayer insulating film 13 using the second resist pattern 15 as a mask. The groove 13b is for forming an upper layer wiring described later, and is connected to the connection hole 13a.

Next, as shown in FIG.
In addition, a diffusion prevention layer 17 made of a high melting point metal is deposited on the inside of the groove 13b and on the interlayer insulating film 13 by sputtering or the like, and a Cu seed layer 18 is deposited on the diffusion prevention layer 17 by sputtering. Diffusion prevention layer 17
Is a layer for preventing Cu in a Cu plating layer described later from diffusing into the interlayer insulating film 13. The thickness of each of the diffusion preventing layer 17 and the Cu seed layer 18 is such that the connection holes 13a are not buried.

Thereafter, as shown in FIG. 6, the Cu seed layer 18 and the diffusion preventing layer 17 existing on the interlayer insulating film 13 are polished by using CMP. The specific method of the CMP is the same as that of the first embodiment.

Next, as shown in FIG. 7, a Cu plating layer 20 is formed on the Cu seed layer 18 using an electroless plating method, so that the Cu plating layer 20 is embedded in the connection holes 13a and the grooves 13b. It is. Thereby, the connection hole 13a
A Cu plug is formed therein, and an upper layer wiring is formed in the groove 13b. The Cu plating layer 20 in the figure indicates a Cu plug and an upper wiring. The electroless plating method here is
This is the same as that of the first embodiment.

According to the second embodiment, after the Cu seed layer 18 is formed only in the connection hole 13a and the groove 13b by performing CMP, Cu plating is performed on the Cu seed layer 18 by electroless plating. The layer 20 is formed. For this reason, the shaving amount in the CMP process can be reduced as compared with the conventional wiring forming method. Therefore, the time required for the CMP step can be reduced, and the wiring formation time can be reduced.

The present invention is not limited to the above-described embodiment, but can be implemented with various modifications.

[0031]

As described above, according to the present invention, the Cu seed layer and the Cu diffusion preventing layer existing on the
The Cu seed layer is left only in the connection hole by removing by the MP, and the Cu plating layer is embedded in the connection hole by forming the Cu plating layer on the Cu seed layer by the electroless plating method. Therefore, it is possible to provide a method for forming a wiring in which the time for forming the wiring can be reduced by shortening the CMP step by using the electroless plating method.

[Brief description of the drawings]

FIGS. 1A to 1C are cross-sectional views illustrating a method for forming a wiring according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a method for forming a Cu dual damascene wiring according to a second embodiment of the present invention.

FIG. 3 is a cross-sectional view illustrating a method of forming a Cu dual damascene wiring according to a second embodiment of the present invention, illustrating a step subsequent to FIG. 2;

FIG. 4 is a cross-sectional view showing a method of forming a Cu dual damascene wiring according to a second embodiment of the present invention, showing a step subsequent to FIG. 3;

FIG. 5 is a cross-sectional view showing a method for forming a Cu dual damascene wiring according to the second embodiment of the present invention, showing a step subsequent to FIG. 4;

FIG. 6 is a cross-sectional view showing a method for forming a Cu dual damascene wiring according to the second embodiment of the present invention, and showing a step subsequent to FIG. 5;

FIG. 7 is a cross-sectional view showing a method of forming a Cu dual damascene wiring according to the second embodiment of the present invention, and showing a step subsequent to FIG. 6;

FIGS. 8A to 8C are cross-sectional views showing a conventional method for forming a wiring.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Insulating film 2 ... Lower wiring 3 ... Interlayer insulating film 3a ... Via hole (connection hole) 4 ... Diffusion prevention layer 5 ... Cu seed layer 6 ... Cu plating layer 11 ... Insulating film 12 ... Lower wiring 13 ... Interlayer insulating film 13a ... Connection hole 13b Groove 14 First resist pattern 15 Second resist pattern 17 Diffusion prevention layer 18 Cu seed layer 20 Cu plating layer 101 Insulating film 102 Lower wiring 103 Interlayer insulating film 103a Via hole 104: diffusion prevention layer 105: Cu seed layer 106: Cu plating layer

Claims (3)

[Claims] A step of forming an insulating film on the lower wiring, a step of providing a connection hole located on the lower wiring in the insulating film, a connection hole on an inner surface of the connection hole and on the insulating film. Forming a Cu seed layer with a thickness not embedded therein, removing the Cu seed layer present on the insulating film by CMP, and forming the Cu seed layer on the Cu seed layer by electroless plating using a copper plating solution. Forming a Cu plating layer to bury the Cu plating layer in the connection hole; and forming an upper wiring on the buried Cu plating layer. Method. 2. The method according to claim 1, further comprising the step of forming a diffusion preventing layer between the insulating film and the Cu seed layer. A step of forming an insulating film on the lower wiring, a step of forming a connection hole on the lower wiring, the connection hole being formed on the lower wiring and forming a connection plug; A step of providing a groove for forming an upper wiring, which is a groove connected to the connection hole, on the film, on the inner surface of the connection hole, on the inner surface of the groove and on the insulating film
A step of forming a Cu seed layer having a thickness that does not embed connection holes, a step of removing the Cu seed layer present on the insulating film by CMP, and a Cu seed layer by an electroless plating method using a copper plating solution. Forming a Cu plating layer thereon to bury the Cu plating layer in the connection holes and the grooves.