JP2002299437A - Method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing semiconductor device by which the influence of damages given to a low-k film by a dry etching plasma used for forming via holes or wiring grooves or ashing performed for peeling a photoresist can be eliminated at the time of forming metallic wiring of Cu, etc., by burying the wiring in the low-k film. SOLUTION: After an insulating film 3 is formed on a semiconductor substrate 1, Cu wiring 11 and 12 having contacts 13 and dummy contacts 14 are formed on the insulating film 3. Then the insulating film 3 is removed and the low-k film 9 is formed. Since the insulating film 3 is finally removed, the influence of damages given to the low-k film 9 by the plasma or ashing can be eliminated. In addition, the dummy contacts 14 are formed to support the wiring 11 and 12 so as to prevent the tilting or peeling of the wiring 11 and 12 until the low-k film 9 is formed when the insulating film 3 is removed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a Cu wiring to be embedded in a low dielectric constant insulating film (hereinafter, referred to as a low-k film).

[0002]

2. Description of the Related Art As a conventional method for forming a Cu wiring using a low-k film material, there is a method shown in FIGS. First, a base insulating film 100 such as a silicon oxide film is formed on a semiconductor substrate 10 such as silicon. The surface of the base insulating film 100 is flattened, and a lower wiring is formed by a Cu single damascene method. Lower layer wiring is lower layer C
Ta or Ta surrounding the u wiring 102 and the lower Cu wiring
It is composed of a barrier metal layer 101 such as N. Next, RIE (Reactive Ion Etching) for forming a via hole on the base insulating film 100 so as to cover the lower wiring is performed.
A silicon nitride (SiN) stopper 103 for preventing over-etching of anisotropic etching such as g) is formed. Then, a Low-k film material is further applied thereon to form a Low-k film 107 (FIG. 8A).
Then, the photoresist 1 on which a predetermined pattern is formed
09 is formed on the Low-k film 107, and a pattern of a via hole 110 for making contact with the lower Cu wiring 102 is formed by lithography (FIG. 8B).

Further, a wiring groove 11 for an upper wiring pattern connected to the via hole 110 by lithography.
1 is formed (FIG. 9A). After this, Ta or Ta
A barrier metal layer 112 such as N is formed, and Cu
Is deposited by a plasma method or the like, and then a low-k film 107 including via holes and wiring grooves by a plating method.
Is deposited over the entire surface of the substrate. Then, a lower layer is formed in the wiring groove in which the via hole is formed by a so-called Cu dual damascene method in which Cu is left only in the wiring groove including the wiring groove and the via hole by a chemical mechanical polishing (CMP) method. An upper layer wiring 104 having a contact connected to a Cu wiring is formed, and an upper layer wiring 105 is formed in a wiring groove where a via hole is not formed.
Is formed (FIG. 9B).

[0004]

Various types of low-k film materials such as fluorinated carbon, silane and organic have been proposed as materials for the low-k film. In comparison, it is characterized by low mechanical strength and resistance to plasma. As described above, when dry etching using plasma for processing via holes and wiring grooves using a photoresist as a mask and ashing for removing the resist thereafter are performed using the low-k film as described above,
The -k film itself is damaged by plasma, and the film itself deteriorates. That is, Lo is applied to the surface of the wiring groove or via hole exposed to plasma or ashing.
A wk film damage layer 108 is formed. as a result,
There have been problems such as peeling of the wiring and an increase in the actual insulation capacity. The damaged layer received by these plasmas can be removed with an HF solution or the like. In this case, however, the processing dimensions change, resulting in a problem such as a short circuit between wirings. The present invention has been made under such circumstances, and Lo
When a metal wiring such as Cu is buried in a w-k film, influence of damage to the low-k film caused by plasma for dry etching for forming a via hole or a wiring groove or ashing for removing a photoresist is considered. Provided is a method for manufacturing a lost semiconductor device.

[0005]

According to the present invention, an insulating film is formed on a semiconductor substrate, a metal wiring such as Cu having a contact and a dummy contact is formed on the insulating film, and the insulating film is removed. After removing this insulating film,
The method is characterized in that a -k film is formed and the metal wiring, the contact and the dummy contact are embedded in the Low-k film. Since the insulating film that forms the low-k film by embedding the metal wiring such as Cu is finally removed, the insulating film is received by dry etching plasma for forming a via hole or a wiring groove or ashing for removing a photoresist. The influence of damage to the Low-k film can be eliminated. Also, the dummy contact
The wiring is supported so that the wiring does not fall or peel until the Low-k film is formed when the insulating film is removed. It is attached when there is only one.
That is, the contact and the dummy contact have a unit wiring length of a predetermined length that one of them can support. Therefore, it is necessary to provide a contact and a dummy contact for each unit wiring length having the predetermined length.

According to the method of manufacturing a semiconductor device of the present invention, a step of forming a first insulating film in which a lower first wiring is buried is formed on a semiconductor substrate on which a semiconductor element is formed; Forming a second insulating film on the film, etching the second insulating film using a patterned photoresist as a mask, forming a wiring groove and a via hole in the wiring groove, and forming the via hole in the via hole. Exposing the lower wiring, simultaneously forming a dummy via hole, and exposing the first insulating film in the dummy via hole;
Depositing a wiring material on the second insulating film including the inside of the wiring groove, the inside of the dummy via hole, and the inside of the via hole; polishing the surface of the deposited wiring material to form a second wiring in the wiring groove; Forming a dummy contact in the dummy via hole, forming a contact connecting the first wiring and the second wiring in the via hole, forming a part or all of the second insulating film. Removing to expose at least a part of the dummy contact or a part of the contact;
Forming a third insulating film made of a low dielectric constant insulating film so as to cover the wiring, the dummy contact, and the contact; and flattening the surface of the third insulating film to form a second insulating film.
Exposing the surface of the wiring. The dummy contact may not be formed immediately above the first wiring in the lower layer.

According to a method of manufacturing a semiconductor device of the present invention, a first insulating film is formed on a semiconductor substrate on which a semiconductor element having an impurity diffusion region is formed, and a second insulating film is formed on the first insulating film. Forming an insulating film, and etching the first insulating film and the second insulating film using a patterned photoresist as a mask to form a wiring groove and a via hole in the wiring groove; Exposing the impurity diffusion region, and simultaneously etching the second insulating film using the photoresist as a mask to form a dummy via hole in the wiring groove, and forming the first insulating film in the dummy via hole. Exposing; and depositing a wiring material on a second insulating film including the inside of the wiring groove, the inside of the dummy via hole, and the inside of the via hole. Flattening the surface of the wiring material, forming a wiring in the wiring groove, forming a dummy contact in the dummy via hole, and forming a contact in the via hole for connecting the wiring and the impurity diffusion region; Removing a part or all of the second insulating film to expose at least a part of the dummy contact or a part of the contact; and insulating with a low dielectric constant so as to cover the wiring, the dummy contact and the contact. A step of forming a third insulating film made of a film; and a step of flattening the surface of the third insulating film to expose a surface of the wiring. The low dielectric constant insulating film may have a lower relative dielectric constant than the silicon oxide film. The low dielectric constant insulating film is an organic insulating film,
It may be one selected from a silane-based insulating film and a fluorinated carbon-based insulating film.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. First, referring to FIG. 1 to FIG.
An example will be described. Each of the drawings is a cross-sectional view showing a manufacturing process of the semiconductor device. A first insulating film 2 such as a silicon oxide film having a thickness of about 800 nm is formed on a semiconductor substrate 1 such as silicon on which a semiconductor element is formed by a CVD method or the like. The surface of the first insulating film 2 is flattened, and a wiring groove having a depth of about 400 nm is formed. The lower wiring is buried in the wiring groove by a Cu single damascene method or the like. The lower layer wiring includes a lower layer Cu wiring 6 and Ta or TaN formed so as to surround the lower layer Cu wiring.
And the like. Next, a silicon film having a thickness of about 50 nm for preventing over-etching of anisotropic etching such as RIE for forming a via hole as a second insulating film on the first insulating film 2 so as to cover the lower wiring. A nitride film (SiN) stopper 7 is formed. Further, a film thickness of about 800 n is further formed thereon.
The third insulating film 3 made of a silicon oxide film of
Is formed by a method D or the like (FIG. 1A).

Thereafter, a photoresist 15 having a predetermined pattern formed thereon is formed on the third insulating film 3, and a pattern of a via hole 16 for making contact with the lower Cu wiring 6 by lithography and the other conductive layers are formed. A pattern of a dummy via hole 17 that is not electrically connected is formed (FIG. 1B). Further, a wiring groove 18 for the upper wiring pattern connected to the via hole 16 is formed by lithography, and a wiring groove 19 for the upper wiring pattern connected to the dummy via hole 17 is formed (FIG. 2A). Thereafter, Ta or Ta is formed on the third insulating film 3 including the insides of the wiring grooves 18 and 19, the via hole 16 and the dummy via hole 17.
After a barrier metal layer 8 such as N is formed, Cu is formed thereon by a plasma method or the like, and then a dummy via hole 17, a via hole 16, a wiring groove 18,
A Cu film is formed on the entire surface of the third insulating film 3 including the inside 19. Thereafter, the wiring groove 18 including the via hole 16 is formed in the wiring groove 18 including the via hole 16 by a so-called Cu dual damascene method in which only the wiring grooves 18 and 19 and the dummy via holes 17 and the via hole 16 are left by the CMP method.
Contact 1 connected to wiring 11 and lower Cu wiring 6
3 and a wiring groove 19 including a dummy via hole 17.
Is formed with an upper layer Cu wiring 12 and a dummy contact 14 (FIG. 2B).

Next, a part of the third insulating film 3 is, for example,
The contact 1 was removed by an etching solution containing HF.
3 and a part of the side surface of the dummy contact 14 are exposed (FIG. 3A). At this time, the upper layer C is controlled by controlling the etching amount of the third insulating film 3 which is a silicon oxide film.
When the degree of exposure of the u wiring is adjusted and the etching amount of the third insulating film 3 becomes larger than the depth of the upper Cu wiring, the insulating film below the upper Cu wiring is removed, so that the upper Cu wiring floats in the air. State, resulting in a wiring failure. Therefore, the previously formed dummy contact serves to prevent wiring failure due to etching. next,
After exposing a part of the upper Cu wirings 11 and 12 by etching, the upper Cu wiring films 11 and 12 are coated with a fourth insulating film 9 which is a Low-k film such as a methylsiloxane-based or polyarylene-based film by a coating method. Is formed over the entire surface of the semiconductor substrate 1 (FIG. 3B). Thereafter, the surface of the Low-k film, which is the fourth insulating film 9, is subjected to CMP.
Processing and flattening. By performing the flattening process, the Low-k film on the wiring groove is removed, and the upper Cu wirings 11 and 12 are exposed (FIG. 4).

The lower wiring composed of the lower Cu wiring 6 and the barrier metal layer 5 is connected to a lower metal wiring or provided with a contact such as tungsten connected to the lower Cu wiring 6. It can be electrically connected to an impurity diffusion region which is one of source / drain regions of a MOS transistor formed on a semiconductor substrate. As in this embodiment, the insulating film damaged by the plasma for dry etching for forming the dummy via hole, the via hole and the wiring groove or the ashing for peeling off the photoresist is peeled off, so that the low-k film is damaged. And a stable wiring structure can be obtained. The dummy contact supports the wiring so that the wiring does not fall down or peel off until the Low-k film is formed when the insulating film is removed, and a wiring having high mechanical strength can be obtained.

Next, a second embodiment will be described with reference to FIGS. 5 and 6 are cross-sectional views illustrating a manufacturing process of the semiconductor device. A first insulating film 23 such as a silicon oxide film is formed by a CVD method or the like on a semiconductor substrate 21 of a semiconductor element, for example, silicon on which a MOS transistor is formed. In a surface region of the semiconductor substrate 21, an impurity diffusion region 22 used as a source / drain region of a MOS transistor is formed. Then, a second insulating film 29 made of a silicon oxide film or the like having a thickness of about 800 nm is formed on the first insulating film 23 by a CVD method or the like. Thereafter, a photoresist on which a predetermined pattern is formed is formed on the second insulating film 29, and is not electrically connected to a pattern of a via hole for making contact with the impurity diffusion region 22 by lithography and other conductive layers. A dummy via hole pattern is formed. Further, a wiring groove for the wiring pattern connected to the via hole is formed by lithography, and a wiring groove for the wiring pattern connected to the dummy via hole is formed.

After that, a T layer is formed on the second insulating film 29 including the insides of these wiring grooves, via holes and dummy via holes.
a or a barrier metal layer 28 such as TaN is formed;
After Cu is formed thereon by a plasma method or the like, Cu is formed on the entire surface of the second insulating film 29 including the dummy via holes, the via holes, and the insides of the wiring grooves by a plating method. Thereafter, the wiring 24 including the via hole and the contact 26 connected to the impurity diffusion region 22 are formed in the wiring groove including the via hole by the so-called Cu dual damascene method in which only the wiring groove, the dummy via hole, and the via hole are left by the CMP method. The Cu wiring 25 and the bottom surface are formed in the wiring groove including the dummy via hole.
3 is formed in contact with the dummy contact 27 in FIG.
(A)).

Next, the second insulating film 29 is formed by, for example, HF
Are removed by an etching solution containing
5. The contact 26 and the dummy contact 27 are exposed (FIG. 5B). At this time, the degree of exposure of the Cu wiring is adjusted by controlling the etching amount of the second insulating film 29, which is a silicon oxide film, and when the etching amount of the second insulating film 29 becomes larger than the depth of the Cu wiring, the Cu wiring becomes lower. By removing the insulating film, the Cu wiring floats in the air, resulting in a wiring failure. Therefore, the dummy contact formed earlier serves to prevent wiring defects due to etching. Next, after exposing the Cu wirings 24 and 25 by etching, Lo
A third insulating film 20, which is a w-k film, is coated with Cu by a coating method.
It is formed on the entire surface of the semiconductor substrate 21 so as to cover the wiring films 24 and 25 (FIG. 6A). Thereafter, the surface of the Low-k film that is the third insulating film 20 is planarized by a CMP process. By performing this planarization process, the Low-k film on the wiring groove is removed, and the Cu wirings 24 and 25 are exposed to form a wiring structure of the semiconductor device.
(B)).

As in this embodiment, the insulating film damaged by the plasma for dry etching for forming the dummy via hole, the via hole or the wiring groove or the ashing for removing the photoresist is peeled off. There is no damage to the film, and a stable wiring structure can be obtained. The dummy contact supports the wiring so that the wiring does not fall down or peel off until the Low-k film is formed when the insulating film is removed, and a wiring having high mechanical strength can be obtained.

Next, a third embodiment will be described with reference to FIG. FIG. 7 is a plan view of the semiconductor device and FIG.
It is sectional drawing of the part which follows the -A 'line. A film thickness of about 80 is formed on a semiconductor substrate 31 such as silicon on which a semiconductor element is formed.
A first insulating film 22 such as a silicon oxide film having a thickness of 0 nm is formed. The surface of the first insulating film 2 is flattened,
A wiring groove having a depth of about 400 nm is formed. The lower wiring is buried in the wiring groove. The lower wiring includes a lower Cu wiring 36 and a barrier metal layer 35 such as Ta or TaN formed so as to surround the lower Cu wiring 36. A silicon nitride film (about 50 nm thick) for preventing over-etching of anisotropic etching such as RIE for forming a via hole as a second insulating film on the first insulating film 32 so as to cover the lower wiring. S
iN) A stopper 37 is formed. Further, a third insulating film 33 made of a silicon oxide film or the like is formed thereon.

On the third insulating film 33, a fourth insulating film 39, which is a low-k film, is formed. Then, the upper wiring and the contact are formed by the third and fourth insulating films 3.
3 and 39 are embedded. Third and fourth insulating films 3
In 3 and 39, a wiring groove having a via hole and a wiring groove having a dummy via hole are formed. In the wiring groove including the via hole, a contact 42 connected to the upper Cu wiring 40 and the lower Cu wiring 36 is formed. In the wiring groove including the dummy via hole, the upper Cu wiring 41 and the bottom surface are formed of the first insulating film. A dummy contact 43 in contact with 32 is formed. In the above-described embodiment, the dummy contact is columnar like the contact. However, the dummy contact is not connected to the underlying wiring or the semiconductor substrate. Therefore, the dummy contact connects between the wirings or between the wiring and the impurity diffusion region. In order to achieve this, the contact existing is restricted in terms of shape, and a free shape is allowed as long as there is no wiring or impurity diffusion region below.

In this embodiment, the contact is in the form of a column, whereas the column is in the form of a continuous plate. With such a structure, the mechanical strength is sufficiently ensured even when the insulating film is peeled off, so that the strength of the wiring structure is improved. In addition, the dummy contact is not necessarily connected to the lower layer wiring, so that it is not always necessary to match the shape of the columnar body or the like with the contact.
For example, as shown in this embodiment, a plurality of dummy contacts can be continuous to form a continuous body. This depends on the state of the underlying insulating film.

[0019]

According to the present invention, when an interlayer insulating film is used as the Low-k film, plasma damage is easily caused when a via hole pattern or a wiring pattern is formed on the Low-k film in the conventional Cu wiring. Peeling and substantial increase in insulation capacity were caused. It is possible to add a step of removing the damaged layer, but in this case, the via diameter and the wiring dimension are increased. On the other hand, in the present invention, Low
Such problems are avoided because the -k film is not exposed to the plasma. Also, the dummy contact
The wiring is supported so that the wiring does not fall down or peel off until the Low-k film is formed when the insulating film is removed, and the method of the present invention for removing the insulating film can be sufficiently supported.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a manufacturing process of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention;

FIG. 4 is a sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention;

FIG. 5 is a sectional view showing a manufacturing process of the semiconductor device according to the second embodiment of the present invention.

FIG. 6 is a sectional view showing a manufacturing process of the semiconductor device according to the second embodiment of the present invention.

FIG. 7 is a sectional view showing a manufacturing process of a semiconductor device according to a third embodiment of the present invention.

FIG. 8 is a sectional view showing a manufacturing process of a conventional semiconductor device.

FIG. 9 is a cross-sectional view illustrating a manufacturing process of a conventional semiconductor device.

[Explanation of symbols]

1, 10, 21, 31 ... semiconductor substrate, 2, 3, 21, 23, 29, 107 ... insulating film, 5, 8, 28, 35, 38, 101, 112 ... barrier metal layer, 6, 11, 12, 24, 25, 36, 40, 41, 10
2, 104, 105: Cu wiring, 7, 37, 103: silicon nitride stopper, 9, 20, 39, 107: insulating film (Low-k)
13, 26, 42, 113 ... contact, 14, 27, 43 ... dummy contact, 16, 110 ... via hole, 17 ... dummy via hole, 18, 19, 111 ... wiring groove .

 ──────────────────────────────────────────────────続 き Continued on front page F term (reference) AF04 AG10 AH02 BD01 BD02 BD04 BD09 BF02 BH20 BJ02

Claims (5)

[Claims] A step of forming a first insulating film in which a lower first wiring is buried on a semiconductor substrate on which a semiconductor element is formed; and a second insulating film on the first insulating film. Forming a wiring groove and a via hole in the wiring groove by using the patterned photoresist as a mask to form a via hole in the wiring groove, exposing the lower wiring in the via hole, and simultaneously forming a dummy via hole Forming the first insulating film in the dummy via hole, and depositing a wiring material on the second insulating film including the inside of the wiring groove, the inside of the dummy via hole, and the inside of the via hole. Polishing the surface of the deposited wiring material to form a second wiring in the wiring groove; forming a dummy contact in the dummy via hole; Forming a contact connecting the first wiring and the second wiring; and removing at least a part of the dummy contact or a part of the contact by removing a part or the whole of the second insulating film. Exposing; forming a third insulating film made of a low dielectric constant insulating film so as to cover the second wiring, the dummy contact and the contact; and planarizing the surface of the third insulating film. Exposing the surface of the second wiring by using the method. 2. The method according to claim 1, wherein the dummy contact is not formed immediately above a first wiring in the lower layer. A step of forming a first insulating film on a semiconductor substrate on which a semiconductor element having an impurity diffusion region is formed; a step of forming a second insulating film on the first insulating film; The first insulating film and the second insulating film are etched using a patterned photoresist as a mask to form a wiring groove and a via hole in the wiring groove to expose the impurity diffusion region in the via hole. Simultaneously etching the second insulating film using the photoresist as a mask to form a dummy via hole in the wiring groove;
Exposing the first insulating film to the inside of the dummy via hole; depositing a wiring material on the second insulating film including the inside of the wiring groove, the inside of the dummy via hole and the inside of the via hole; Flattening the surface of the wiring material thus formed to form a wiring in the wiring groove, forming a dummy contact in the dummy via hole, and forming a contact in the via hole to connect the wiring and the impurity diffusion region; Removing a part or all of the second insulating film to expose at least a part of the dummy contact or a part of the contact; and a low dielectric constant so as to cover the wiring, the dummy contact and the contact. Forming a third insulating film made of an insulating film; flattening the surface of the third insulating film to form a surface of the wiring; The method of manufacturing a semiconductor device characterized by comprising the step of exposing the. 4. The method according to claim 1, wherein the low dielectric constant insulating film has a lower relative dielectric constant than a silicon oxide film. 5. The insulating film according to claim 1, wherein the low dielectric constant insulating film is one selected from an organic insulating film, a silane-based insulating film, and a fluorinated carbon-based insulating film. 13. A method for manufacturing a semiconductor device according to