JPS59214228A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS59214228A JPS59214228A JP8754383A JP8754383A JPS59214228A JP S59214228 A JPS59214228 A JP S59214228A JP 8754383 A JP8754383 A JP 8754383A JP 8754383 A JP8754383 A JP 8754383A JP S59214228 A JPS59214228 A JP S59214228A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- film
- opening
- etching
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
Abstract
Description
【発明の詳細な説明】
（技術分野う
この発明は、半導体素子内の絶縁性被膜の開口形状を改
良して、金属配線部の段切れを防止できるようにした半
導体装置の製造方法に関する。TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor device in which the shape of an opening in an insulating film in a semiconductor element is improved to prevent breakage in metal wiring sections.
（従来技術）
近年高集積密度のＩＣ装置の製造において、ドライエツ
チング法が使用されている。このドライエツチング法で
コンタクト穴などの゛開口部を形成すると、開口部側壁
のテーパが少なく、良好なエツチング精度が得られるこ
とが知られている。(Prior Art) In recent years, dry etching methods have been used in the manufacture of IC devices with high integration density. It is known that when an opening such as a contact hole is formed using this dry etching method, the side wall of the opening has less taper and good etching accuracy can be obtained.
しかし、開口部のテーパが小さいことは、第１図に示す
ごとく、シリコン基板１上のＣＶＤ５ｉＯ２（ＰＳＧ）
膜２とＡｔ配線３との段差が大きくなり、Ａｔ配線３の
段切れ４が発生し易くなる。However, the small taper of the opening means that the CVD5iO2 (PSG) on the silicon substrate 1 is
The difference in level between the film 2 and the At wiring 3 becomes large, and a break 4 in the At wiring 3 is likely to occur.
たとえば、深さ６ｏｏｏＡ程度の開口部５に厚さ約１０
００ＯＡのＡｔ配線層３を形成すると、開口部５の端部
でのＡｔ配線層３の厚みは１０００λ程度になり、通電
中Ｍ配線層３が断線することがある。For example, the opening 5 with a depth of about 6oooA has a thickness of about 10mm.
When the At wiring layer 3 of 00 OA is formed, the thickness of the At wiring layer 3 at the end of the opening 5 is about 1000 λ, and the M wiring layer 3 may be disconnected during energization.
゛また、水分により、ｋｌが酸化すると、抵抗成分が増
加するため、さらに通電により、Ａｔ配線層３が溶断す
る危険性があった。Furthermore, when kl is oxidized by moisture, the resistance component increases, so there is a risk that the At wiring layer 3 may be blown out by further energization.
（発明の目的）
この発明は、上記従来の欠点を除去するためになされた
もので、金属配線部の段切れを防止できる半導体装置の
製造方法を提供することを目的とする。(Object of the Invention) The present invention has been made to eliminate the above-mentioned conventional drawbacks, and an object of the present invention is to provide a method for manufacturing a semiconductor device that can prevent disconnection of the metal wiring portion.
（発明の構成）
この発明の半導体装置の製造方法は、半導体基板上に第
１の絶縁膜を形成してオーミック接触すべき拡散領域の
第１の絶縁膜を除去して開口部を形成し、この開口部お
よび第１の絶縁膜の全表面に第２の絶縁膜を形成し、こ
の第２の絶縁膜を第１の絶縁膜が露出するまでエツチン
グを行って開口部の部分において第１の絶縁膜の内壁面
に第２の絶縁膜によるテーパ領域を形成し、上記拡散領
域にオーミック接触する工うに第１の絶縁膜およびテー
パ領域に金属配線を形成するようにしたものである。(Structure of the Invention) A method for manufacturing a semiconductor device of the present invention includes forming a first insulating film on a semiconductor substrate and removing the first insulating film in a diffusion region to be in ohmic contact to form an opening. A second insulating film is formed over the opening and the entire surface of the first insulating film, and the second insulating film is etched until the first insulating film is exposed, so that the first insulating film is etched in the opening. A tapered region of a second insulating film is formed on the inner wall surface of the insulating film, and metal wiring is formed on the first insulating film and the tapered region to make ohmic contact with the diffusion region.
、（実施例）
以下、この発明の半導体装置の製造方法の実施例につい
て図面に基づき説明する。第２図（ａ）ないし第２図（
ｄ）はその−実施例の工程説明図である。, (Example) Hereinafter, an example of the method for manufacturing a semiconductor device of the present invention will be described based on the drawings. Figure 2 (a) to Figure 2 (
d) is a process explanatory diagram of the example.
まず、第２図（ａ）に示すように、シリコン基板１００
上に、厚さ約６０００〜８０００人のリンを含んだＣＶ
Ｄ ５ｉ０２（Ｐ Ｓ Ｇ ）膜１１を形成する。First, as shown in FIG. 2(a), a silicon substrate 100 is
On top, a CV containing about 6000 to 8000 phosphorus in thickness
A D 5i02 (P S G ) film 11 is formed.
次に、厚さ１２０００〜１５０００Ａのホトレソヌ）
１２ （ＡＺ−１３５０または１４５０ ）をＣＶ Ｄ
Ｓ ｉ ０２膜１１上に形成する。Next, a photoresonne with a thickness of 12,000 to 15,000A)
12 (AZ-1350 or 1450) CV D
It is formed on the SiO2 film 11.
次に、オーミック接触すべき拡散領域１１０上のＣＶＤ
ＳｉＯ□膜１１膜上１ホトレジスト膜１２を除去して
開口部１３を形成する。Next, CVD on the diffusion region 110 to be made into ohmic contact.
The first photoresist film 12 on the SiO□ film 11 is removed to form an opening 13.
この開口部１３は、たとえば、ＣＦ４’またはＣ２Ｆ６
ガス中で反応性（異方性）イオンエツチングすることに
よシ、形成されるため、開口部１３の開口壁のテーパは
極めて少ない。This opening 13 is, for example, CF4' or C2F6
Since it is formed by reactive (anisotropic) ion etching in a gas, the taper of the opening wall of the opening 13 is extremely small.
次に、ホトレジスト膜１２を除去した後、開口部および
ＣＶ Ｄ Ｓ ｉ ０２膜１１の全表面に約８０００〜
１ｏｏｏｏ人のＣＶＤ ５ｉｎ２膜１４を第２図（ｂ）
に示すように形成する。Next, after removing the photoresist film 12, about 8,000~
Figure 2 (b) 1oooo CVD 5in2 film 14
Form as shown.
次に、と（Ｄ ＣＶＤ ５ｉｆｔ膜１４は、ＣＦ４また
ｈｃ２Ｆａガス中で反応性イオンエツチングされる。こ
のイオンエツチングはＣＶＤ ５ｉｎ２膜１４の最初の
形状にしたがって進むので、 ＣＶＤ ５ｉＯｚ膜１１
の表面が露出した時点でイオンエツチングを終了させる
。Next, the CVD 5in2 film 14 is reactive ion etched in CF4 or hc2Fa gas. This ion etching proceeds according to the initial shape of the CVD 5in2 film 14, so that the CVD 5iOz film 11
Ion etching is terminated when the surface of the substrate is exposed.
これによυ、ＣＶＤ５ＩＯ２のチー／Ｊ領域１５が形成
される。As a result, the Q/J region 15 of CVD5IO2 is formed.
次に、第２図（ｄ）に示すように、ＣＶＤ ５ｉＯｚ膜
１１の全表面に約厚さ１００００〜１２０００ＡのＡｎ
蒸Ｎまたはスパツン′することによシ、拡散領域１１０
と万一ミックコンタクトするように、金属配線１６を形
成する。Next, as shown in FIG. 2(d), an An layer with a thickness of approximately 10,000 to 12,000 Å is applied to the entire surface of the CVD 5iOz film 11.
Diffusion region 110 is formed by vaporizing N or sputtering.
A metal wiring 16 is formed so as to be in contact with the metal wiring 16.
第３図はこの発明の半導体装置の製造方法の第２の実施
例を説明するための図である。この第３図の実施例の場
合は、シリコン基板３０上にｂ間絶縁膜３１ （ＰＳＧ
膜）全形成する。FIG. 3 is a diagram for explaining a second embodiment of the method for manufacturing a semiconductor device of the present invention. In the case of the embodiment shown in FIG. 3, an inter-b insulating film 31 (PSG
membrane) completely formed.
次に、拡散領域３５上のこの眉間絶縁膜３１を除去して
開口部３６ Ｓ、Ｈ形成する。この開口部３６を形成し
た後、第２の絶縁性被膜を形成して全面方向性エツチン
グを行い、この方向性エツチング後、開口部３６におけ
る層間絶縁膜３１の側壁にテーノ？状の絶縁膜３２が存
在する。Next, the glabellar insulating film 31 on the diffusion region 35 is removed to form openings 36S and H. After this opening 36 is formed, a second insulating film is formed and directional etching is performed on the entire surface, and after this directional etching, the sidewall of the interlayer insulating film 31 in the opening 36 is coated with a TENO film. There is an insulating film 32 having a shape.
この絶縁膜３２が形成されることによシ、その上にｈｔ
ｉどの金縞配＆３３を形成′Ｊ−ると、開口部３６にお
ける壁面カバー状態をなだらかにすることによシ、金属
配ＫＭ３３の膜厚を確保する。By forming this insulating film 32, ht
When forming the gold striped pattern KM33, the thickness of the metal pattern KM33 is ensured by smoothing the wall surface covering at the opening 36.
また、厚い５ｉ０２領域上のＰＳＧ膜３膜上１上成され
た層間絶縁膜３１においても段差部分３４が形成される
が、この段差部分３４においても同様の効果が得られる
。Further, a step portion 34 is also formed in the interlayer insulating film 31 formed on the PSG film 3 on the thick 5i02 region, and the same effect can be obtained in this step portion 34 as well.
このように、第２の実施例では、層間絶縁膜３１を開口
した後、全面に第２の絶縁性被膜を形成し、次に全面方
向性エツチングを行う工程を追加するだけで、開口側壁
を斜面化することができ、急峻な段差をなくすることに
なる。これによシ、ステップカバーの悪い膜を上層につ
けても、断切れをしない構造を作る利点がある。In this way, in the second embodiment, after opening the interlayer insulating film 31, the second insulating film is formed on the entire surface, and then the opening sidewalls are formed by simply adding the steps of performing directional etching on the entire surface. It can be made into a slope, eliminating steep steps. This has the advantage of creating a structure that will not break even if a film with a bad step cover is attached to the upper layer.
また、上記第２の実施例では、拡散領域３５のコンタク
トホール（開口部３６）の金属配線３３のステップカバ
−ソの改善について説明したが、第３図に示すような構
造とすることにより、配線金属３３０段差をもなだらか
にする効果が生じる。Furthermore, in the second embodiment described above, improvement of the step cover of the metal wiring 33 in the contact hole (opening 36) of the diffusion region 35 was explained, but by adopting the structure as shown in FIG. The effect of smoothing out the level difference in the wiring metal 330 is also produced.
以上のように、この発明の半導体装置の製造方法によれ
ば、半導体基板上に第１の絶縁膜を形成してオーミック
接触すべき拡散領域の第１の絶縁膜を除去して開口部を
形成し、この開口部および第１の絶縁膜の全表面に第２
の絶縁膜を形成し、この第２の絶縁膜を第１の絶縁膜が
露出するまでエツチングを行って開口部の部分において
第１の絶縁膜の内壁面に第２の絶縁膜によるテーパ領域
を形成し、拡散領域にオーミック接触するように第１の
絶縁膜およびテーパ領域に金属配線を形成するようにし
たので、ステップカバー状態が改善され、金属配線の段
切れを防止することができる。As described above, according to the method of manufacturing a semiconductor device of the present invention, a first insulating film is formed on a semiconductor substrate, and an opening is formed by removing the first insulating film in a diffusion region where ohmic contact is to be made. A second insulating film is formed in this opening and on the entire surface of the first insulating film.
This second insulating film is etched until the first insulating film is exposed to form a tapered region of the second insulating film on the inner wall surface of the first insulating film at the opening. Since the metal wiring is formed in the first insulating film and the tapered region so as to be in ohmic contact with the diffusion region, the step cover condition is improved and breakage of the metal wiring can be prevented.
第１図は従来の半導体装置の製造方法を説明するための
図、第２図（ａ）ないし第２図（ｄ）はそれぞれこの発
明の半導体装置の製造方法の一実施例の工程説明図、第
３図はこの発明の半導体装置の製造方法の他の実施例の
工程説明図である。
３０．１００・・シリコン基板、１１．１４・・・ＣＶ
Ｄ ５ｉ０２膜、１２・・・ホトレゾスト膜、１３・・
・開口部、１５・・・テーパ領域、１６・・・Ａｔ配線
、３１・・・層間絶縁膜、３２・・・絶縁膜、３３・・
・金属配線、３４・・・段差部分、３５，１１０・・・
拡散領域。
第１図
第３図
０
第２゜FIG. 1 is a diagram for explaining a conventional method of manufacturing a semiconductor device, and FIGS. 2(a) to 2(d) are process explanatory diagrams of an embodiment of the method of manufacturing a semiconductor device of the present invention, respectively. FIG. 3 is a process explanatory diagram of another embodiment of the method for manufacturing a semiconductor device of the present invention. 30.100...Silicon substrate, 11.14...CV
D 5i02 film, 12... Photoresist film, 13...
- Opening, 15... Tapered region, 16... At wiring, 31... Interlayer insulating film, 32... Insulating film, 33...
・Metal wiring, 34...Step part, 35,110...
Diffusion area. Figure 1 Figure 3 0 2゜
Claims (1)
板の拡散領域の部分に開口部を形成する工程と、この開
口部の形成後に上記第１の絶縁膜上に第２の絶縁を形成
しこの第２の絶縁膜を上記開口部の側壁に傾斜状に残存
するように全面エツチングを行う工程と、このエツチン
グ工程終了（＆上記拡散領域にコンタクトするように上
記第１の絶縁膜上に金属配線を形成する工程とよシなる
半導体装置の製造方法。After forming a first insulating film on the semiconductor substrate, forming an opening in the diffusion region of the semiconductor substrate, and forming a second insulating film on the first insulating film after forming the opening. There is a step of etching the entire surface of the second insulating film so that it remains in an inclined manner on the side wall of the opening, and a step of etching the second insulating film on the first insulating film so as to be in contact with the diffusion region. A method of manufacturing semiconductor devices that is different from the process of forming metal wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8754383A JPS59214228A (en) | 1983-05-20 | 1983-05-20 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8754383A JPS59214228A (en) | 1983-05-20 | 1983-05-20 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59214228A true JPS59214228A (en) | 1984-12-04 |
Family
ID=13917892
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8754383A Pending JPS59214228A (en) | 1983-05-20 | 1983-05-20 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59214228A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0257948A2 (en) * | 1986-08-25 | 1988-03-02 | AT&T Corp. | Conductive via plug for CMOS devices |
| JPS63170921A (en) * | 1987-01-08 | 1988-07-14 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| US7411211B1 (en) * | 1999-07-22 | 2008-08-12 | Semiconductor Energy Laboratory Co., Ltd. | Contact structure and semiconductor device |
-
1983
- 1983-05-20 JP JP8754383A patent/JPS59214228A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0257948A2 (en) * | 1986-08-25 | 1988-03-02 | AT&T Corp. | Conductive via plug for CMOS devices |
| JPS63170921A (en) * | 1987-01-08 | 1988-07-14 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| US7411211B1 (en) * | 1999-07-22 | 2008-08-12 | Semiconductor Energy Laboratory Co., Ltd. | Contact structure and semiconductor device |
| US7626202B2 (en) | 1999-07-22 | 2009-12-01 | Semiconductor Energy Laboratory Co., Ltd. | Contact structure and semiconductor device |
| US7956359B2 (en) | 1999-07-22 | 2011-06-07 | Semiconductor Energy Laboratory Co., Ltd. | Contact structure and semiconductor device |
| US8258515B2 (en) | 1999-07-22 | 2012-09-04 | Semiconductor Energy Laboratory Co., Ltd. | Contact structure and semiconductor device |
| US8368076B2 (en) | 1999-07-22 | 2013-02-05 | Semiconductor Energy Laboratory Co., Ltd. | Contact structure and semiconductor device |
| US8624253B2 (en) | 1999-07-22 | 2014-01-07 | Semiconductor Energy Laboratory Co., Ltd. | Contact structure and semiconductor device |
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