JPH09172075A - Manufacture for interlayer connection hole in multilayer wiring of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce ununiformity and film thickening of a resist film by a method wherein a wiring groove is formed in an interlayer film, resist is applied to the interior of a groove and a face of the interlayer film until the groove is completely embedded, and resist is ground to such degree that the face of interlayer film is not faced, so that the film is flattened and thinned. SOLUTION: Resist 100 is applied to an interlayer film 181, and after patterned, resist is etched, to form a wiring groove 102 and a wiring groove group 103. After resist for forming the wiring groove 102 and the wiring groove group 103 is removed, interlayer connection hole forming resist 101 is reapplied. At this time, the resist 101 to be applied is applied to such degree that the wiring groove 102 and the wiring groove group 103 are completely embedded. Then, the interlayer connection hole forming resist 101 is ground by a CMP device, etc., and a film thickness Z is set to be about 1μm. The film thickness Z is decided by the relationship between a depth of the interlayer connection hole to be formed and an etching rate of the interlayer film and resist. It is possible to reduce ununiformity and film thickening of a resist film.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing an interlayer connection hole when a trench wiring is used.

[0002]

2. Description of the Related Art With the recent high integration of integrated circuits, the area used for wiring connecting elements on the integrated circuit has become smaller. For this reason, a technique for forming a multilayer wiring has become important. 5 (a) to 5 (e) show a conventional manufacturing process of a multilayer wiring.

As shown in FIG. 5A, lower layer wirings 584 and 585 are provided in a lower layer portion 580 used for forming a buried wiring or the like. Next, an interlayer film 581 made of an insulating film such as silicon dioxide is formed on the lower layer portion 580. The interlayer film 581 has a function of insulating and separating the wiring formed in the lower layer portion 580 and the wiring or the semiconductor element formed in the upper layer portion 582.

Next, as shown in FIG. 5B, a resist 500 is applied to the surface of the interlayer film 581, and patterning is performed by a lithography method to form wiring. After that, the interlayer film 581 is etched to a desired depth by reactive ion etching (hereinafter, referred to as RIE) or the like to form a wide wiring groove 502 and a narrow wiring groove group 50.
Form 3 The wiring groove 502 and the wiring groove group 503 thus formed are used as groove wiring by embedding a wiring material such as aluminum or copper in them. Generally, these wirings are often used in a laminated structure with a refractory metal.

Next, as shown in FIG. 5C, the wiring groove 502 and the wiring groove group 503 formed in the interlayer film 581.
After removing the resist 500 used to form
A resist 501 is newly applied on the surface of the interlayer film 581. At this time, the film thicknesses A and B of the resist become non-uniform due to the viscosity of the applied resist and the difference in the pattern shapes of the groove wiring portion 586 and the wiring groove group portion 588.
In the wiring groove group portion 588, the individual wiring width is narrow,
Since they are dense, the resist film thickness B becomes thicker.

Next, as shown in FIG.
From the state of (c), the resist of the wiring groove portion 586 and the wiring groove group portion 588 is exposed by the lithography method,
develop. At the time of this exposure and development, the non-uniformity and thickening of the resist film as described above cause the processing variations K, L, and M in the thick wiring groove group portion 588 of the resist film.

Next, as shown in FIG. 5E, the interlayer film 481 is etched using the resist 501 as a mask,
The interlayer connection hole 510 is formed. In this case, the etchant gas is not sufficiently supplied to the entire resist opening portion in the wiring groove group portion 588 where the resist opening depth is deep, and therefore, FIG.
As shown in (e) of (4), the shapes of the contact portions (P, Q, R) of the interlayer film 581 vary.

On the other hand, in order to make the resist film thicknesses A and B uniform, it is possible to apply a thicker resist. However, in this case, since the resist film thickness is increased as a whole,
The variation in processing during exposure and development increases, and the variation in processing during etching also increases.

In addition, in the manufacture of multilayer wiring in a semiconductor device in recent years, there are many factors that make it difficult to form an interlayer connection hole coexisting with a groove wiring. That is, the diameter of the inter-layer connection hole has become smaller with the miniaturization of the semiconductor device, and it is desirable that the thickness of the inter-layer film be set thicker in order to reduce the inter-layer wiring capacitance between the wirings. In order to reduce the above, it is required to design the wiring film to be as thick as possible (that is, the wiring groove is as deep as possible), which makes it difficult to suppress variations in processing.

[0010]

Due to the nonuniformity and thickening of the resist film as described above, the resist cannot be removed into a desired shape during exposure and development, resulting in variations in processing of interlayer connection holes. Was. An object of the present invention is to solve the above problems and to provide a method of manufacturing an interlayer connection hole which enables stable and easy processing of an interlayer connection hole coexisting with a groove wiring. I am trying.

[0011]

In order to achieve the above object, the present invention is to form a wiring groove in an interlayer film and apply a resist to the inside of the groove and the surface of the interlayer film until the groove is completely filled, The method is characterized by including a step of flattening and thinning the resist by polishing it so that the surface of the interlayer film is not exposed.

Since the resist in the portion where the interlayer connection hole is processed is flattened and thinned, it is possible to reduce unevenness and thickening of the resist film. Therefore, processing variations during exposure, development, and etching are reduced, and the interlayer film can be processed into a desired shape. As a result, it is possible to stably manufacture the interlayer connection hole for connecting the upper layer wiring and the lower layer wiring which are insulated from each other with a high yield.

Further, by using the flattening stopper film between the resist and the interlayer film, the film thickness of the resist finally left after polishing can be made sufficiently thin. Since it is possible to remove all of the above resist and leave the resist only in the wiring groove, it is possible to more reliably achieve the above object.

Further, the standing wave effect at the time of exposure can be suppressed by using the resist and the antireflection film in combination. Therefore, the removal of the malformation of the resist is further suppressed, and the achievement of the above object can be further ensured.

[0015]

1 (a) to 1 (e) is a first embodiment of the present invention. As shown in FIG. 1A, lower layer wirings 184 and 185 are provided in a lower layer portion 180 used to form a buried wiring and the like, and on top of that,
An interlayer film 181 made of an insulating film of silicon dioxide (hereinafter referred to as an oxide film) is formed. Next, a resist 100 is applied on the interlayer film 181, patterned by a lithography method, and then etched by a RIE method using this resist as a mask to form a wiring groove 102 and a wiring groove group 103. Here, the interlayer film 181 acts to insulate the wiring formed in the lower layer portion 180 from the wiring formed in the upper layer portion 182, the semiconductor element, and the like. In addition, the interlayer film 181
May be an insulating film such as BPSG.

Next, as shown in FIG. 1B, after removing the resist 100 for forming the wiring groove 102 and the wiring groove group 103, the resist 101 for forming the interlayer connection hole is recoated. At this time, the resist 101 to be applied is, until the wiring groove 102 and the wiring groove group 103 are completely filled,
Applied. The resist applied here may be a single-layer resist or a multi-layer resist. Further, as will be described below, since the resist 101 is flattened and thinned by polishing, the resist 100 may be flattened together with the resist 101 without being removed in advance.

Next, as shown in FIG. 1C, in order to reduce the unevenness and thickening of the resist 101,
The resist 101 for forming the interlayer connection hole is flattened. This flattening is performed by polishing with a CMP device or the like, and the film thickness Z of the resist above the interlayer film surface 191 is 1 μm.
m. The film thickness Z is determined by the relationship between the depth of the interlayer connection hole to be formed and the etching rate of the interlayer film and the etching rate of the resist.

Here, as shown in FIG. 1D, the interlayer connection hole forming resist 101 is polished until the interlayer film surface 191 is exposed, and then a new resist 190 is formed on the interlayer film surface 191. May be applied. The re-applied resist 190 may have any structure such as a single layer, a multi-layer resist, a single layer with an antireflection film, or a multi-layer resist. Further, as the planarization method, a method such as RIE or chemical etching using active species may be used.

Next, as shown in FIG.
In the state of (c) of FIG.
02 and wiring groove group 103 resist patterning,
By using this resist 101 as a mask, the interlayer film 1 is formed by the RIE method.
81 is etched to form an interlayer connection hole 120 having a desired shape. The etchant gas used during etching is, for example, silicon dioxide and BPS for the interlayer film 181.
In the case of G, a fluorine-based mixed gas is used.

Before applying the resist 101, an antireflection film may be applied inside the wiring groove 102 in order to suppress the standing wave effect. Further, after the resist 101 is flattened, an antireflection film may be applied on the flattened resist 101. The antireflection film may be applied both before the resist 101 is applied and after the resist 101 is flattened.

In this embodiment, since the resist 101 is flattened by polishing, it is possible to reduce unevenness and thickening of the resist 101 film. Therefore, it is possible to reduce the variation in processing of the interlayer connection hole 120 which has occurred conventionally, and it is possible to manufacture a multilayer wiring having higher reliability than the conventional one with a high yield.

The second embodiment is shown in FIGS. 2 (a) to 2 (f).
It was shown to. As shown in FIG. 2A, the lower layer wiring 2 is formed in the lower layer portion 280 used for forming the embedded wiring and the like.
84 and 285 are provided, an interlayer film 281 made of an oxide film is formed thereon, and a flattening stopper film 230 made of amorphous silicon is formed on the interlayer film 281 to a thickness of 0.
After being formed to a thickness of about 5 μm, a resist 200 is applied on the upper surface of the planarization stopper film 230 to a thickness of about 1 μm and patterned by a lithographic method. Using the resist 200 as a mask, the planarization stopper film 230 and the interlayer film 2 are formed.
81 is sequentially etched by the RIE method to form a wiring groove 202.
And the wiring groove group 203 is formed.

Next, as shown in FIG. 2B, as in the first embodiment, a resist 201 is applied so as to completely fill the wiring groove 202 and the wiring groove group 203. Next, as shown in FIG. 2C, the resist 201 is flattened and thinned by polishing the flattening stopper film 230 until it is exposed.

Further, as shown in FIG. 2D, this flattening may be stopped before the flattening stopper film 230 is exposed. Further, as shown in FIG. 2E, the resist 290 may be recoated after polishing until the planarization stopper film 230 is exposed.

The flattening stopper film is not amorphous silicon but silicon nitride, aluminum oxide,
Insulating film such as oxynitride, TiN, TaAlT
It may be i, W or an alloy containing a high melting point metal. Also,
This planarization method may use RIE or chemical etching using active species instead of polishing.

Next, as shown in FIG.
In the state of (c), patterning is performed by the lithography method, and the interlayer film 281 is R
Etching is performed by the IE method to form the interlayer connection hole 220. Further, the flattening stopper film 230 made of amorphous silicon has a property of conducting electricity and short-circuits the wirings, so it is removed after the above steps. If an insulating film such as silicon nitride, aluminum oxide, or oxynitride is used for the flattening stopper film, it need not be removed.

Further, in order to suppress the standing wave effect at the time of exposure, an antireflection film may be applied inside the wiring groove 202 before applying the resist 201. Also, the resist 2
After 01 is polished until the planarization stopper film 230 is exposed, an antireflection film may be applied on the planarized resist 201. The antireflection film may be applied both before the resist 201 is applied and after the resist 201 is flattened.

In this embodiment, since the resist exists only in the wiring groove, the resist film can be made uniform and can be made as thin as the depth of the wiring groove. Further, by using the antireflection film together, the resist 2 in the exposure in the interlayer connection hole forming step is formed.
Resistant wave in 01 is suppressed, and resist 201 is more reliable.
Can be processed into a desired shape. For these reasons, the interlayer connection holes for connecting the upper layer wiring and the lower layer wiring, which are insulated from each other, are manufactured more stably than in the case of the first embodiment, and there is no variation in the processing. It is possible to manufacture highly reliable multilayer wiring.

The third embodiment is shown in FIGS. 3A to 3D.
Shown in As shown in FIG. 3A, as in the first embodiment, the wiring groove 302 and the wiring groove group 30 are formed in the interlayer film 381.
3, a flattening stopper film 301 made of amorphous silicon is formed on the surface of the interlayer film 381, inside the wiring groove 302 and inside the wiring groove group 303 to a thickness of about 0.5 μm, and flattened until the groove is sufficiently filled. Stopper film 3
A resist 301 is applied on the surface 30.

Next, as shown in FIG. 3B, the resist 301 is formed so that the flattening stopper film 330 is not exposed.
Is flattened by polishing. Also, the resist 301
May be planarized until the planarization stopper film 330 is exposed, and then the resist may be recoated. Further, as the planarization method, a method such as RIE or chemical etching using active species may be used.

Next, as shown in FIG. 3C, the resist of the wiring groove 302 and the wiring groove group 303 is patterned by a lithography method, and the flattening stopper film on the bottom of the wiring groove 302 and the wiring groove group 303 is formed. Expose 330.

Next, as shown in FIG. 3D, in the state of FIG. 3C, the resist 301 is used as a mask and the planarizing stopper film 330 and the interlayer film 381 made of amorphous silicon are formed by RIE. Are sequentially etched to form an interlayer connection hole 320.

Further, the step of FIG.
Using 1 as a mask, only the flattening stopper film 330 made of amorphous silicon at the bottom of the wiring groove 302 and the wiring groove group 303 is etched by the RIE method, and then all the resist 301 is peeled off, and the flattening stopper film 330 is used as a mask. The interlayer film 381 may be etched to form the interlayer connection hole 320. .

Before applying the resist 301, an antireflection film may be applied to the flattening stopper film inside the wiring groove 302 and the wiring groove group 303 in order to suppress the standing wave effect. After the resist 301 is flattened, an antireflection film may be applied on the flattened resist 301. Further, the antireflection film may be applied both before the resist 301 is applied and after the resist 301 is flattened.

In this embodiment, since the resist 301 is flattened, it is possible to reduce the unevenness and thickening of the resist 301 film. For this reason, the interlayer connection hole 3 that has conventionally occurred
FIGS. 4A to 4D show a fourth embodiment in which it is possible to reduce the variation in processing of No. 20 and manufacture a multilayer wiring having higher reliability than the conventional one with a high yield. As shown in FIG. 4A, a thickness of 0.5 μm is formed on the surface of the interlayer film 481 in the upper layer portion 482 where the groove wiring and the groove wiring group are formed.
A flattening stopper film 430 having a thickness of about 4 μm is formed, a resist 400 having a thickness of about 1 μm is applied thereon, and a wiring groove 402 and a wiring groove group 403 are formed as in the second embodiment.

Next, as shown in FIG. 4B, the resist 400 is removed, and a barrier metal material 495 made of TiN is applied to the flattening stopper film in order to prevent disconnection of the groove wiring due to electromigration and stress migration. Deposited on 430, inside the wiring groove 402, and inside the wiring groove group 403. Thereafter, as described above, the resist 401 is applied until the wiring groove 402 and the wiring groove group 403 are sufficiently filled. Further, for the above reason, the resist 3 for forming the wiring groove 402 and the wiring groove group 403 is formed.
00 does not have to be removed.

Next, as shown in FIG. 4C, the resist 401 is planarized by polishing until the planarization stopper film 430 is exposed. Next, as shown in FIG. 4D, the barrier metal material 495 and the interlayer film 481 are sequentially etched by the RIE method using the resist 401 and the planarization stopper film 430 as a mask to form an interlayer connection hole 420. This barrier metal material 49
In the step of opening the interlayer connection hole following the etching of 5,
The resist 401 may be removed, and the interlayer film 420 may be etched using the barrier metal material 495 as a mask.

Before applying the resist 401, an antireflection film may be applied on the barrier metal material 495 in order to suppress the standing wave effect. In addition, the resist 40
1 may be planarized by polishing until the planarization stopper film 430 is exposed, and then an antireflection film may be applied onto the planarized resist 401. The antireflection film may be applied both before the resist 401 is applied and after the resist 401 is flattened.

In the present embodiment, since the barrier metal material 495 is used for the wiring groove portion 402 and the wiring groove group portion 403 in addition to the flattening stopper film 430, disconnection of the groove wiring due to electromigration and stress migration can be prevented. Further, by using the antireflection film together, the standing wave effect in the resist 401 during the exposure in the step of forming the interlayer connection hole is suppressed, and the resist 40 can be more reliably formed.
1 can be removed by development. For these reasons, it becomes possible to manufacture a multilayer wiring having higher reliability than the first, second, and third embodiments with a high yield.

[0040]

According to the present invention, by flattening the resist film, it is possible to reduce the unevenness and thickening of the resist film. Therefore, variations in the lithography process and the etching process are reduced. As a result, it is possible to stably manufacture the upper-layer wiring and the lower-layer wiring that are insulated from each other with a desired shape and size, and to obtain a highly reliable multi-layer wiring with no processing variations. It can be manufactured with a high yield.

[Brief description of the drawings]

FIG. 1 is a first embodiment of a manufacturing process of an interlayer connecting hole in a multilayer wiring according to the manufacturing method of the present invention.

FIG. 2 is a second embodiment diagram of a manufacturing process of an interlayer connection hole in a multilayer wiring by a manufacturing method of the present invention.

FIG. 3 is a diagram of a third embodiment of the manufacturing process of the interlayer connection hole in the multilayer wiring by the manufacturing method of the present invention.

FIG. 4 is a diagram of a fourth embodiment of the manufacturing process of the interlayer connection hole in the multilayer wiring by the manufacturing method of the present invention.

FIG. 5 is a manufacturing process drawing of an interlayer connection hole in a multilayer wiring by a conventional manufacturing method.

[Explanation of symbols]

182, 282, 382, 482, 582 ... Upper layer portion 180, 280, 380, 480, 580 ... Lower layer portion 184, 185, 284, 285, 384, 385, 4
84, 585 ... Lower layer wiring 181, 281, 381, 481, 581 ... Interlayer film 100, 190, 200, 400, 500 ... Resist 101, 201, 301, 401, 501 ... Resist 102, 202, 302, 402, 502 ... Wiring groove 103, 203, 303, 403, 503 ... Wiring groove group 586 ... Groove wiring portion 588 ... Groove wiring group portion A, B, Z ... Resist film thickness 191 ... Interlayer film surface 120, 220, 320, 420, 520 Interlayer connection hole AX Interlayer connection hole diameter BX Depth of wiring groove 230, 330, 530 Flattening stopper film 595 Barrier metal material

Claims (8)

[Claims] 1. A step of forming an interlayer film for insulating a first wiring layer and a second wiring layer, a step of forming a wiring groove in the interlayer film, and an interlayer film surface including the inside of the wiring groove. A step of coating a resist on the wiring groove and filling the inside of the wiring groove with a resist, a step of thinning and flattening the resist, a step of exposing and patterning the resist in the wiring groove portion, and a step of performing the patterning. A method for manufacturing an interlayer connection hole for multilayer wiring, comprising the step of etching the interlayer film using the resist as a mask to form an interlayer connection hole. 2. A step of forming an interlayer film for insulating the first wiring layer and the second wiring layer, a step of forming a planarization stopper film on the interlayer film, the interlayer film and the planarization. A step of forming a wiring groove in the stopper film, a step of applying a resist to the inside of the wiring groove and the surface of the flattening stopper film and filling the inside of the wiring groove with a resist, and exposing the resist film to the flattening stopper film Planarizing step, exposing the resist inside the groove to patterning, and etching the interlayer film using the patterned resist and the planarization stopper film as a mask to form an interlayer connection hole. A method of manufacturing an interlayer connection hole for multilayer wiring, comprising the steps of: 3. A step of forming an interlayer film for insulating the first wiring layer and the second wiring layer, a step of forming a wiring groove in the interlayer film, a surface of the interlayer film and the inside of the wiring groove. A step of forming a flattening stopper film on the surface, a step of applying a resist to the surface of the flattening stopper film including the inside of the wiring groove and filling the inside of the wiring groove with a resist, and a thin and flat resist film. And a step of exposing the resist inside the groove to perform patterning, a step of etching the flattening stopper film using the patterned resist as a mask, and a step of removing the patterned mask, A method of manufacturing an interlayer connection hole for multilayer wiring, comprising the step of etching the interlayer film using the flattening stopper film as a mask to form an interlayer connection hole. 4. The method according to claim 1, further comprising a step of applying an antireflection film on the flat surface after the step of flattening.
3. A method for manufacturing an interlayer connection hole for multilayer wiring as described in 3 above. 5. The method for manufacturing an interlayer connection hole for multilayer wiring according to claim 1, further comprising the step of applying an antireflection film inside the wiring groove after forming the wiring groove. 6. The method according to claim 3, further comprising a step of applying an antireflection film on the surface of the flattening stopper film inside the wiring groove after forming the flattening stopper film. Production method. 7. The interlayer connection for multilayer wiring according to claim 1, further comprising a step of applying an antireflection film on the inside of the wiring groove after forming the wiring groove and on the flat surface after the step of flattening. Method of making holes. 8. The method according to claim 3, further comprising a step of applying an antireflection film on the flattening stopper film inside the wiring groove and the flat surface after the step of flattening after the flattening stopper film is formed. Manufacturing method of interlayer connection hole for multilayer wiring.