JPH08236621A - Fabrication of semiconductor device - Google Patents
Fabrication of semiconductor deviceInfo
- Publication number
- JPH08236621A JPH08236621A JP7040648A JP4064895A JPH08236621A JP H08236621 A JPH08236621 A JP H08236621A JP 7040648 A JP7040648 A JP 7040648A JP 4064895 A JP4064895 A JP 4064895A JP H08236621 A JPH08236621 A JP H08236621A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- wiring
- barrier metal
- film
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Weting (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置の製造方法に
関し、特に多層配線形成方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a multi-layer wiring.
【０００２】[0002]
【従来の技術】従来溝を利用して配線を行うにあたって
は、図５（ａ），（ｂ）に示すように、層間絶縁膜２０
０１に配線用溝２００２をドライエッチングにより形成
し、配線用溝２００２を含む層間絶縁膜２００１の表面
に配線用メタル２００３を被着し、次いで化学機械研磨
ＣＭＰ法により配線用溝２００２を除く層間絶縁膜２０
０１上の配線用メタル２００３を除去し、溝２０００２
中にのみ配線用メタル２００３を残存させて配線を行っ
ていた（例えば、Ｊａｍｅｓ．Ｓ．Ｃｈｏ他、Ｉｎｔｅ
ｒｎａｔｉｏｎａｌ Ｅｌｅｃｔｒｏｎ Ｄｅｖｉｃｅ
ｓ Ｍｅｅｔｉｎｇ，１９９２，１１．４．１）。2. Description of the Related Art Conventionally, when wiring is performed using a groove, as shown in FIGS. 5 (a) and 5 (b), an interlayer insulating film 20 is formed.
A wiring groove 2002 is formed by dry etching at 01, a wiring metal 2003 is deposited on the surface of an interlayer insulating film 2001 including the wiring groove 2002, and then interlayer insulation except for the wiring groove 2002 is performed by a chemical mechanical polishing CMP method. Membrane 20
The metal 2003 for wiring on 01 is removed to form the groove 20002.
Wiring was carried out by leaving the metal 2003 for wiring only in the inside (for example, James. S. Cho et al., Inte.
national Electron Device
S Meeting, 1992, 11.4.1).
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、この方
法では層間絶縁膜２００１に配線用溝２００２をドライ
エッチングにより形成する際、そのドライエッチングを
自動的に停止するための基準となるストッパー層が層間
絶縁膜に設けられておらず、オペレータがドライエッチ
ングを勘により制御して配線用溝２００２を設けること
となるため、溝２００２の深さを設計値のものにコント
ロールすることは、非常に困難である。However, in this method, when the wiring trench 2002 is formed in the interlayer insulating film 2001 by dry etching, the stopper layer serving as a reference for automatically stopping the dry etching is the interlayer insulating film. Since it is not provided on the film and the operator controls the dry etching to provide the wiring groove 2002, it is very difficult to control the depth of the groove 2002 to a designed value. .
【０００４】一方、上述の困難を回避する目的で特開平
１−１２８５２８号で提案された方法が在る。その方法
は図５（ｃ）に示すように溝２００７の深さに対応させ
て層間絶縁膜２００６にバリアメタル２００５を被着
し、かつバリアメタル２００５をパターニングして溝２
００７の底部にのみ残留させる。On the other hand, there is a method proposed in JP-A-1-128528 for the purpose of avoiding the above-mentioned difficulties. As shown in FIG. 5C, the method involves depositing a barrier metal 2005 on the interlayer insulating film 2006 corresponding to the depth of the groove 2007, and patterning the barrier metal 2005 to form the groove 2
Remain only at the bottom of 007.
【０００５】次に層間絶縁膜２００６をドライエッチン
グして溝２００７を形成し、溝２００７内にバリアメタ
ル２００５が露出した時点でドライエッチングを終了さ
せていた。Next, the interlayer insulating film 2006 is dry-etched to form a groove 2007, and the dry etching is terminated when the barrier metal 2005 is exposed in the groove 2007.
【０００６】しかしながら、上述した従来の方法では、
バリアメタル２００５をパターニングする際と、溝２０
０７を開孔させる際とでそれぞれ目合わせ露光を行う必
要があり、この方法では、配線溝形成に２回の目合わせ
露光が必要であり、多層配線形成の工程数が増加すると
いう問題点があった。However, in the above-mentioned conventional method,
When patterning the barrier metal 2005 and the groove 20.
It is necessary to perform the aligning exposure when opening the hole 07, and this method requires two aligning exposures for forming the wiring groove, which causes a problem that the number of steps for forming the multilayer wiring increases. there were.
【０００７】本発明の目的は、目合わせ露光回数を増加
させることなく、配線用溝の深さを自動的に制御する半
導体装置の製造方法を提供することにある。An object of the present invention is to provide a method of manufacturing a semiconductor device in which the depth of a wiring groove is automatically controlled without increasing the number of aligning exposures.
【０００８】[0008]
【課題を解決するための手段】前記目的を達成するた
め、本発明に係る半導体装置の製造方法は、埋設工程
と、パターニング工程と、堆積工程と、溝形成工程と、
配線形成工程とを有し、絶縁膜の配線用溝内に配線を形
成する半導体装置の製造方法であって、埋設工程は、第
１の絶縁膜上にバリアメタルを被着し、その上に第２の
絶縁膜を形成することにより、バリアメタルを第１の絶
縁膜内に埋設するものであり、パターニング工程は、前
記バリアメタル上の第２の絶縁膜を配線形状に加工し、
該配線形状の絶縁膜をマスクとして前記バリアメタルを
配線形状にパターニング加工するものであり、堆積工程
は、前記配線形状に加工された第２の絶縁膜及びバリア
メタルの周囲に第３の絶縁膜を堆積するものであり、溝
形成工程は、前記第３の絶縁膜を残して前記バリアメタ
ル上の第２の絶縁膜を除去し、バリアメタルを底部とす
る配線用溝を形成するものであり、配線形成工程は、前
記配線用溝内にメタルを充填して配線を形成するもので
ある。In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention comprises a burying step, a patterning step, a depositing step, a groove forming step,
A method of manufacturing a semiconductor device, comprising: forming a wiring in a wiring groove of an insulating film, wherein the burying step includes depositing a barrier metal on the first insulating film, and forming a barrier metal on the first insulating film. The barrier metal is embedded in the first insulating film by forming the second insulating film, and the patterning step processes the second insulating film on the barrier metal into a wiring shape,
The barrier metal is patterned into a wiring shape by using the wiring-shaped insulating film as a mask. In the deposition step, a third insulating film is formed around the second insulating film and the barrier metal processed into the wiring shape. In the groove forming step, the second insulating film on the barrier metal is removed while leaving the third insulating film, and a wiring groove having the barrier metal as a bottom is formed. In the wiring forming step, wiring is formed by filling the wiring groove with metal.
【０００９】また、前記埋設工程から配線形成工程に至
る一連の処理を繰返し行い、多層の絶縁膜に設けた配線
用溝を利用して多層に配線を形成するものである。Further, a series of processes from the burying step to the wiring forming step are repeatedly performed to form wiring in multiple layers by utilizing the wiring grooves provided in the multilayer insulating film.
【００１０】また、前記第１及び第２の絶縁膜は、リン
或いはボロンを含有するシリコン酸化膜、またはプラズ
マ気相成長法によるシリコン酸化膜であり、前記第３の
絶縁膜は、ポリイミド膜である。Further, the first and second insulating films are silicon oxide films containing phosphorus or boron or silicon oxide films formed by plasma vapor deposition, and the third insulating film is a polyimide film. is there.
【００１１】また、前記第１及び第３の絶縁膜は、リン
或いはボロンを含有するシリコン酸化膜、またはプラズ
マ気相成長法によるシリコン酸化膜であり、前記第２の
絶縁膜は、ポリイミド膜である。The first and third insulating films are silicon oxide films containing phosphorus or boron, or silicon oxide films formed by plasma vapor deposition, and the second insulating film is a polyimide film. is there.
【００１２】また、前記第２の絶縁膜上に付着する余分
な第３の絶縁膜を化学機械研磨ＣＭＰ法により除去し、
第２の絶縁膜の表面を完全に露出するものである。Excessive third insulating film adhered on the second insulating film is removed by a chemical mechanical polishing CMP method,
The surface of the second insulating film is completely exposed.
【００１３】また、前記第２の絶縁膜上に付着する余分
な第３の絶縁膜をドライエッチングによるエッチバック
法で除去し、第２の絶縁膜の表面を完全に露出するもの
である。Further, the excess third insulating film attached on the second insulating film is removed by an etch back method by dry etching to completely expose the surface of the second insulating film.
【００１４】また、前記第３の絶縁膜上に付着する余分
な配線用のメタルを化学機械研磨ＣＭＰ法により除去す
るものである。Further, excess wiring metal adhering to the third insulating film is removed by a chemical mechanical polishing CMP method.
【００１５】また、前記第３の絶縁膜上に付着する余分
な配線用のメタルをドライエッチングによるエッチバッ
ク法で除去するものである。Further, the excess wiring metal adhering to the third insulating film is removed by an etch back method by dry etching.
【００１６】[0016]
【作用】バリアメタル上の第２の絶縁膜を配線形状に加
工し、配線形状の第２の絶縁膜をマスクとしてバリアメ
タルを配線形状にパターニング加工する。本発明では、
上記パターニング工程においてのみ目合わせ露光技術を
用いる。The second insulating film on the barrier metal is processed into a wiring shape, and the barrier metal is patterned into a wiring shape using the wiring-shaped second insulating film as a mask. In the present invention,
The aligning exposure technique is used only in the patterning step.
【００１７】後工程ではパターニング加工されたバリア
メタル周囲への絶縁膜の堆積処理、及びバリアメタル上
の絶縁膜の除去処理並びにバリアメタル上への配線形成
処理を行う。この各処理は目合わせ露光技術を用いる必
要がなく、工数を増加させることはない。In a subsequent step, a process of depositing an insulating film around the patterned barrier metal, a process of removing the insulating film on the barrier metal, and a process of forming a wiring on the barrier metal are performed. It is not necessary to use the aligning exposure technique for each of these processes, and the number of steps is not increased.
【００１８】[0018]
【実施例】以下、本発明の実施例を図により説明する。Embodiments of the present invention will be described below with reference to the drawings.
【００１９】（実施例１）図１，図２，図３は、本発明
の実施例１を工程順に示す断面図である。(Embodiment 1) FIGS. 1, 2 and 3 are sectional views showing Embodiment 1 of the present invention in the order of steps.
【００２０】図において、本発明に係る半導体装置の製
造方法は、基本的構成として、埋設工程と、パターニン
グ工程と、堆積工程と、溝形成工程と、配線形成工程と
を有し、絶縁膜の配線用溝内に配線を形成するものであ
る。各工程について説明すると、埋設工程は、第１の絶
縁膜上にバリアメタルを被着し、その上に第２の絶縁膜
を形成することにより、バリアメタルを第１の絶縁膜内
に埋設するものである。In the figure, the method of manufacturing a semiconductor device according to the present invention has a basic structure including an embedding step, a patterning step, a depositing step, a groove forming step, and a wiring forming step. The wiring is formed in the wiring groove. Explaining each step, in the embedding step, a barrier metal is deposited on the first insulating film, and a second insulating film is formed on the barrier metal, thereby embedding the barrier metal in the first insulating film. It is a thing.
【００２１】またパターニング工程は、前記バリアメタ
ル上の第２の絶縁膜を配線形状に加工し、該配線形状の
絶縁膜をマスクとして前記バリアメタルを配線形状にパ
ターニング加工するものである。In the patterning step, the second insulating film on the barrier metal is processed into a wiring shape, and the barrier metal is patterned into a wiring shape using the wiring-shaped insulating film as a mask.
【００２２】また堆積工程は、前記配線形状に加工され
た第２の絶縁膜及びバリアメタルの周囲に第３の絶縁膜
を堆積するものである。In the deposition step, a third insulating film is deposited around the second insulating film and the barrier metal processed into the wiring shape.
【００２３】また溝形成工程は、前記第３の絶縁膜を残
して前記バリアメタル上の第２の絶縁膜を除去し、バリ
アメタルを底部とする配線用溝を形成するものであり、
配線形成工程は、前記配線用溝内にメタルを充填して配
線を形成するものである。In the groove forming step, the second insulating film on the barrier metal is removed leaving the third insulating film to form a wiring groove having the barrier metal as a bottom portion.
In the wiring forming step, the wiring is formed by filling the wiring groove with metal.
【００２４】前記第１及び第２の絶縁膜は、リン或いは
ボロンを含有するシリコン酸化膜（ＰＳＧあるいはＢＰ
ＳＧ膜）、またはプラズマ気相成長法によるシリコン酸
化膜（ＰＥＣＶＤ−ＳｉＯＰＥＣＶＤ−ＳｉＯ2）であ
り、前記第３の絶縁膜は、ポリイミド膜である、または
前記第１及び第３の絶縁膜は、リン或いはボロンを含有
するシリコン酸化膜（ＰＳＧあるいはＢＰＳＧ膜）、ま
たはプラズマ気相成長法によるシリコン酸化膜（ＰＥＣ
ＶＤ−ＳｉＯＰＥＣＶＤ−ＳｉＯ2）であり、前記第２
の絶縁膜は、ポリイミド膜である。The first and second insulating films are silicon oxide films (PSG or BP) containing phosphorus or boron.
SG film) or a silicon oxide film (PECVD-SiOPECVD-SiO 2 ) formed by plasma vapor deposition, the third insulating film is a polyimide film, or the first and third insulating films are Silicon oxide film containing phosphorus or boron (PSG or BPSG film) or silicon oxide film by plasma vapor deposition (PEC)
VD-SiOPECVD-SiO 2 ) and the second
The insulating film is a polyimide film.
【００２５】次に第１及び第２の絶縁膜としてＢＰＳＧ
膜、第３の絶縁膜としてポリイミド膜をそれぞれ用いた
場合の具体的な例により本発明を説明する。Next, BPSG is used as the first and second insulating films.
The present invention will be described with reference to specific examples in which polyimide films are used as the film and the third insulating film.
【００２６】まず図１（ａ）に示すように１μｍのＢＰ
ＳＧ膜（第１の絶縁膜）１００上に膜厚１０００Åのバ
リアメタルとしてタングステン（Ｗ）１１０をスパッタ
被着し、さらに膜厚１μｍのＢＰＳＧ膜（第２の絶縁
膜）１２０を堆積する。次に上層のＢＰＳＧ膜１２０上
にフォトレジスト１３０を塗布し、目合わせ露光技術に
よりフォトレジスト１３０を配線パターン形状に形成す
る。First, as shown in FIG. 1 (a), 1 μm BP is used.
On the SG film (first insulating film) 100, a tungsten (W) 110 is deposited as a barrier metal having a film thickness of 1000Å by sputtering, and a BPSG film (second insulating film) 120 having a film thickness of 1 μm is further deposited. Next, a photoresist 130 is applied on the upper BPSG film 120, and the photoresist 130 is formed into a wiring pattern shape by the aligning exposure technique.
【００２７】次に図１（ｂ）に示すように配線パターン
形状のフォトレジスト１３０をマスクとしてＢＰＳＧ膜
１２０とバリアメタル１１０をドライエッチングにより
パターニングし、配線パターン形状のＢＰＳＧ膜１２０
Ａとバリアメタル１１０Ａを得る。Next, as shown in FIG. 1B, the BPSG film 120 and the barrier metal 110 are patterned by dry etching using the photoresist 130 having a wiring pattern shape as a mask, and the BPSG film 120 having a wiring pattern shape.
A and barrier metal 110A are obtained.
【００２８】次に図１（ｃ）に示すように配線パターン
形状のＢＰＳＧ膜１２０Ａ上に残留したフォトレジスト
１３０を除去した後、ポリイミド膜（第３の絶縁膜）１
４０をＢＰＳＧ膜１００上のＢＰＳＧ膜１２０Ａ及びバ
リアメタル１１０Ａの周囲に２μｍ塗布しベークを行
う。Next, as shown in FIG. 1C, after removing the photoresist 130 remaining on the wiring pattern shaped BPSG film 120A, a polyimide film (third insulating film) 1 is formed.
40 is applied to the periphery of the BPSG film 120A and the barrier metal 110A on the BPSG film 100 by 2 μm and baked.
【００２９】次に図２（ｄ）に示すように化学機械研磨
ＣＭＰ法によりポリイミド膜１４０を約１μｍ研磨し、
ＢＰＳＧ膜１２０Ａの表面を完全に露出させる。Next, as shown in FIG. 2D, the polyimide film 140 is polished by about 1 μm by the chemical mechanical polishing CMP method,
The surface of the BPSG film 120A is completely exposed.
【００３０】次に図２（ｅ）に示すように表面が露出し
たＢＰＳＧ膜１２０Ａをフッ酸を用いたエッチング法に
より選択的に除去する。ポリイミド膜１４０Ａ並びにバ
リアメタル１１０Ａは、フッ酸ではエッチングされない
ため、ＢＰＳＧ膜１２０Ａのみを選択的に除去すること
が可能となり、バリアメタル１１０Ａを底部とする配線
用溝が形成される。Next, as shown in FIG. 2E, the exposed BPSG film 120A is selectively removed by an etching method using hydrofluoric acid. Since the polyimide film 140A and the barrier metal 110A are not etched with hydrofluoric acid, only the BPSG film 120A can be selectively removed, and a wiring groove having the barrier metal 110A as the bottom is formed.
【００３１】次に図２（ｆ）に示すようにＣｕ（銅）膜
１５０をポリイミド膜１４０Ａの表面及びポリイミド膜
１４０Ａ間の配線用溝内に２μｍ被着する。Next, as shown in FIG. 2F, a Cu (copper) film 150 is deposited by 2 μm on the surface of the polyimide film 140A and in the wiring groove between the polyimide films 140A.
【００３２】最終的にＣｕ膜１５０を化学機械研磨ＣＭ
Ｐ法により配線用溝内にのみ残存させることにより、配
線用溝内に埋設されたＣｕ配線１５０Ａを形成する。Finally, the Cu film 150 is subjected to chemical mechanical polishing CM.
The Cu wiring 150A embedded in the wiring groove is formed by leaving it only in the wiring groove by the P method.
【００３３】尚、余分なポリイミド膜（第３の絶縁膜）
１４０をドライエッチングによるエッチバック法で除去
してもよく、また配線用溝以外の不要なＣｕ膜１５０を
除去するにあたっては、ドライエッチングによるエッチ
バック法を用いてもよい。An extra polyimide film (third insulating film)
140 may be removed by an etch-back method by dry etching, and an etch-back method by dry etching may be used to remove the unnecessary Cu film 150 other than the wiring trench.
【００３４】（実施例２）図４は本発明の実施例２を示
す断面図である。さらに本発明は、前記埋設工程から配
線形成工程に至る一連の処理を繰返し行い、多層の絶縁
膜に設けた配線用溝を利用して多層に配線を形成するよ
うにしてもよく、本発明の実施例を図４に示す。図４に
示す実施例では、実施例１の方法を基本的に使用するこ
とにより２層のＣｕ配線を形成したものである。すなわ
ち、実施例１に示す１層のＣｕ配線１０５Ａを形成した
後、プラズマ酸化膜（第１の絶縁膜）２００を約１μｍ
被着し、プラズマ酸化膜２００にスルーホール２１０を
開口し、スルーホール２１０の内周面及びプラズマ酸化
膜２００の表面にバリアメタル２０５を被着した後、実
施例１で示したと同様の方法で第２の絶縁膜をバリアメ
タル２０５上に堆積し、第２の絶縁膜とバリアメタル２
０５を配線パターン形状にパターニングし、さらに第３
の絶縁膜としてのポリイミド膜２３０Ａを形成し、その
後ポリイミド膜２３０Ａで取り囲まれた第２の絶縁膜を
バリアメタル２０５が露出するまで除去し配線用溝を形
成し、その溝及びスルーホール２１０内にＣｕ膜２２０
を充填し、２層目のＣｕ配線２２０を形成したものであ
る。尚、配線用溝を利用して多層配線を形成するにあた
っては、図４に示される２層のものに限定されるもので
はなく、２層以上設けてもよい。(Embodiment 2) FIG. 4 is a sectional view showing Embodiment 2 of the present invention. Further, in the present invention, a series of processes from the burying step to the wiring forming step may be repeated to form the wiring in multiple layers by utilizing the wiring grooves provided in the multilayer insulating film. An example is shown in FIG. In the embodiment shown in FIG. 4, two layers of Cu wiring are formed by basically using the method of the first embodiment. That is, after forming the one-layer Cu wiring 105A shown in Example 1, the plasma oxide film (first insulating film) 200 is formed to a thickness of about 1 μm.
After deposition, a through hole 210 is opened in the plasma oxide film 200, a barrier metal 205 is deposited on the inner peripheral surface of the through hole 210 and the surface of the plasma oxide film 200, and then the same method as that described in Example 1 is used. A second insulating film is deposited on the barrier metal 205, and the second insulating film and the barrier metal 2 are deposited.
05 is patterned into a wiring pattern shape,
Forming a polyimide film 230A as an insulating film, and then removing the second insulating film surrounded by the polyimide film 230A until the barrier metal 205 is exposed to form a wiring groove, and in the groove and the through hole 210. Cu film 220
To form a second layer of Cu wiring 220. It should be noted that when forming a multilayer wiring using the wiring groove, it is not limited to the two layers shown in FIG. 4, and two or more layers may be provided.
【００３５】[0035]
【発明の効果】以上説明したように本発明によれば、一
回の目合わせ露光で溝配線を形成することができる。ま
た、配線埋設用溝の深さをドライエッチング時に自動的
に制御して形成することができる。さらに、ドライエッ
チングによる微細加工の困難なポリイミド膜中に、直接
ポリイミド膜をエッチングすることなく微細な配線用溝
を形成することができ、比誘電率の低いポリイミド膜を
層間膜として使用することができるという効果がある。As described above, according to the present invention, it is possible to form the groove wiring by a single aligning exposure. Further, the depth of the wiring burying groove can be automatically controlled and formed during dry etching. Further, it is possible to form fine wiring grooves in a polyimide film which is difficult to be micromachined by dry etching without directly etching the polyimide film, and it is possible to use a polyimide film having a low relative dielectric constant as an interlayer film. The effect is that you can do it.
【図１】本発明の実施例１を工程順に示す断面図であ
る。FIG. 1 is a cross-sectional view showing a first embodiment of the present invention in process order.
【図２】本発明の実施例１を工程順に示す断面図であ
る。FIG. 2 is a cross-sectional view showing the first embodiment of the present invention in the order of steps.
【図３】本発明の実施例１を工程順に示す断面図であ
る。FIG. 3 is a cross-sectional view showing the first embodiment of the present invention in the order of steps.
【図４】本発明の実施例２を示す断面図である。FIG. 4 is a sectional view showing a second embodiment of the present invention.
【図５】従来例を示す断面図である。FIG. 5 is a cross-sectional view showing a conventional example.
１００，１２０，１２０Ａ ＢＰＳＧ膜 １１０，１１０Ａ，２０５ タングステン（バリアメタ
ル） １３０ フォトレジスト １５０，１５０Ａ，２２０ Ｃｕ膜 １４０，１４０Ａ，２３０Ａ ポリイミド膜 ２１０ スルーホール ２００１ 層間絶縁膜 ２００２ 配線用溝 ２００３ 配線用メタル100, 120, 120A BPSG film 110, 110A, 205 Tungsten (barrier metal) 130 Photoresist 150, 150A, 220 Cu film 140, 140A, 230A Polyimide film 210 Through hole 2001 Interlayer insulating film 2002 Wiring groove 2003 Wiring metal
Claims (8)
工程と、溝形成工程と、配線形成工程とを有し、絶縁膜
の配線用溝内に配線を形成する半導体装置の製造方法で
あって、 埋設工程は、第１の絶縁膜上にバリアメタルを被着し、
その上に第２の絶縁膜を形成することにより、バリアメ
タルを第１の絶縁膜内に埋設するものであり、 パターニング工程は、前記バリアメタル上の第２の絶縁
膜を配線形状に加工し、該配線形状の絶縁膜をマスクと
して前記バリアメタルを配線形状にパターニング加工す
るものであり、 堆積工程は、前記配線形状に加工された第２の絶縁膜及
びバリアメタルの周囲に第３の絶縁膜を堆積するもので
あり、 溝形成工程は、前記第３の絶縁膜を残して前記バリアメ
タル上の第２の絶縁膜を除去し、バリアメタルを底部と
する配線用溝を形成するものであり、 配線形成工程は、前記配線用溝内にメタルを充填して配
線を形成するものであることを特徴とする半導体装置の
製造方法。1. A method of manufacturing a semiconductor device, comprising a burying step, a patterning step, a depositing step, a groove forming step, and a wiring forming step, wherein a wiring is formed in a wiring groove of an insulating film. In the burying step, a barrier metal is deposited on the first insulating film,
By forming a second insulating film on the barrier metal, the barrier metal is embedded in the first insulating film. In the patterning step, the second insulating film on the barrier metal is processed into a wiring shape. The barrier metal is patterned into a wiring shape by using the wiring-shaped insulating film as a mask, and the deposition step includes a third insulation film around the second insulating film and the barrier metal processed into the wiring shape. A film is deposited. In the groove forming step, the second insulating film on the barrier metal is removed while leaving the third insulating film, and a wiring groove having the barrier metal as a bottom is formed. In the method for manufacturing a semiconductor device, the wiring forming step is to fill the inside of the wiring groove with metal to form a wiring.
連の処理を繰返し行い、多層の絶縁膜に設けた配線用溝
を利用して多層に配線を形成するものであることを特徴
とする請求項１に記載の半導体装置の製造方法。2. A wiring is formed in multiple layers by utilizing a wiring groove provided in a multilayer insulating film by repeating a series of processes from the burying step to the wiring forming step. Item 2. A method of manufacturing a semiconductor device according to item 1.
はボロンを含有するシリコン酸化膜、またはプラズマ気
相成長法によるシリコン酸化膜であり、 前記第３の絶縁膜は、ポリイミド膜であることを特徴と
する請求項１に記載の半導体装置の製造方法。3. The first and second insulating films are silicon oxide films containing phosphorus or boron or silicon oxide films formed by plasma vapor deposition, and the third insulating film is a polyimide film. The method for manufacturing a semiconductor device according to claim 1, wherein there is.
はボロンを含有するシリコン酸化膜、またはプラズマ気
相成長法によるシリコン酸化膜であり、 前記第２の絶縁膜は、ポリイミド膜であることを特徴と
する請求項１に記載の半導体装置の製造方法。4. The first and third insulating films are silicon oxide films containing phosphorus or boron, or silicon oxide films formed by plasma vapor deposition, and the second insulating film is a polyimide film. The method for manufacturing a semiconductor device according to claim 1, wherein there is.
３の絶縁膜を化学機械研磨ＣＭＰ法により除去し、第２
の絶縁膜の表面を完全に露出することを特徴とする請求
項１に記載の半導体装置の製造方法。5. Excessive third insulating film adhering to the second insulating film is removed by a chemical mechanical polishing CMP method,
The method for manufacturing a semiconductor device according to claim 1, wherein the surface of the insulating film is completely exposed.
３の絶縁膜をドライエッチングによるエッチバック法で
除去し、第２の絶縁膜の表面を完全に露出することを特
徴とする請求項１に記載の半導体装置の製造方法。6. The excess third insulating film adhering to the second insulating film is removed by an etch-back method by dry etching to completely expose the surface of the second insulating film. The method for manufacturing a semiconductor device according to claim 1.
線用のメタルを化学機械研磨ＣＭＰ法により除去するこ
とを特徴とする請求項１に記載の半導体装置の製造方
法。7. The method of manufacturing a semiconductor device according to claim 1, wherein excess wiring metal adhering to the third insulating film is removed by a chemical mechanical polishing CMP method.
線用のメタルをドライエッチングによるエッチバック法
で除去することを特徴とする請求項１に記載の半導体装
置の製造方法。8. The method of manufacturing a semiconductor device according to claim 1, wherein the excess wiring metal adhering to the third insulating film is removed by an etch back method by dry etching.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7040648A JPH08236621A (en) | 1995-02-28 | 1995-02-28 | Fabrication of semiconductor device |
| KR1019960005632A KR960032617A (en) | 1995-02-28 | 1996-02-28 | Method for forming interconnections of semiconductor devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7040648A JPH08236621A (en) | 1995-02-28 | 1995-02-28 | Fabrication of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH08236621A true JPH08236621A (en) | 1996-09-13 |
Family
ID=12586381
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7040648A Pending JPH08236621A (en) | 1995-02-28 | 1995-02-28 | Fabrication of semiconductor device |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPH08236621A (en) |
| KR (1) | KR960032617A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105084303A (en) * | 2014-05-21 | 2015-11-25 | 上海蓝沛新材料科技股份有限公司 | Micro-nano copper wire and preparation method thereof |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100487476B1 (en) * | 1997-05-23 | 2005-09-16 | 삼성전자주식회사 | Method of forming semiconductor devices and semiconductor devices formed thereby |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02114639A (en) * | 1988-10-25 | 1990-04-26 | Seiko Epson Corp | Semiconductor device |
| JPH03244126A (en) * | 1990-02-22 | 1991-10-30 | Toshiba Corp | Manufacture of semiconductor device |
| JPH04290249A (en) * | 1991-03-19 | 1992-10-14 | Nec Corp | Manufacture of semiconductor device |
| JPH06177126A (en) * | 1992-12-01 | 1994-06-24 | Alps Electric Co Ltd | Formation of multilayer thin film |
| JPH06275612A (en) * | 1993-03-19 | 1994-09-30 | Fujitsu Ltd | Manufacture of integrated circuit device |
-
1995
- 1995-02-28 JP JP7040648A patent/JPH08236621A/en active Pending
-
1996
- 1996-02-28 KR KR1019960005632A patent/KR960032617A/en active IP Right Grant
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02114639A (en) * | 1988-10-25 | 1990-04-26 | Seiko Epson Corp | Semiconductor device |
| JPH03244126A (en) * | 1990-02-22 | 1991-10-30 | Toshiba Corp | Manufacture of semiconductor device |
| JPH04290249A (en) * | 1991-03-19 | 1992-10-14 | Nec Corp | Manufacture of semiconductor device |
| JPH06177126A (en) * | 1992-12-01 | 1994-06-24 | Alps Electric Co Ltd | Formation of multilayer thin film |
| JPH06275612A (en) * | 1993-03-19 | 1994-09-30 | Fujitsu Ltd | Manufacture of integrated circuit device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105084303A (en) * | 2014-05-21 | 2015-11-25 | 上海蓝沛新材料科技股份有限公司 | Micro-nano copper wire and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| KR960032617A (en) | 1996-09-17 |
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