KR100487476B1 - Method of forming semiconductor devices and semiconductor devices formed thereby - Google Patents
Method of forming semiconductor devices and semiconductor devices formed thereby Download PDFInfo
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- KR100487476B1 KR100487476B1 KR1019970020372A KR19970020372A KR100487476B1 KR 100487476 B1 KR100487476 B1 KR 100487476B1 KR 1019970020372 A KR1019970020372 A KR 1019970020372A KR 19970020372 A KR19970020372 A KR 19970020372A KR 100487476 B1 KR100487476 B1 KR 100487476B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76846—Layer combinations
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by physical means, e.g. sputtering, evaporation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
Abstract
본 발명은 반도체장치의 제조방법 및 그에 따라 제조되는 반도체장치에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device manufactured accordingly.
본 발명은, 반도체장치의 제조방법에 있어서, 반도체 기판 상의 소정의 영역에 경계금속막을 형성시키는 경계금속막형성단계 및 상기 소정의 영역에 형성된 경계금속막이 노출되도록 반도체 기판 상에 아이엘디막을 형성시키는 아이엘디막형성단계를 구비하여 이루어짐을 특징으로 한다.In the method of manufacturing a semiconductor device, a boundary metal film forming step of forming a boundary metal film in a predetermined region on a semiconductor substrate, and forming an IEL film on the semiconductor substrate so that the boundary metal film formed in the predetermined region is exposed. It is characterized by comprising the IEL film forming step.
또한 본 발명의 반도체장치는, 금속막이 접촉되는 반도체 기판 상의 제 1 영역에 경계금속막을 구비하여 이루어짐을 특징으로 한다.In addition, the semiconductor device of the present invention is characterized in that the boundary metal film is provided in the first region on the semiconductor substrate to which the metal film is in contact.
따라서, 충분한 스텝 커버리지를 확보할 수 있고, 또한 불량을 방지할 수 있어 제품의 신뢰도가 향상되는 효과가 있다.Therefore, sufficient step coverage can be ensured and a defect can be prevented and the reliability of a product improves.
Description
본 발명은 반도체장치의 제조방법 및 그에 따라 제조되는 반도체장치에 관한 것으로서, 보다 상세하게는 반도체 기판 상에 콘택 홀(Contact Hole)이 형성되는 영역의 저부에 경계금속막(Barrier Metal Film)을 구비하는 반도체장치의 제조방법 및 그에 따라 제조되는 반도체장치에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device manufactured according to the present invention. More particularly, a barrier metal film is provided at a bottom of a region where a contact hole is formed on a semiconductor substrate. It relates to a method for manufacturing a semiconductor device and a semiconductor device manufactured accordingly.
일반적으로 반도체장치의 제조는 주로 실리콘(Si)으로 이루어지는 반도체 기판을 이용하여 성막공정, 사진식각공정, 불순물주입공정 및 금속공정 등을 수행하여 소자의 특성에 따른 패턴(Pattern)을 형성시킴으로써 이루어진다.In general, a semiconductor device is manufactured by forming a pattern according to the characteristics of a device by performing a film forming process, a photolithography process, an impurity implantation process and a metal process using a semiconductor substrate mainly made of silicon (Si).
여기서 상기 금속공정은 반도체장치의 제조공정 중 마지막 단계에서 수행되는 공정으로써 소자들의 전기적인 접촉, 소자들의 전기적인 연결 또는 외부와의 전기적인 연결 등의 기능을 수행하는 금속막(Metal Film)을 형성시킨다.Here, the metal process is a process performed in the last step of the manufacturing process of the semiconductor device to form a metal film (Metal Film) that performs a function such as electrical contact of the elements, electrical connection of the elements or electrical connection to the outside. Let's do it.
이러한 금속공정은 주로 고온의 온도분위기 중에서 수행되고, 고온의 공정수행시, 반도체 기판 상에 형성되는 금속막이 안정화되기 위하여 상기 반도체 기판과 금속막의 계면에서는 반도체 기판을 이루고 있는 실리콘 원자들이 금속막으로 이동하는 물질이동이 일어났고, 이러한 물질이동으로 인하여 반도체 기판에는 피팅(Pitting)현상이 일어나고, 상기 피팅현상에 의해 정션 스파이크(Junction Spike) 등과 같은 불량이 발생하였다.The metal process is mainly performed in a high temperature atmosphere, and during the high temperature process, silicon atoms constituting the semiconductor substrate move to the metal film at the interface between the semiconductor substrate and the metal film to stabilize the metal film formed on the semiconductor substrate. The material movement occurs, and the material movement causes a fitting phenomenon on the semiconductor substrate, and a defect such as a junction spike occurs due to the fitting phenomenon.
이에 따라 상기 정션 스파이크 등과 같은 불량을 방지하고저 최근에는 반도체 기판 상에 경계금속막을 형성시켜 물질이동을 방지하였다.Accordingly, defects such as the junction spike and the like are prevented, and recently, a boundary metal film is formed on the semiconductor substrate to prevent material movement.
이러한 상기 경계금속막을 구비하는 금속막의 제조공정은 먼저, 반도체 기판 상에 콘택 홀을 형성시킨 후, 상기 콘택 홀을 포함하는 반도체 기판 상에 상기 경계금속막을 형성시키고, 그 상부에 금속막을 형성시켰다.In the process of manufacturing a metal film including the boundary metal film, first, a contact hole is formed on a semiconductor substrate, and then the boundary metal film is formed on a semiconductor substrate including the contact hole, and a metal film is formed thereon.
즉, 종래에는 반도체 기판 상에 콘택 홀을 형성시킨 후, 경계금속막을 형성시키는 것으로써, 상기 경계금속막을 콘택 홀이 형성된 저부 뿐만아니라 상기 콘택 홀의 양측벽에도 형성시켰다.That is, conventionally, by forming a contact hole on a semiconductor substrate and then forming a boundary metal film, the boundary metal film was formed not only at the bottom of the contact hole but also at both side walls of the contact hole.
여기서 고집적화, 고밀도화 되어가는 최근의 반도체장치는 상기 콘택 홀의 종횡비(Aspcet Ratio)가 커져가는 추세이고, 또한 상기 콘택 홀의 스텝 커버리지(Step Coverage)의 확보가 중요시 되고 있다.In recent years, as the integration and density of semiconductor devices are increasing, the aspect ratio of the contact hole is increasing, and it is important to secure the step coverage of the contact hole.
그러나 최근의 반도체장치는 고집적화, 고밀도화 되어감으로 인해 상기 콘택 홀의 종횡비가 커져 갈 뿐만 아니라 상기 콘택 홀을 형성하는 복합막인 아이엘디막(ILD Film : Inter Layer Dielectric Film)의 단차로 인하여 상기 스텝 커버리지의 확보가 용이하지 않았다.However, in recent years, the aspect ratio of the contact hole increases not only due to the high integration and the high density, but also the step coverage due to the step of the interlayer dielectric film (ILD film), which is a composite film forming the contact hole. It was not easy to secure.
이에 따라 상기 스텝 커버리지가 취약한 부분이 상기 반도체 기판의 저부 영역에서도 나타남으로 인해 상기 경계금속막의 형성이 용이하지 않아 상기 반도체 기판의 노출이 빈번하게 일어났다.As a result, the weak portion of the step coverage also appears in the bottom region of the semiconductor substrate, so that the formation of the boundary metal film is not easy, so that the semiconductor substrate is frequently exposed.
따라서 상기 경계금속막 상에 형성되는 금속막중에서 상기 반도체 기판이 노출된 부분에는 상기 금속막이 직접 접촉되기 때문에 그 계면에서는 여전히 상기한 바와 같이 물질이동이 일어났으며, 또한 이러한 물질이동으로 인하여 피팅현상이 일어났고, 상기 피팅현상에 의해 졍선 스파이크 등과 같은 불량이 발생하였다.Accordingly, since the metal film is in direct contact with the exposed portion of the semiconductor substrate in the metal film formed on the boundary metal film, the material movement still occurs at the interface as described above, and the fitting phenomenon is caused by the material movement. Occurred, and defects such as X-ray spikes occurred due to the fitting phenomenon.
더욱이 종래의 경계금속막은 상기 콘택 홀의 양측벽에도 형성되였기 때문에 상기 콘택 홀의 실질적인 종횡비는 크게 나타났고, 이로 인해 경계 금속막이 형성된 콘택 홀의 영역에서는 금속막이 끊어진 상태로 형성되는 단락(Short) 현상 또는 상기 콘택 홀의 입구부분에서 금속막이 붙어버리는 보이드(Void) 현상 등과 같은 불량이 빈번하게 일어났다.In addition, since the conventional boundary metal film is formed on both side walls of the contact hole, a substantial aspect ratio of the contact hole is large, and thus, a short phenomenon or a contact phenomenon in which the metal film is formed in the contact hole area where the boundary metal film is formed is broken. Defects such as a void phenomenon in which the metal film adheres at the inlet of the hole frequently occur.
따라서 종래의 콘택 홀을 포함하는 반도체 기판 상에 형성시키는 경계금속막은 스텝 커버리지의 확보가 용이하지 않고, 또한 금속막의 형성시 불량이 빈번하게 발생되어 제품의 신뢰도가 저하되는 문제점이 있었다.Therefore, the boundary metal film formed on the semiconductor substrate including the conventional contact hole is not easy to secure the step coverage, and there is a problem in that defects frequently occur during the formation of the metal film, thereby lowering the reliability of the product.
본 발명의 목적은, 반도체 기판 상의 콘택 홀이 형성되는 저부에 경계금속막을 형성시켜 이용함으로써 스텝 커버리지의 충분한 확보와 불량의 발생 등을 억제시켜 제품의 신뢰도를 향상시키기 위한 반도체장치의 제조방법 및 그에 따라 제조되는 반도체장치를 제공하는 데 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a semiconductor device for improving the reliability of a product by suppressing occurrence of sufficient step coverage and occurrence of defects by forming and using a boundary metal film at a bottom where a contact hole on a semiconductor substrate is formed. The present invention provides a semiconductor device manufactured according to the present invention.
상기 목적을 달성하기 위한 본 발명에 따른 반도체장치의 제조방법은, 반도체장치의 제조방법에 있어서, 반도체 기판 상의 제 1 영역에 경계금속막을 형성시키는 경계금속막형성단계 및 상기 제 1 영역에 형성된 경계금속막이 노출되도록 반도체 기판 상에 아이엘디막을 형성시키는 아이엘디막 형성단계를 구비하여 이루어짐을 특징으로 한다.In the semiconductor device manufacturing method according to the present invention for achieving the above object, in the manufacturing method of the semiconductor device, a boundary metal film forming step of forming a boundary metal film in the first region on the semiconductor substrate and the boundary formed in the first region And forming an ELD film on the semiconductor substrate so that the metal film is exposed.
상기 경계금속막을 포함하는 아이엘디막 상에 금속막을 형성시키는 금속막형성단계를 더 구비하여 이루어지는 것이 바람직하다.It is preferable to further comprise a metal film forming step of forming a metal film on the ELD film including the boundary metal film.
상기 경계금속막은 스퍼터링을 이용하여 반도체 기판 상에 적층시킨 후, 사진식각공정을 이용하여 상기 제 1 영역에 형성시키는 것이 바람직하다.The boundary metal film is preferably laminated on the semiconductor substrate using sputtering, and then formed in the first region using a photolithography process.
상기 경계금속막이 형성되는 제 1 영역 상에는 그 종횡비가 2이상인 콘택 홀을 형성시키는 것이 바람직하다.It is preferable to form contact holes having an aspect ratio of 2 or more on the first region where the boundary metal film is formed.
상기 경계금속막은 1,000Å 내지 1,400Å 정도의 두께로, 티타늄 및 질화티타늄을 순차적으로 적층, 형성시켜 이루어지는 것이 바람직하다.The boundary metal film is preferably formed by sequentially stacking and forming titanium and titanium nitride in a thickness of about 1,000 kPa to 1,400 kPa.
상기 아이엘디막은 산화막, 고온산화막 및 보호막 또는 고온산화막 및 보호막을 순차적으로 적층, 형성시켜 이루어지는 것이 바람직하고, 상기 산화막은 플라즈마 반응을 이용하고, 상기 보호막은 비피에스지로 적층, 형성시켜 이루어지는 것이 바람직하다.It is preferable that the IDL film is formed by sequentially stacking and forming an oxide film, a high temperature oxide film and a protective film or a high temperature oxide film and a protective film, and the oxide film is preferably formed by laminating and forming the BP paper using a plasma reaction. .
상기 제 1 영역이 제거되도록 형성시키는 아이엘디막은 사진식각공정을 수행하여, 상기 경계금속막이 60% 내지 90% 정도가 노출되도록 상기 아이엘디막을 제거, 형성시켜 이루어지는 것이 바람직하다.The ILD film formed to remove the first region may be formed by performing a photolithography process to remove and form the IDL film so that the boundary metal film is exposed to about 60% to 90%.
상기 금속막은 알루미늄을 적층, 형성시켜 이루어지는 것이 바람직하다.It is preferable that the said metal film is formed by laminating | stacking and forming aluminum.
본 발명에 따른 반도체장치의 제조방법은, 반도체장치의 제조방법에 있어서, (1) 반도체 기판 상에 경계금속막을 형성시키는 경계금속막형성단계; (2) 상기 경계금속막이 형성된 반도체 기판 상의 제 1 영역을 제외한 나머지 영역의 경계금속막을 제거시키는 제 1 제거단계; (3) 상기 (2)의 제 1 제거단계에 의하여 상기 제 1 영역에 형성된 경계금속막을 포함하는 반도체 기판 상에 아이엘디막을 형성시키는 아이엘디막형성단계; 및 (4) 상기 제 1 영역에 형성된 경계금속막이 노출되도록 상기 제 1 영역의 아이엘디막을 제거시키는 제 2 제거단계를 구비하여 이루어짐을 특징으로 한다.A semiconductor device manufacturing method according to the present invention includes a semiconductor device manufacturing method comprising: (1) a boundary metal film forming step of forming a boundary metal film on a semiconductor substrate; (2) a first removing step of removing the boundary metal film in the remaining regions except for the first region on the semiconductor substrate on which the boundary metal film is formed; (3) forming an ELD film on the semiconductor substrate including the boundary metal film formed in the first region by the first removing step of (2); And (4) a second removing step of removing the ILD film of the first region so that the boundary metal film formed on the first region is exposed.
상기 제 2 제거단계에 의해 노출되는 경계금속막을 포함하는 아이엘디막 상에 금속막을 형성시키는 금속막형성단계를 더 구비하는 것이 바람직하다.Preferably, the method further includes a metal film forming step of forming a metal film on the IEL film including the boundary metal film exposed by the second removing step.
상기 경계금속막은 스퍼터링을 이용하여 형성시키고, 상기 제 1 제거 및 제 2 제거는 사진식각공정을 수행하여 이루어지는 것이 바람직하다.The boundary metal film is formed by sputtering, and the first removal and the second removal are preferably performed by performing a photolithography process.
본 발명에 따른 반도체장치는, 금속막이 접촉되는 반도체 기판 상의 제 1 영역에 경계금속막을 구비하여 이루어짐을 특징으로 한다.The semiconductor device according to the present invention is characterized in that the boundary metal film is provided in the first region on the semiconductor substrate to which the metal film is in contact.
상기 제 1 영역 상의 경계금속막을 포함하는 반도체 기판 상에 아이엘디막 및 금속막을 더 구비하는 것이 바람직하다.It is preferable that an IEL film and a metal film are further provided on the semiconductor substrate including the boundary metal film on the first region.
상기 제 1 영역은 콘택 홀 영역이고, 상기 콘택 홀은 그 종횡비가 2이상인 것이 바람직하다.Preferably, the first region is a contact hole region, and the contact hole has an aspect ratio of two or more.
상기 경계금속막은 그 두께가 1,000Å 내지 1,400Å 정도로, 티타늄막 및 질화티타늄막이 순차적으로 적층, 형성된 복합경계금속막인 것이 바람직하고, 상기 티타늄막은 그 두께가 200Å 내지 400Å 정도이고, 상기 질화티타늄막은 그 두께가 700Å 내지 1,200Å 정도인 것이 바람직하다.Preferably, the boundary metal film has a thickness of about 1,000 kPa to 1,400 kPa, and is a composite boundary metal film in which a titanium film and a titanium nitride film are sequentially stacked and formed. The titanium film has a thickness of about 200 kPa to 400 kPa, and the titanium nitride film It is preferable that the thickness is about 700 Pa-1,200 Pa.
상기 아이엘디막은 산화막, 고온산화막 및 보호막 또는 고온산화막 및 보호막이 순차적으로 적층, 형성되는 복합막인 것이 바람직하다.The IDL film is preferably a composite film in which an oxide film, a high temperature oxide film and a protective film or a high temperature oxide film and a protective film are sequentially stacked and formed.
상기 산화막은 플라즈마 산화막이고, 상기 보호막은 비피에스지막인 것이 바람직하다.It is preferable that the said oxide film is a plasma oxide film, and the said protective film is a BPS film.
상기 금속막은 알루미늄막인 것이 바람직하다.It is preferable that the said metal film is an aluminum film.
이하, 본 발명의 구체적인 실시예를 첨부한 도면을 참조하여 상세히 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도1 내지 도5는 본 발명에 따른 반도체장치의 제조방법의 일 실시예를 나타내는 단면도이다.1 to 5 are cross-sectional views showing one embodiment of a method of manufacturing a semiconductor device according to the present invention.
먼저, 도1은 반도체 기판(10) 상에 경계금속막(11)이 순차적으로 적층, 형성되어 있는 상태이다.First, FIG. 1 is a state in which the boundary metal film 11 is sequentially stacked and formed on the semiconductor substrate 10.
여기서 본 발명은 상기 경계금속막(11)을 1,000Å 내지 1,400Å 정도의 두께로 형성시킬 수 있고, 실시예에서는 1,200Å의 두께로 형성시킨다.In the present invention, the boundary metal film 11 may be formed to a thickness of about 1,000 kPa to about 1,400 kPa.
또한 본 발명은 상기 경계금속막(11)을 티타늄막(Ti Film)(12) 및 질화티타늄막(TiN Film)(14)을 순차적으로 적층, 형성시킬 수 있고, 상기 티타늄막(12)을 200Å 내지 400Å 정도의 두께로, 상기 질화티타늄막(14)의 두께를 700Å 내지 1,200Å 정도의 두께로 형성시킬 수 있으며, 실시예에서는 상기 티타늄막(12)을 300Å의 두께로, 질화티타늄막(14)을 900Å의 두께로 형성시킨다.In addition, according to the present invention, the boundary metal film 11 may be sequentially stacked and formed on a titanium film 12 and a titanium nitride film 14, and the titanium film 12 may be 200 Å. To about 400 kPa, the thickness of the titanium nitride film 14 may be formed to a thickness of about 700 kPa to about 1,200 kPa. In the embodiment, the titanium film 12 to a thickness of 300 kPa, the titanium nitride film 14 ) Is formed to a thickness of 900Å.
그리고 본 발명은 상기 티타늄막(12) 및 질화티타늄막(14)으로 이루어지는 경계금속막(11)은 스퍼터링(Sputtering)을 이용하여 적층, 형성시킨다.In the present invention, the boundary metal film 11 including the titanium film 12 and the titanium nitride film 14 is laminated and formed by sputtering.
계속해서 도2는 반도체 기판(10)의 소정의 영역에 경계금속막(11)이 적층, 형성되어 있는 상태이다.2, the boundary metal film 11 is laminated | stacked and formed in the predetermined | prescribed area | region of the semiconductor substrate 10. FIG.
여기서 본 발명의 상기 소정의 영역은 콘택 홀이 형성되는 영역이고, 본 발명의 상기 소정의 영역에 형성되는 경계금속막(11)은 사진식각공정을 수행하여 형성시킨다.The predetermined region of the present invention is a region in which contact holes are formed, and the boundary metal film 11 formed in the predetermined region of the present invention is formed by performing a photolithography process.
여기서 상기 콘택 홀이 형성되는 본 발명의 상기 소정의 영역은 설계된 패턴 등에 의한 것이다.The predetermined region of the present invention in which the contact hole is formed is due to a designed pattern or the like.
그리고 도3은 상기 소정의 영역에 형성된 경계금속막(11)을 포함하는 반도체 기판(10) 상에 아이엘디막(16)이 형성되어 있는 상태이다.3 is a state in which the ILD film 16 is formed on the semiconductor substrate 10 including the boundary metal film 11 formed in the predetermined region.
여기서 본 발명은 상기 아이엘디막(16)을 산화막, 고온산화막(HTO : High Temperature Oxidation) 및 보호막(Passivation Film)이 순차적으로 형성되는 복합막을 이용할 수 있고, 또한 고온산화막 및 보호막이 순차적으로 적층, 형성되는 복합막을 이용할 수 있다.Here, the present invention may use a composite film in which an oxide film, a high temperature oxide film (HTO: High Temperature Oxidation), and a passivation film (STO) are sequentially formed on the ELD film 16, and the high temperature oxide film and the protective film are sequentially stacked, The composite film formed can be used.
그리고 실시예에서는 상기 아이엘디막(16)을 산화막, 고온산화막 및 보호막이 순차적으로 적층, 형성되는 복합막을 이용하며, 상기 산화막은 플라즈마(Plasma) 반응을 이용하여 형성되는 플라즈마 산화막(PEOX : Plasma Enhancement Oxidation)을, 상기 보호막은 비피에스지막(BPSG Film : Borophosphorsilicate Glass Film)을 적층, 형성시킨다.In the embodiment, the IELDI film 16 is formed by using a composite film in which an oxide film, a high temperature oxide film, and a protective film are sequentially stacked and formed, and the oxide film is formed using a plasma reaction (PEOX: Plasma Enhancement). Oxidation, and the protective layer is laminated to form a BPSG film (Borophosphorsilicate Glass Film).
이어서 도4는 상기 아이엘디막(16)의 소정의 영역을 제거시켜 상기 경계금속막(11)이 노출되는 상태를 나타낸다.4 shows a state in which the boundary metal film 11 is exposed by removing a predetermined region of the ILD film 16.
여기서 본 발명은 전술한 바와 같이 상기 소정의 영역은 콘택 홀이 형성되는 영역으로써, 상기 아이엘디막(16)의 소정의 영역을 제거시켜 콘택 홀을 형성시키는 것이다.In the present invention, as described above, the predetermined region is a region in which the contact hole is formed, and the predetermined region of the ILD film 16 is removed to form the contact hole.
그리고 본 발명은 상기 아이엘디막(16)의 소정의 영역의 제거로 형성되는 콘택 홀의 종횡비를 2이상으로 형성시키고, 상기 반도체 기판(10) 상의 콘택 홀의 저부에 형성된 경계금속막(11)이 60% 내지 90% 정도로 노출되도록 하며, 실시예에서는 상기 경계금속막(11)이 80% 정도가 노출되도록 상기 아이엘디막(16)을 제거한다.In the present invention, the aspect ratio of the contact hole formed by removing the predetermined region of the ILD film 16 is formed to be 2 or more, and the boundary metal film 11 formed at the bottom of the contact hole on the semiconductor substrate 10 is 60. The IELDI film 16 is removed so that the boundary metal film 11 is exposed to about 80%.
여기서 상기 아이엘디막(16)의 제거로 형성되는 콘택 홀의 종횡비 및 상기 경계금속막(11)이 노출되는 영역의 정도는 작업자가 설계시 임의로 설정할 수 있다.In this case, the aspect ratio of the contact hole formed by the removal of the IDL film 16 and the degree of the region where the boundary metal film 11 is exposed may be arbitrarily set by the operator during design.
즉, 상기 아이엘디막(16)의 두께와 상기 경계금속막(11)의 넓이를 적절히 고려하여 형성시킴으로써 상기 콘택 홀의 종횡비 및 상기 경계금속막(11)이 노출되는 영역을 결정할 수 있다.That is, by considering the thickness of the ILD film 16 and the width of the boundary metal film 11 properly, it is possible to determine the aspect ratio of the contact hole and the region where the boundary metal film 11 is exposed.
그리고 본 발명은 상기 소정의 영역의 아이엘디막(16)의 제거를 사진식각공정을 이용하여 수행한다.In the present invention, the ILD film 16 of the predetermined region is removed using a photolithography process.
계속해서 도5는 상기 아이엘디막(16)의 소정의 영역의 제거로 노출된 경계금속막(11)을 포함하는 아이엘디막(16) 상에 금속막(18)이 적층, 형성된 상태이다.5, the metal film 18 is laminated | stacked and formed on the IEL film | membrane 16 containing the boundary metal film 11 exposed by removal of the predetermined | prescribed area | region of the said IEL film | membrane 16. FIG.
여기서 본 발명의 상기 금속막(18)은 알루미늄막(Al Film)을 적층, 형성시킨다.Here, the metal film 18 of the present invention laminates and forms an aluminum film.
전술한 구성으로 이루어지는 본 발명의 구체적인 실시예에 대한 작용 및 효과에 대하여 설명한다.Actions and effects of specific embodiments of the present invention having the above-described configuration will be described.
먼저, 반도체 기판(10) 상에 경계금속막(11)인 티타늄막(12) 및 질화티타늄막(14)을 스퍼터링을 이용하여 순차적으로 적층, 형성시킨다.First, the titanium film 12 and the titanium nitride film 14, which are the boundary metal film 11, are sequentially stacked and formed on the semiconductor substrate 10 by sputtering.
여기서 상기 티타늄막(12)을 300Å의 두께로 상기 질화티타늄막(14)을 900Å의 두께로 하여 상기 경계금속막(11)을 1,200Å의 두께로 적층, 형성시킨다.Here, the boundary metal film 11 is laminated and formed to a thickness of 1,200 kPa, with the titanium film 12 having a thickness of 300 kPa and the titanium nitride film 14 having a thickness of 900 kPa.
그리고 사진식각공정을 수행하여 상기 경계금속막(11)이 반도체 기판(10) 상의 소정의 영역 즉, 콘택 홀이 형성되는 영역에 형성되도록 한다.A photolithography process is performed so that the boundary metal film 11 is formed in a predetermined region on the semiconductor substrate 10, that is, a region in which contact holes are formed.
이어서 상기 소정의 영역에 형성된 경계금속막(11)을 포함하는 반도체 기판(10) 상에 산화막, 고온산화막 및 비피에스지막이 순차적으로 이루어지는 아이엘디막(16)을 적층, 형성시킨다.Subsequently, an ILD film 16 having an oxide film, a high temperature oxide film, and a BPS film is sequentially stacked and formed on the semiconductor substrate 10 including the boundary metal film 11 formed in the predetermined region.
그리고 사진식각공정을 수행하여 상기 아이엘디막(16)의 소정의 영역을 제거시켜 콘택 홀을 형성시킨다.The photolithography process is performed to remove a predetermined region of the ILD film 16 to form a contact hole.
즉, 상기 아이엘디막(16)의 소정의 영역의 제거로 형성되는 콘택 홀의 저부에 상기 경계금속막(11)이 80% 정도로 노출되도록 한다.That is, the boundary metal film 11 is exposed to about 80% at the bottom of the contact hole formed by removing a predetermined region of the IDL film 16.
여기서 상기 콘택 홀의 종횡비는 2이상으로 형성시키고, 이러한 종횡비의 결정은 전술한 바와 같이 상기 아이엘디막(16)과 상기 경계금속막(11)의 넓이 등을 고려하여 작업자가 임의로 설정할 수 있다.In this case, the aspect ratio of the contact hole is formed to be 2 or more, and the aspect ratio can be arbitrarily set by the operator in consideration of the width of the ILD film 16 and the boundary metal film 11 as described above.
그리고 상기 아이엘디막(16)의 제거로 노출된 경계금속막(11)을 포함하는 아이엘디막(16) 상에 알루미늄막으로 이루어지는 금속막(18)을 적층, 형성시킨다.Then, a metal film 18 made of an aluminum film is laminated and formed on the IEL film 16 including the boundary metal film 11 exposed by the removal of the IEL film 16.
이러한 구성으로 이루어지는 본 발명은 반도체 기판(10)의 소정의 영역 즉, 콘택 홀이 형성되는 영역 상에 미리 경계금속막(11)을 적층, 형성시킨 후, 아이엘디막(16)을 이용하여 콘택 홀을 형성시키고 그 상부에 금속 막(18)을 적층, 형성시킨다.According to the present invention having such a configuration, after the boundary metal film 11 is laminated and formed on a predetermined region of the semiconductor substrate 10, that is, the region where the contact hole is formed, the contact is formed by using the ILD film 16. Holes are formed, and a metal film 18 is stacked and formed thereon.
이에 따라 본 발명은 경계금속막(11)이 콘택 홀의 양측벽에는 형성되지 않고, 상기 콘택 홀의 저부에만 형성되는 것으로써, 상기 콘택 홀을 형성하는 아이엘디막(16)의 단차에 영향을 받지 않는다.Accordingly, in the present invention, the boundary metal film 11 is not formed on both side walls of the contact hole, and is formed only at the bottom of the contact hole, and thus is not affected by the step difference of the IEL film 16 forming the contact hole. .
또한 상기 경계금속막(11)으로 인해 콘택 홀의 종횡비가 실질적으로 커지는 것을 방지할 수 있다.In addition, it is possible to prevent the aspect ratio of the contact hole from being substantially increased due to the boundary metal film 11.
이에 따라 본 발명의 반도체장치의 제조방법을 이용하면 콘택 홀의 종횡비가 2이상으로 이루어지는 최근의 반도체장치의 제조에 적절히 대응할 수 있다.Accordingly, by using the method for manufacturing a semiconductor device of the present invention, it is possible to appropriately cope with the recent production of a semiconductor device having an aspect ratio of a contact hole of two or more.
그리고 상기 경계금속막(11)을 60% 내지 90% 정도로 노출시켜 그 상부에 금속막(18)을 적층, 형성시킴으로써 상기 금속막(18)이 상기 반도체 기판(10)과 접촉하는 것을 방지할 수 있어 상기 반도체 기판(10)의 실리콘 원자가 상기 금속막(18)으로 물질이동하는 것을 방지할 수 있다.The metal film 18 may be prevented from contacting the semiconductor substrate 10 by exposing the boundary metal film 11 to about 60% to 90% by laminating and forming the metal film 18 thereon. Therefore, the silicon atoms of the semiconductor substrate 10 may be prevented from moving to the metal layer 18.
이에 따라 반도체 기판인 실리콘 원자와의 물질이동을 방지함으로써 피팅현상으로 인한 졍선 스파이크 등과 같은 불량을 억제할 수 있다.Accordingly, defects such as X-ray spikes due to the fitting phenomenon can be suppressed by preventing material movement with silicon atoms, which are semiconductor substrates.
또한 본 발명은 금속막의 적층, 형성시 단락 또는 보이드 등과 같은 불량을 억제시킬 수 있다.In addition, the present invention can suppress defects such as short-circuits or voids in lamination and formation of metal films.
따라서, 본 발명에 의하면 충분한 스텝 커버리지를 확보할 수 있고, 또한 불량을 방지할 수 있어 제품의 신뢰도가 향상되는 효과가 있다.Therefore, according to the present invention, sufficient step coverage can be ensured, and defects can be prevented, thereby improving the reliability of the product.
이상에서 본 발명은 기재된 구체예에 대해서만 상세히 설명되었지만 본 발명의 기술사상 범위 내에서 다양한 변형 및 수정이 가능함은 당업자에게 있어서 명백한 것이며, 이러한 변형 및 수정이 첨부된 특허청구범위에 속함은 당연한 것이다.Although the present invention has been described in detail only with respect to the described embodiments, it will be apparent to those skilled in the art that various modifications and variations are possible within the technical scope of the present invention, and such modifications and modifications are within the scope of the appended claims.
도1 내지 도5는 본 발명에 따른 반도체장치의 제조방법의 일 실시예를 나타내는 단면도이다.1 to 5 are cross-sectional views showing one embodiment of a method of manufacturing a semiconductor device according to the present invention.
※도면의 주요부분에 대한 부호의 설명※ Explanation of symbols for main parts of drawing
10 : 반도체 기판 11 : 경계금속막10 semiconductor substrate 11 boundary metal film
12 : 티타늄막 14 : 질화티타늄막12 titanium film 14 titanium nitride film
16 : 아이엘디막 18 : 금속막16: ELD film 18: metal film
Claims (30)
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| KR1019970020372A KR100487476B1 (en) | 1997-05-23 | 1997-05-23 | Method of forming semiconductor devices and semiconductor devices formed thereby |
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| KR1019970020372A KR100487476B1 (en) | 1997-05-23 | 1997-05-23 | Method of forming semiconductor devices and semiconductor devices formed thereby |
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| KR100487476B1 true KR100487476B1 (en) | 2005-09-16 |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR890016634A (en) * | 1988-04-07 | 1989-11-29 | 강진구 | Manufacturing Method of Semiconductor Device |
| JPH05121565A (en) * | 1991-10-25 | 1993-05-18 | Oki Electric Ind Co Ltd | Manufacture of semiconductor devices |
| KR960032617A (en) * | 1995-02-28 | 1996-09-17 | 가네꼬 히사시 | Method for forming interconnections of semiconductor devices |
| KR960043119A (en) * | 1995-05-19 | 1996-12-23 | 김주용 | Via hole formation method of semiconductor device |
| KR970018102A (en) * | 1995-09-21 | 1997-04-30 | 김광호 | Formation method of small contact hole with high aspect ratio |
| KR100227622B1 (en) * | 1996-12-28 | 1999-11-01 | 김영환 | Method of fabricating bit line of semiconductor device |
-
1997
- 1997-05-23 KR KR1019970020372A patent/KR100487476B1/en not_active IP Right Cessation
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR890016634A (en) * | 1988-04-07 | 1989-11-29 | 강진구 | Manufacturing Method of Semiconductor Device |
| JPH05121565A (en) * | 1991-10-25 | 1993-05-18 | Oki Electric Ind Co Ltd | Manufacture of semiconductor devices |
| KR960032617A (en) * | 1995-02-28 | 1996-09-17 | 가네꼬 히사시 | Method for forming interconnections of semiconductor devices |
| KR960043119A (en) * | 1995-05-19 | 1996-12-23 | 김주용 | Via hole formation method of semiconductor device |
| KR970018102A (en) * | 1995-09-21 | 1997-04-30 | 김광호 | Formation method of small contact hole with high aspect ratio |
| KR100227622B1 (en) * | 1996-12-28 | 1999-11-01 | 김영환 | Method of fabricating bit line of semiconductor device |
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| KR19980084541A (en) | 1998-12-05 |
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