JPH01300537A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To scale down the stepped section of a pattern, and to improve flatness by forming an insulating sidewall composed of a material different from an inter-layer insulating film onto the internal side face of a contact hole shaped to an inter-layer insulating layer containing the inter-layer insulating film consisting of a specific material, forming conductive layers onto the sidewall and electrically connecting the conductive layers on both sides. CONSTITUTION:Contact holes 10 are bored on first layer metallic wiring patterns 3, and a plasma SiN film 12 is deposited. The thickness section of the depositing plasma SiN film 12 is removed through anisotropic etching, one parts of the SiN film 12 are left on the internal side faces of the contact, holes 10 and insulating sidewalls 14 are shaped. An Al-Si film 15 for a second layer wiring is formed onto a plasma SiO2 film 17 and the insulating sidewalls 14, and a wiring pattern is shaped. Accordingly, a contact pattern for multilayer interconnections can be formed without damaging flatness and increasing contact resistance in the contact holes.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a fine contact pattern for multilayer wiring in an integrated circuit element.

<Prior Art> Conventionally, as a method for forming a contact pattern for multilayer wiring, a method comprising the following steps (iXii) (river X1v) corresponding to, for example, FIG. 2 (iXii X1iiXiv) is known.

(i) First layer wiring pattern formation: After depositing boron ring glass on the Si substrate 1 to form the boron ring glass film 2, a layer of A is formed on the boron ring glass film 2.
A metal wiring pattern 3 is formed from l-Si alloy.

(ii) Formation of interlayer insulating layer: At an ambient temperature of about 300°C, the metal wiring pattern 3 is
A plasma Sin film 5 is formed by depositing approximately 0.3 to 0.4 μm of plasma Sin on top, followed by coating approximately 0.3 to 0.5 μm of spin-on glass (SOG) and heat-treating. After forming the SOG film 6, plasma 5iOz is deposited again to a thickness of about 0.5 μm at an ambient temperature of 300° C. to form a plasma 5iOy film 7. These 5hot film 5, SOG film 6.5iot film 7 form an interlayer insulating layer 8.

(iii) Contact hole processing.

A contact hole 10 is formed on the interlayer insulating layer 8 by reactive ion etching using a resist pattern (not shown) as a mask.

(iv) Formation of a second-layer metal film for wiring A second-layer wiring metal film 11 made of an Al-5i alloy is formed on the interlayer insulating layer 8 and inside the contact hole 10 by a varnish batter method.

<Problems to be Solved by the Invention> According to the method for forming a contact pattern for multilayer interconnection comprising the above steps, as can be seen from FIG. 2(iii), when the contact hole 10 is opened, the side surface of the SOG film 6 is exposed to the contact hole IO.

Residual gas evaporates from this SOG, and an aluminum oxide film is generated on the Al-9i film 3, which is the first layer wiring pattern.

This causes poor contact between the wiring metal films 3 and 11.

This effect becomes more pronounced as the diameter of the contact hole becomes smaller, resulting in the problem of increased contact resistance between both metal films.

In order to solve this problem, in the step (ii) above, after forming the SOG film 6, the 5OGI 16 on the first layer metal pattern 3 is etched back, as shown in FIG. 3(a). A method of removing it is often used.

However, this has the following problems.

During etchback, the etching rate of the SOG film thickly deposited between the wirings and the SOG film thinly deposited on the wirings is different, so that the SOG between the wirings is etched faster than the SOG on the wirings. Therefore, as shown in FIG. 3(b), the SO formed outside the upper side of the first layer metal pattern 3
G is also removed in a ■ shape except for both corners. As a result, the flatness obtained by applying SOG deteriorates.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to form a contact pattern for multilayer wiring without impairing flatness or increasing contact resistance in contact holes.

<Means for Solving the Problems> In order to achieve the above object, a method for manufacturing a semiconductor device including a plurality of conductive layers and an interlayer insulating layer on a substrate according to the present invention provides an interlayer insulating layer made of at least one specific material. A contact hole is opened in the interlayer insulating layer including the film, an insulating sidewall made of a material different from the interlayer insulating film made of the specific material is formed on the inner surface of the contact hole, and then a conductive layer is formed on the insulating sidewall. The conductive layer is formed on the interlayer insulating layer to electrically connect the conductive layers on both sides of the interlayer insulating layer.

<Example> Hereinafter, the present invention will be explained in detail with reference to illustrated embodiments.

Figure 1 is a process diagram showing one embodiment of the present invention.
1) corresponds to FIG. 2(iii). In other words, there is a contact hole on top of the first layer metal wiring pattern 3! The steps to form 0 are shown in FIGS. 2(i) and (ii).

Since it is the same as that shown in (iii), the explanation is omitted, and the subsequent steps are shown in Figure 1 (nXIIIXIV).
Explain according to the following.

CU) Formation of insulating film for sidewall formation: Figure 1 (
1) After opening a contact hole 10 on the first layer metal wiring pattern 3, a plasma SiN film 12 of about 0.5 μm is deposited using the CVD method at an ambient temperature of about 300° C. .

([Ir) Sidewall processing: Next, anisotropic etching is performed using a reactive ion etching method to remove the thickness of the deposited plasma SiN film 12 from the plasma SiN film 12. In this way, a portion of the SiN film 12 remains on the inner surface of the contact hole 10, forming an insulating sidewall 14. Since the SOG film 6 exposed on the side surface of the contact hole 10 in step (1) is covered by the insulating sidewall 14, residual gas generated from this SOG will not flow into the contact hole 10. Further, as is clear from FIG. 1 (IXIV), the insulating sidewall 14 is thinner at the outer part of the contact hole 10 than at the inner part, and the slope of the side wall of the contact hole is made gentler. Therefore, the flatness of the wiring pattern is improved.

(■) Formation of second-layer wiring metal film: An Al-3i film 15' for second-layer wiring is formed on the plasma 5iOy film 7 and the insulating sidewall 14 by sputtering. Thereafter, a wiring pattern is produced using a normal method.

According to the above embodiment, the SOG exposed through the opening of the contact hole 10 is covered by the sidewall 14, so that the residual gas from the exposed SOG is prevented from evaporating as in the conventional case. Therefore, an increase in contact resistance between metal wirings due to the formation of an aluminum oxide film due to this residual gas can be prevented. In addition, as shown in FIG. 1 (1), by forming the sidewall 14, the effective diameter d2 of the contact hole becomes smaller than the diameter d when the contact hole is opened. Machining becomes easier because it is only necessary to pattern the hole so that it has a diameter d that is slightly larger than the diameter d of the hole. In addition, unlike conventional methods, SOG is not etched back, so there is no deterioration in the flatness of the pattern.Furthermore, by forming the sidewall 14, the slope of the sidewall of the contact hole IO becomes gentler, making it even better. A flatness can be obtained. Therefore, problems such as disconnection and short circuit of the second layer metal wiring I5 can be avoided.

Although the SOG film 6 was used as one of the insulating films in the above embodiment, other volatile glasses may be used, and the insulating sidewall I4 was formed of a SiN film.
For example, other nitride films or oxide films may be used as long as they are not volatile under certain conditions.

<Effects> As is clear from the above explanation, according to the present invention, since an insulating side wheel is used on the side wall of the contact hole, the level difference in the pattern is reduced and good smoothness is obtained, so that the conductive layer When wiring is processed, it is possible to effectively prevent wiring breaks and short circuits. Further, since the insulating sidewall is used, when opening the contact hole, the diameter can be patterned to a size slightly thicker than the intended diameter. In addition, if a material that is volatile under certain conditions is used in the interlayer insulation layer and a material that is nonvolatile under the above conditions is used in the insulating sidewall, the gas that is generated from the volatile material will be absorbed by the insulating sidewall. Since it is sealed, the problem of increased contact resistance between metal wirings due to oxide film formation due to volatile gas does not occur, and a fine contact pattern can be formed.

[Brief explanation of the drawing]

Figure 1 is a process diagram of an embodiment of the present invention, Figures 2 and 3 are
The figure is a process diagram of a conventional example. l...Si substrate, 3...first layer metal pattern,
5.7...5iOz film, 6...SOG film, 8...interlayer insulating layer, IO...contact hole, 11.15...
... Metal film for second layer wiring, 14... Insulating side wall.

Claims (1)

[Claims] (1) A method for manufacturing a semiconductor device having a plurality of conductive layers and an interlayer insulating layer on a substrate, the method comprising: opening a contact hole in an interlayer insulating layer including an interlayer insulating film made of at least one specific material; An insulating sidewall made of a material different from the interlayer insulating film made of the specific material is formed on the inner surface of the contact hole, and then a conductive layer is formed on the insulating sidewall to increase conductivity on both sides of the interlayer insulating layer. A method for manufacturing a semiconductor device, characterized by electrically connecting layers.