JPH01273333A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH01273333A JPH01273333A JP10295588A JP10295588A JPH01273333A JP H01273333 A JPH01273333 A JP H01273333A JP 10295588 A JP10295588 A JP 10295588A JP 10295588 A JP10295588 A JP 10295588A JP H01273333 A JPH01273333 A JP H01273333A
- Authority
- JP
- Japan
- Prior art keywords
- opening
- conductive film
- insulating film
- film
- insulation film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 11
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 238000000034 method Methods 0.000 claims abstract description 15
- 238000005530 etching Methods 0.000 claims abstract description 10
- 239000004020 conductor Substances 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims 1
- 239000000758 substrate Substances 0.000 abstract description 5
- 238000009413 insulation Methods 0.000 abstract 8
- 230000000694 effects Effects 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製造方法に関し、特に多層配線構
造におけるコンタクト部の段差を緩和する製造方法に関
する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device for reducing steps in contact portions in a multilayer wiring structure.
従来、多層配線構造における上下の配線層を相互に電気
接続するコンタクト部の製造方法として、第３図（ａ）
乃至（Ｃ）に示す方法が取られている。Conventionally, as a method for manufacturing a contact portion that electrically connects upper and lower wiring layers to each other in a multilayer wiring structure, the method shown in FIG. 3(a) is used.
The methods shown in (C) are used.
即ち、第３図（ａ）のように、半導体基板１１を覆う下
地絶縁膜１２に選択的に開孔部１２ａを設け、この開孔
部の少なくとも一部を覆いかつ下地絶縁膜１２上に延在
する第１の導電膜１３を選択的に形成する。That is, as shown in FIG. 3(a), an opening 12a is selectively provided in the base insulating film 12 covering the semiconductor substrate 11, and a hole 12a is selectively formed in the base insulating film 12, covering at least a part of the opening and extending onto the base insulating film 12. The existing first conductive film 13 is selectively formed.
この上に、第３図（ｂ）のように、第１の絶縁膜１４を
被着し、かつ第１の導電膜１３の位置において第１の絶
縁膜１４に選択的に開孔部１４ａを設ける。On top of this, as shown in FIG. 3(b), a first insulating film 14 is deposited, and openings 14a are selectively formed in the first insulating film 14 at the positions of the first conductive film 13. establish.
更に、第３図（ｃ）のように、第１の絶８！膜１４の開
孔部の少なくとも一部を覆う第２の導電膜１６を選択的
に形成し、この開孔部を通して第１及び第２の各導電膜
１３．１６を相互に電気接続している。Furthermore, as shown in Figure 3(c), the first 8! A second conductive film 16 is selectively formed to cover at least a portion of the opening in the membrane 14, and the first and second conductive films 13.16 are electrically connected to each other through the opening. .
上述した従来の製造方法は、第１の絶縁膜１４を比較的
に厚く形成するため、これに開設した開孔部１４ａの段
部が急峻になる。このため、この開孔部１４ａにおいて
、第２の導電膜１６に楔状の亀裂が発生し易く、この部
分において第２の導電膜１６が断線するという問題があ
る。In the conventional manufacturing method described above, the first insulating film 14 is formed relatively thick, so that the step of the opening 14a formed therein becomes steep. Therefore, wedge-shaped cracks are likely to occur in the second conductive film 16 at this opening 14a, and there is a problem that the second conductive film 16 is disconnected at this portion.
本発明は第２の導電膜における断線を有効に防止する半
導体装置の製造方法を提供することを目的としている。An object of the present invention is to provide a method for manufacturing a semiconductor device that effectively prevents disconnection in the second conductive film.
本発明の半導体装置の製造方法は、第１の導電体を覆う
第１の絶縁膜に開孔部を開設する工程と、この開孔部を
含む第１の絶縁膜上に第２の絶縁膜を被着する工程と、
この第２の絶縁膜を異方性エツチング法によりエツチン
グバックして前記開孔部の内壁に沿ってその一部を残す
工程と、この開孔部を含む領域に第２の導電膜を形成す
る工程とを含んでいる。The method for manufacturing a semiconductor device of the present invention includes the steps of forming an opening in a first insulating film covering a first conductor, and forming a second insulating film on the first insulating film including the opening. a process of applying
etching back the second insulating film using an anisotropic etching method to leave a portion of the second insulating film along the inner wall of the opening, and forming a second conductive film in a region including the opening. It includes the process.
上述した方法により製造した多層配線のコンタクト部は
、異方性エツチング法によって第１の絶縁膜の開孔部の
内壁に第２の絶縁膜の一部が残され、かつその上面がテ
ーパ状に形成されるため、この第２の絶縁膜によって開
孔部の段差を緩和し、第２の導電膜の被着性を改善する
。In the contact portion of the multilayer wiring manufactured by the method described above, a part of the second insulating film is left on the inner wall of the opening in the first insulating film by an anisotropic etching method, and the upper surface thereof is tapered. Therefore, the second insulating film alleviates the step difference in the opening and improves the adhesion of the second conductive film.
（実施例〕 次に、本発明を図面を参照して説明する。(Example〕 Next, the present invention will be explained with reference to the drawings.
第１図（ａ）乃至（ｄ）は本発明の第１実施例を製造工
程に従って示す断面図である。FIGS. 1(a) to 1(d) are cross-sectional views showing a first embodiment of the present invention according to the manufacturing process.
先ず、第１図（ａ）のように、半導体基板１の表面を覆
う酸化膜からなる下地絶縁膜２に選択的に開孔部２ａを
開設する。この上に、開孔部２ａの少なくとも一部を覆
うように第１の導電膜３を所要パターンに形成する。First, as shown in FIG. 1(a), openings 2a are selectively opened in the base insulating film 2 made of an oxide film covering the surface of the semiconductor substrate 1. Then, as shown in FIG. Thereon, the first conductive film 3 is formed in a desired pattern so as to cover at least a portion of the opening 2a.
次いで、第１図（ｂ）のように、前記下地絶縁膜２及び
第１の導電膜３を覆うように窒化膜からなる第１の絶縁
膜４を比較的厚く形成する。そして、この第１の絶縁膜
４の前記第１の導電膜３上の位置に、選択的に開孔部４
ａを開設する。更に、この開孔部４ａを含む全面に窒化
膜からなる第２の絶縁膜５を被着する。Next, as shown in FIG. 1(b), a relatively thick first insulating film 4 made of a nitride film is formed so as to cover the base insulating film 2 and the first conductive film 3. Then, an opening 4 is selectively formed in the first insulating film 4 at a position above the first conductive film 3.
Open a. Further, a second insulating film 5 made of a nitride film is deposited on the entire surface including the opening 4a.
続いて、第１図（ｃ）のように、前記第２の絶縁膜５に
対して異方性イオンエツチングを施しててエツチングバ
ックする。この異方性エツチングにより、第２の絶縁膜
５の水平部分はエツチングされるが、開孔部４ａの内壁
に沿う垂直一部５ａのみが残され、かつその異方性によ
りこの部分５ａの上面は開孔部４ａの中心に向けて傾斜
されたテーバ状にエツチングされる。Subsequently, as shown in FIG. 1(c), the second insulating film 5 is etched back by anisotropic ion etching. Through this anisotropic etching, the horizontal portion of the second insulating film 5 is etched, but only the vertical portion 5a along the inner wall of the opening 4a remains, and due to its anisotropy, the upper surface of this portion 5a is etched. is etched in a tapered shape inclined toward the center of the opening 4a.
したがって、第１図（ｄ）のように、この上から開孔部
４ａを含む領域に第２の導電膜６を所要パターンに形成
し、開孔部４ａを通して第１の導電膜３に電気接続する
。このとき、開孔部４ａにおいては、開孔部４ａの段差
が象、峻であっても、開孔部４ａに沿って残された第２
の導電膜の一部５ａの上面テーパ形状によって段差が緩
和され、第２の導電膜６の被着性が改善され、亀裂等の
発生が防止される。Therefore, as shown in FIG. 1(d), a second conductive film 6 is formed in a desired pattern in a region including the opening 4a from above, and electrically connected to the first conductive film 3 through the opening 4a. do. At this time, in the aperture 4a, even if the step of the aperture 4a is steep, the second portion left along the aperture 4a is
The tapered shape of the upper surface of the portion 5a of the conductive film reduces the level difference, improves the adhesion of the second conductive film 6, and prevents the occurrence of cracks and the like.
第２図（ａ）及び（ｂ）は本発明の第２実施例の一部を
製造工程順に示す断面図である。FIGS. 2(a) and 2(b) are cross-sectional views showing a part of a second embodiment of the present invention in the order of manufacturing steps.
この実施例では、第１実施例の第１図（ａ）乃至（Ｃ）
と同一の工程を施した後、開孔部４ａ内に残されている
第２の絶縁膜５の異方性エツチングを更に進めている。In this embodiment, FIGS. 1(a) to (C) of the first embodiment
After performing the same steps as above, anisotropic etching of the second insulating film 5 remaining in the opening 4a is further progressed.
これにより、第２図（ａ）のように、第２の絶縁膜５ａ
のテーパ面が第１の導電膜３に接触される位置まで進め
られ、開孔部４ａの内面の段差を更に改善する。As a result, as shown in FIG. 2(a), the second insulating film 5a
The tapered surface is advanced to a position where it comes into contact with the first conductive film 3, thereby further improving the level difference on the inner surface of the opening 4a.
したがって、第２図（ｂ）のように、開孔部４ａを含む
領域に形成する第２の導電膜６における被着性を改善し
、亀裂の発生を更に有効に防止できる。Therefore, as shown in FIG. 2(b), the adhesion of the second conductive film 6 formed in the region including the opening 4a can be improved, and the generation of cracks can be more effectively prevented.
なお、本発明は半導体基板と第１の導電膜とのコンタク
ト部に適用することができるとともに、３層以上の多層
配線構造における第２の導電膜以降のコンタクト部にお
いても同様に適用できる。Note that the present invention can be applied to the contact portion between the semiconductor substrate and the first conductive film, and can also be applied to the contact portion after the second conductive film in a multilayer wiring structure of three or more layers.
以上説明したように本発明は、異方性エツチング法によ
って第１の絶縁膜の開孔部の内壁に第２の絶縁膜の一部
を残し、かつその上面をテーバ状に形成することにより
、第１の絶縁膜における開孔部の段差を緩和し、第２の
導電膜の被着性を改善して亀裂を未然に防止し、その断
線を防止することが可能となる。As explained above, the present invention leaves a part of the second insulating film on the inner wall of the opening of the first insulating film using an anisotropic etching method, and forms the upper surface of the second insulating film in a tapered shape. It becomes possible to reduce the level difference in the opening in the first insulating film, improve the adhesion of the second conductive film, prevent cracks, and prevent wire breakage.
第１図（ａ）乃至第１図（ｄ）は本発明の第１実施例を
製造工程順に示す断面図、第２図（ａ）及び第２図（ｂ
）は本発明の第２実施例の工程−部を示す断面図、第３
図（ａ）乃至第３図（Ｃ）は従来方法を工程順に示す断
面図である。
■、１１・・・半導体基板、２．１２・・・下地絶縁膜
、３．１３・・・第１の導電膜、４．１４・・・第１の
絶縁膜、４ａ、１４ａ・・・開孔部、５・・・第２の絶
縁膜、５ａ・・・第２の絶縁膜の一部、６．１６・・・
第２の導電膜。
第１図
第１図
第２図
ａ
第３図FIGS. 1(a) to 1(d) are sectional views showing the first embodiment of the present invention in the order of manufacturing steps, and FIGS. 2(a) and 2(b).
) is a sectional view showing the process part of the second embodiment of the present invention, and
Figures (a) to 3(C) are cross-sectional views showing the conventional method in the order of steps. ■, 11...Semiconductor substrate, 2.12... Base insulating film, 3.13... First conductive film, 4.14... First insulating film, 4a, 14a... Open Hole portion, 5... second insulating film, 5a... part of second insulating film, 6.16...
Second conductive film. Figure 1 Figure 1 Figure 2 a Figure 3
Claims (1)
る工程と、この開孔部を含む第１の絶縁膜上に第２の絶
縁膜を被着する工程と、この第２の絶縁膜を異方性エッ
チング法によりエッチングバックして前記開孔部の内壁
に沿ってその一部を残す工程と、この開孔部を含む領域
に第２の導電膜を形成する工程とを含むことを特徴とす
る半導体装置の製造方法。1. A step of forming an opening in a first insulating film covering a first conductor, a step of depositing a second insulating film on the first insulating film including the opening, and a step of etching back the second insulating film using an anisotropic etching method to leave a portion of the second insulating film along the inner wall of the opening; and a step of forming a second conductive film in a region including the opening. A method for manufacturing a semiconductor device, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10295588A JPH01273333A (en) | 1988-04-26 | 1988-04-26 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10295588A JPH01273333A (en) | 1988-04-26 | 1988-04-26 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01273333A true JPH01273333A (en) | 1989-11-01 |
Family
ID=14341223
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10295588A Pending JPH01273333A (en) | 1988-04-26 | 1988-04-26 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01273333A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01300537A (en) * | 1988-05-27 | 1989-12-05 | Sharp Corp | Manufacture of semiconductor device |
| US5269880A (en) * | 1992-04-03 | 1993-12-14 | Northern Telecom Limited | Tapering sidewalls of via holes |
-
1988
- 1988-04-26 JP JP10295588A patent/JPH01273333A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01300537A (en) * | 1988-05-27 | 1989-12-05 | Sharp Corp | Manufacture of semiconductor device |
| US5269880A (en) * | 1992-04-03 | 1993-12-14 | Northern Telecom Limited | Tapering sidewalls of via holes |
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