JPS62241372A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS62241372A JPS62241372A JP8362886A JP8362886A JPS62241372A JP S62241372 A JPS62241372 A JP S62241372A JP 8362886 A JP8362886 A JP 8362886A JP 8362886 A JP8362886 A JP 8362886A JP S62241372 A JPS62241372 A JP S62241372A
- Authority
- JP
- Japan
- Prior art keywords
- metal
- alloy
- wiring
- contact hole
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 11
- 229910045601 alloy Inorganic materials 0.000 claims abstract description 23
- 239000000956 alloy Substances 0.000 claims abstract description 23
- 229910052751 metal Inorganic materials 0.000 claims abstract description 21
- 239000002184 metal Substances 0.000 claims abstract description 21
- 239000010410 layer Substances 0.000 claims abstract description 20
- 239000011229 interlayer Substances 0.000 claims abstract description 17
- 238000009792 diffusion process Methods 0.000 abstract description 10
- 239000000758 substrate Substances 0.000 abstract description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 2
- 229910004339 Ti-Si Inorganic materials 0.000 abstract 1
- 229910010978 Ti—Si Inorganic materials 0.000 abstract 1
- 238000007493 shaping process Methods 0.000 abstract 1
- 238000004544 sputter deposition Methods 0.000 abstract 1
- 229910021341 titanium silicide Inorganic materials 0.000 abstract 1
- 238000009413 insulation Methods 0.000 description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- -1 7-recide Inorganic materials 0.000 description 1
- 229910000714 At alloy Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000008719 thickening Effects 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置における多層配線構造に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a multilayer wiring structure in a semiconductor device.
本発明は、半導体装置に係り、半導体装置の多１１ｉ＃
配線に於て、層間絶縁膜に開けられたコンタクト穴部に
は少くとも第１の金属または合金が埋められて成り、該
第１の金属または合金の表面がほぼ平担に形成された上
に第２の金属または合金による配線ノーが形成されて成
る事を特徴とする。The present invention relates to a semiconductor device, and the present invention relates to a semiconductor device.
In the wiring, a contact hole formed in an interlayer insulating film is filled with at least a first metal or alloy, and the surface of the first metal or alloy is formed substantially flat. It is characterized in that a wiring node is formed using a second metal or alloy.
従来の半導体装置における層間配ｄｊ構造は、第５図に
示す如き構造をとるのが通例であった。すなわち、Ｓｔ
基板１の表面には下地配線となる拡散ｌ−配、腺２２と
層間絶縁膜２５が形成され、核層間絶縁ｇ２３内に前記
拡散層配線２２上にコンタクト穴が開けられ、それら表
面に１層または２層の金？４または合金から成る１！！
、極２４が形成されて成るのが通例であった。The interlayer dj structure in a conventional semiconductor device usually has a structure as shown in FIG. That is, St
A diffusion layer wiring layer 22 and an interlayer insulating film 25 are formed on the surface of the substrate 1, and a contact hole is formed on the diffusion layer wiring 22 in the core interlayer insulation g23. Or two layers of gold? 4 or 1 consisting of an alloy! !
, poles 24 were usually formed.
しかし、上記従来技術によると、第３図のコンタクト穴
部に例示した如く、電極２４がコンタクト穴部に於てつ
きまわりが悪く、断線するという問題点と、更に上部に
層間、他縁膜を形成して、コンタクト穴部上に上層ＰＪ
Ｌ極を配線すると、該コンタクト穴部に於て上層電極配
線が更にＷ＋線するという問題点がある。However, according to the above-mentioned prior art, as illustrated in the contact hole portion of FIG. 3, there are problems in that the electrode 24 has poor coverage in the contact hole portion and breaks, and furthermore, an interlayer or other border film is formed on the upper part. The upper layer PJ is formed on the contact hole.
When wiring the L pole, there is a problem that the upper layer electrode wiring further becomes a W+ line in the contact hole.
本発明は、かかる従来技術の問題点をなくし、半導体装
置における多層配線構造に関し、１１間絶Ｒ模のコンタ
クト穴部における成極配線表面の平担化を計ることを目
的とする。It is an object of the present invention to eliminate the problems of the prior art and to flatten the surface of the polarized wiring in the contact hole portion of the 11-interval radius pattern in a multilayer wiring structure in a semiconductor device.
上記問題点を解決するために、半導体装置の多層配線に
於て、ノー間絶縁膜に開けられたコンタクト穴部には少
くとも第１の金属または合金が埋ま込まれて成り、該第
１の金属または合金の表面がほぼ平担に形成された上に
第２の金属または合金による配線層を形成する手段をと
る。In order to solve the above-mentioned problems, in a multilayer wiring of a semiconductor device, at least a first metal or alloy is filled in a contact hole formed in a no-interval insulating film, and the first The first metal or alloy has a substantially flat surface, and then a wiring layer made of a second metal or alloy is formed.
以下、実施例によシ本発明を詳述する。 Hereinafter, the present invention will be explained in detail with reference to Examples.
第１図は本発明による配線構造の一例を示すものであり
、Ｓｔ基板１の表面には拡散配線２、層間絶縁ノ漠３が
形成され、該ノー間絶縁膜５内の前記拡散層配線２上に
はコンクメト穴が開けられ、該コンクタト大内にはチタ
ン・７リサイドや多結晶シリコン等から成る；４１の金
属または合金がＣ”ｉ’Ｄ等で部分的に埋め込まれて成
り、コンタクト穴埋込み配線４が層間絶縁膜表面とほぼ
平担に形成され、該平担面上に第２の金属または合金と
してのｈＬ−ＴＩ−３１層等が電極５としてヌパンタ法
等で形成されて成る。FIG. 1 shows an example of a wiring structure according to the present invention, in which a diffusion wiring 2 and an interlayer insulation layer 3 are formed on the surface of an St substrate 1, and the diffusion layer wiring 2 in the insulation film 5 is formed on the surface of an St substrate 1. A contact hole is made on the top, and inside the contact hole, a metal or alloy made of titanium, 7-recide, polycrystalline silicon, etc. is partially filled with C"i'D, etc., and the contact hole is A buried wiring 4 is formed substantially flat with the surface of the interlayer insulating film, and an hL-TI-31 layer or the like as a second metal or alloy is formed as an electrode 5 on the flat surface by the Nupanta method or the like.
扇２図は本発明による配線構造のその他の実施列であり
、Ｓｔ基板１１の表面には拡散増配＋截１２、層間絶縁
膜１５が形成され、該層間絶縁膜１６に開けられた拡散
層配線１２との接続のためのコンタクト穴部には第１の
配線層としてコンタクト穴埋込み配＠１４として、Ｃｖ
Ｄでチタン・シリナイドや＾を合金膜がその表面が平担
になるように層間絶縁膜１５上に延在して形成され、そ
の上に＠２の配線としてｈＬ合金膜が電極１５として形
成されて成る。Figure 2 shows another implementation of the wiring structure according to the present invention, in which a diffusion thickening + cutting 12 and an interlayer insulating film 15 are formed on the surface of the St substrate 11, and a diffusion layer wiring opened in the interlayer insulating film 16. In the contact hole portion for connection with 12, Cv
In D, a titanium silinide or ^ alloy film is formed extending over the interlayer insulating film 15 so that its surface is flat, and an hL alloy film is formed as the electrode 15 as the wiring @2 on top of the interlayer insulating film 15. It consists of
尚本央捲例では拡散層配線２．１２としてシリコン配線
を例示したが、下地配線としてＡｔ合金膜が更に下地の
絶縁膜上に形成された状態であっても良い事は云うまで
もない。In this central example, a silicon wiring is illustrated as the diffusion layer wiring 2.12, but it goes without saying that an At alloy film may be further formed on the underlying insulating film as the underlying wiring.
本発明の如く、半導体装置の多層配線に於て、層間絶縁
膜に開けられたコンタクト穴部には少くとも＞４１の金
属または合金が埋め込まれて成り、該第１の金属または
合金の表面がほぼ平担に形成された上に第２の金属また
は合金による配線層を形成することにより、半導体装置
に２ける多；−配置メにおいて、配、腺ノーのコンタク
ト穴部内及び穴部表面での断線をなくすることができる
という効果がある。As in the present invention, in a multilayer wiring of a semiconductor device, a contact hole formed in an interlayer insulating film is filled with at least a >41 metal or alloy, and the surface of the first metal or alloy is By forming a second metal or alloy wiring layer on a substantially flat wiring layer, it is possible to create a semiconductor device with a second metal or alloy wiring layer. This has the effect of eliminating disconnections.
第１図及びＪ２図は本発明の実施例を示す多層配線構造
の断面図？、第５図は従来技術による多層配線構造の断
面図を示す。
１．１１．２１・・・・・・８１基板
２．１２．２２・・・・・・拡散層配線５、 １ ５．
２６・−−−・り一間絶縁ノｊ莫４．１４・・・・・
・・・・・・・・・・コンタクト穴埋込み配線５、１５
．２４−−−・・−’！ｉ極。
第１図
第２図
第３図1 and J2 are cross-sectional views of a multilayer wiring structure showing an embodiment of the present invention. , FIG. 5 shows a cross-sectional view of a multilayer wiring structure according to the prior art. 1.11.21...81 substrate 2.12.22...diffusion layer wiring 5, 1 5.
26・---・Insulation between 4.14...
・・・・・・・・・Contact hole embedded wiring 5, 15
．． 24---...-'! i pole. Figure 1 Figure 2 Figure 3
Claims (1)
コンタクト穴部には少くとも第１の金属または合金が埋
め込まれて成り、該第１の金属または合金の表面がほぼ
平担に形成された上に第２の金属または合金による配線
層が形成されて成る事を特徴とする半導体装置。In multilayer wiring of a semiconductor device, at least a first metal or alloy is embedded in a contact hole formed in an interlayer insulating film, and the surface of the first metal or alloy is formed to be substantially flat. 1. A semiconductor device characterized in that a wiring layer made of a second metal or alloy is formed thereon.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8362886A JPS62241372A (en) | 1986-04-11 | 1986-04-11 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8362886A JPS62241372A (en) | 1986-04-11 | 1986-04-11 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62241372A true JPS62241372A (en) | 1987-10-22 |
Family
ID=13807735
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8362886A Pending JPS62241372A (en) | 1986-04-11 | 1986-04-11 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62241372A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5489796A (en) * | 1992-03-30 | 1996-02-06 | Texas Instruments Incorporated | Integrated circuit resistor comprising amorphous silicon |
| US6320260B1 (en) * | 1993-10-12 | 2001-11-20 | Kabushiki Kaisha Toshiba | Semiconductor device and method for manufacturing the same |
-
1986
- 1986-04-11 JP JP8362886A patent/JPS62241372A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5489796A (en) * | 1992-03-30 | 1996-02-06 | Texas Instruments Incorporated | Integrated circuit resistor comprising amorphous silicon |
| US6320260B1 (en) * | 1993-10-12 | 2001-11-20 | Kabushiki Kaisha Toshiba | Semiconductor device and method for manufacturing the same |
| US6326691B1 (en) | 1993-10-12 | 2001-12-04 | Kabushiki Kaisha Toshiba | Semiconductor device and method for manufacturing the same |
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