JPS63237441A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS63237441A JPS63237441A JP7221987A JP7221987A JPS63237441A JP S63237441 A JPS63237441 A JP S63237441A JP 7221987 A JP7221987 A JP 7221987A JP 7221987 A JP7221987 A JP 7221987A JP S63237441 A JPS63237441 A JP S63237441A
- Authority
- JP
- Japan
- Prior art keywords
- conductor
- insulating film
- connecting hole
- semiconductor device
- connection hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 239000004020 conductor Substances 0.000 claims abstract description 24
- 239000002184 metal Substances 0.000 claims abstract description 14
- 229910052751 metal Inorganic materials 0.000 claims abstract description 13
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 10
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 10
- 239000010937 tungsten Substances 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 4
- 229910000838 Al alloy Inorganic materials 0.000 claims description 2
- 230000008018 melting Effects 0.000 claims description 2
- 238000002844 melting Methods 0.000 claims description 2
- 229910001092 metal group alloy Inorganic materials 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 10
- 238000005530 etching Methods 0.000 abstract description 5
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 3
- 238000004544 sputter deposition Methods 0.000 abstract description 2
- 238000004519 manufacturing process Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 238000001459 lithography Methods 0.000 description 2
- 230000035515 penetration Effects 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
この発明は半導体装置に関し、特に接続孔等を有する半
導体装置の孔内の埋込み技術に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and more particularly to a technique for embedding a hole in a semiconductor device having a connection hole or the like.
［従来の技術］
第２Ａ図および第２Ｂ図は従来の半導体装置の概略製造
工程図である。[Prior Art] FIGS. 2A and 2B are schematic manufacturing process diagrams of a conventional semiconductor device.
図を参照して、以下製造方法について説明する。The manufacturing method will be described below with reference to the drawings.
半導体基板（図示せず）に形成された導体領域１上に絶
縁膜２を堆積して形成した後、リソグラフィ技術および
エツチング法を用いて所望の位置に接続孔３を形成する
（第２Ａ図参照）。After forming an insulating film 2 by depositing it on a conductor region 1 formed on a semiconductor substrate (not shown), a contact hole 3 is formed at a desired position using lithography technology and an etching method (see FIG. 2A). ).
次に、たとえばタングステンをＣＶＤ法等で選択的に堆
積させることによって接続孔３を充填していた（第２Ｂ
図参照）。Next, the connection hole 3 was filled by selectively depositing tungsten, for example, by a CVD method (Second B
(see figure).
ここで、タングステン５を充填するのは直接絶縁膜２の
上層のアルミ配線層等を接続孔に形成した場合のステッ
プカバレッジの問題を解消すべく絶縁膜２の上面を平坦
化して良好な外部配線層と導体領域１との接続を確保し
ようとするためである。Here, the filling with tungsten 5 is to flatten the upper surface of the insulating film 2 to solve the problem of step coverage when an aluminum wiring layer or the like on the upper layer of the insulating film 2 is formed in the connection hole. This is to ensure the connection between the layer and the conductor region 1.
［発明が解決しようとする問題点コ
上記のような従来の半導体装置では、タングステン５と
絶縁膜２とが直接接しているので密着性が悪く、特にタ
ングステンをバリアメタルとして使用したとき絶縁膜２
との境界面を通して上層のアルミ配線等の突き抜は現象
が起こりやすいという問題点があった。[Problems to be Solved by the Invention] In the conventional semiconductor device as described above, the tungsten 5 and the insulating film 2 are in direct contact with each other, resulting in poor adhesion, and especially when tungsten is used as a barrier metal, the insulating film 2
There was a problem in that a phenomenon was likely to occur when the upper layer aluminum wiring etc. was punched through the interface with the aluminum wire.
この発明はかかる問題点を解決するためになされたもの
で、タングステン等の金属層を接続孔に充填する利点は
そのままに、金属層と絶縁膜との密告性の優れた半導体
装置を提供することを目的とする。The present invention has been made to solve these problems, and provides a semiconductor device that maintains the advantages of filling connection holes with a metal layer such as tungsten and has excellent contact between the metal layer and the insulating film. With the goal.
［問題点を解決するための手段］
この発明に係る半導体装置は、接続孔内の側壁に導体を
形成した後、接続孔に金属層を充填する°ものである。[Means for Solving the Problems] In the semiconductor device according to the present invention, a conductor is formed on the side wall of the contact hole, and then the contact hole is filled with a metal layer.
［作用］
この発明においては、接続孔内の側壁に形成された導体
と金属層との密亡性が良いので、金属層の境界面におけ
る配線層の突き抜は現象を生じさせない。[Operation] In the present invention, since the conductor formed on the side wall of the connection hole and the metal layer have good tightness, penetration of the wiring layer at the interface between the metal layers does not cause any phenomenon.
［実施例〕
第１Ａ図および第１Ｂ図はこの発明の一実施例を示す概
略製造工程図である。[Example] Figures 1A and 1B are schematic manufacturing process diagrams showing an example of the present invention.
以下、図を参照して製造方法について説明する。The manufacturing method will be described below with reference to the drawings.
半導体基板（図示せず）に形成された導体領域１に絶縁
膜２を形成した後、リソグラフィ技術およびエツチング
法を用いて所望の位置に接続孔３を形成するのは従来例
と同様である。次にこの接続孔３内にたとえばアモルフ
ァスシリコン等の絶縁膜２との整合性の良い導体ｒｃｖ
ｐ法やスパッタ法等で形成し、続いてこれを異方性エツ
チング法で所定部分を除去することによ゛って接続孔３
の側壁に導体４を残す（第１Ａ−参照）。As in the conventional example, after forming an insulating film 2 on a conductor region 1 formed on a semiconductor substrate (not shown), a connection hole 3 is formed at a desired position using lithography and etching. Next, a conductor rcv made of amorphous silicon or the like having good matching with the insulating film 2 is placed in the connection hole 3.
The connection hole 3 is formed by forming it by a p-method, sputtering method, etc., and then removing a predetermined portion by an anisotropic etching method.
The conductor 4 is left on the side wall of the (see 1A-).
導体４が残った接続孔３内にたとえばタングステンをＣ
ＶＤ法等で選択的に堆積させることによって充填した後
、絶縁膜２の上面を平坦化する（第１Ｂ図参照）。For example, tungsten is placed in the connection hole 3 where the conductor 4 remains.
After filling by selective deposition using a VD method or the like, the upper surface of the insulating film 2 is flattened (see FIG. 1B).
以降、絶縁膜２上に配線層等を形成する工程等が続くが
、この発明外故に説明を省略する。Thereafter, the process of forming a wiring layer etc. on the insulating film 2 continues, but the description thereof will be omitted since it is outside the scope of this invention.
なお、上記実施例では導体はアモルファスシリコンとし
ているが、高融点金属やアルミ合金等の絶縁膜との整合
性の良いものであれば同様の効果を奏する。In the above embodiment, the conductor is made of amorphous silicon, but the same effect can be obtained if the conductor is made of a high melting point metal, aluminum alloy, or the like and has good compatibility with the insulating film.
また、上記実施例では、接続孔を例としているが半導体
装置のスルーホールにも適用できることは言うまでもな
い。Further, in the above embodiments, a connection hole is used as an example, but it goes without saying that the present invention can also be applied to a through hole of a semiconductor device.
［発明の効果］
この発明は以上説明したとおり、接続孔の側壁に金属層
との密着性の良い導体を形成したので、金属層の境界面
における配線層の突き抜は現象を防止し、安定した配線
構造となる効果がある。[Effects of the Invention] As explained above, this invention forms a conductor with good adhesion to the metal layer on the side wall of the connection hole, thereby preventing the phenomenon of penetration of the wiring layer at the interface between the metal layers and providing stable This has the effect of creating a wiring structure that is
第１Ａ図および第１Ｂ図はこの発明の一実施例を示す概
略製造工程図、第２Ａ図および第２Ｂ図は従来の半導体
装置の概略製造工程図である。
図において、１は導体領域、２は絶縁膜、３は接続孔、
４は導体、５はタングステンである。
なお、各図中同一符号は同一または相当部分を示す。1A and 1B are schematic manufacturing process diagrams showing one embodiment of the present invention, and FIGS. 2A and 2B are schematic manufacturing process diagrams of a conventional semiconductor device. In the figure, 1 is a conductor region, 2 is an insulating film, 3 is a connection hole,
4 is a conductor, and 5 is tungsten. Note that the same reference numerals in each figure indicate the same or corresponding parts.
Claims (4)
と、 前記半導体基板に形成される導体領域と、 前記半導体基板上に形成され、かつ前記導体領域に対応
した前記接続孔を有する絶縁膜と、前記接続孔内の側壁
に形成された導体と、 前記導体を除いた前記接続孔内を充填する金属層とを備
えた、半導体装置。(1) A semiconductor device having a connection hole, comprising: a semiconductor substrate; a conductor region formed on the semiconductor substrate; and an insulating film formed on the semiconductor substrate and having the connection hole corresponding to the conductor region. A semiconductor device comprising: a conductor formed on a side wall within the connection hole; and a metal layer filling the inside of the connection hole except for the conductor.
およびアルミ合金よりなる一群から選択される、特許請
求の範囲第１項記載の半導体装置。(2) The semiconductor device according to claim 1, wherein the conductor is selected from the group consisting of amorphous silicon, high melting point metal, and aluminum alloy.
求の範囲第１項または第２項記載の半導体装置。(3) The semiconductor device according to claim 1 or 2, wherein the connection hole constitutes a through hole.
範囲第１項、第２項または第３項記載の半導体装置。(4) The semiconductor device according to claim 1, 2, or 3, wherein the metal layer is tungsten.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7221987A JPS63237441A (en) | 1987-03-25 | 1987-03-25 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7221987A JPS63237441A (en) | 1987-03-25 | 1987-03-25 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63237441A true JPS63237441A (en) | 1988-10-03 |
Family
ID=13482916
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7221987A Pending JPS63237441A (en) | 1987-03-25 | 1987-03-25 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63237441A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5011791A (en) * | 1989-02-03 | 1991-04-30 | Motorola, Inc. | Fusible link with built-in redundancy |
| US5317192A (en) * | 1992-05-06 | 1994-05-31 | Sgs-Thomson Microelectronics, Inc. | Semiconductor contact via structure having amorphous silicon side walls |
| US5851581A (en) * | 1994-04-22 | 1998-12-22 | Nec Corporation | Semiconductor device fabrication method for preventing tungsten from removing |
-
1987
- 1987-03-25 JP JP7221987A patent/JPS63237441A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5011791A (en) * | 1989-02-03 | 1991-04-30 | Motorola, Inc. | Fusible link with built-in redundancy |
| US5317192A (en) * | 1992-05-06 | 1994-05-31 | Sgs-Thomson Microelectronics, Inc. | Semiconductor contact via structure having amorphous silicon side walls |
| US5851581A (en) * | 1994-04-22 | 1998-12-22 | Nec Corporation | Semiconductor device fabrication method for preventing tungsten from removing |
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