JPH09283617A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a highly integrated semiconductor device, by a method wherein the margin for positional deviation which is required to provide for the connection hole used to connect wirings is decreased in the wirings of a semiconductor device. SOLUTION: A wiring consisting of different layers is insulated by a first and a second insulating layers 7 and 8 having an etching selectivity, a piece of metal 4 is filled in a connection hole provided on the first insulating layer 7 only, and different wiring layers 2 are connected through the filled-in metal. As the filling metal can be brought into contact not with only the upper surface of the wiring but also with the side face of the wiring, sufficient connection can be obtained without providing a margin for positional deviation. As a result, the margin for positional deviation can be decreased, and the degree of integration of a semiconductor device can be improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to improvement of a wiring structure and a method of manufacturing the same.

[0002]

2. Description of the Related Art FIG. 4 is a schematic view showing a wiring structure in a conventional semiconductor device. 4 (a) is a top view, FIG.
4B is a sectional view taken along line XX ′ in FIG.
In the figure, 1 is a semiconductor substrate, 2 is a wiring layer, 3 is an insulating layer, and 4 is a filling metal layer.

FIG. 5 is a process explanatory view of a method of forming the wiring structure of FIG. First, as shown in FIG. 5A, the wiring layer 2 is formed on the semiconductor substrate 1 on which the element is formed, and the insulating layer 3 is formed so as to cover the wiring layer 2. Next, as shown in FIG. 5B, a connection hole for connecting the wiring layer 2 and the upper wiring is formed by etching, and as shown in FIG. 5C, the connection hole is exposed. The filling metal layer 4 is formed in the connection hole by the selective growth method using the wiring layer 2 as a nucleus.

[0004]

In the process of FIG. 5B, there is a possibility that misalignment between the wiring layer and the connection hole may occur. Therefore, as shown in FIG. 4, the wiring layer 2 corresponding to the periphery of the connection hole has a large wiring width with a margin 5 for misalignment. As a result, as shown in FIG.
(A) is a top view and FIG. 6 (b) is a sectional view taken along line XX 'in FIG. 6 (a). As shown in FIG. A connection with 2 can be made. However, since an extra area for the margin is required for the wiring layer, the area of the semiconductor device is increased and the integration degree is reduced. As the semiconductor microfabrication technology advances and the sizes of wirings and connection holes become smaller, the influence of this misalignment is considered to hinder further high integration of semiconductor devices.

The present invention has been made in view of the above problems, and its object is to reduce the margin of the wiring with respect to the connection hole and to obtain a reliable connection between the wiring and the filling metal. It is to provide a semiconductor device capable of

[0006]

In order to solve the above problems, according to the present invention, wirings of different layers are arranged in multiple layers with an insulating layer sandwiched therebetween, and a connecting hole is provided in the insulating layer. In a semiconductor device in which wirings of different layers are connected through filled metal layers, the depth of the connection hole reaches the height of the side surface of the wiring.

According to the present invention, the filled metal makes contact with not only the upper surface of the wiring layer but also the side surface of the wiring layer, so that a reliable connection can be obtained.

Further, according to the present invention, first and second insulating layers having different etching selectivity are formed between different wiring layers, a connection hole is formed only in the first insulating layer, and a metal is formed in the formed connection hole. To be filled.

According to the present invention, the filled metal makes contact not only with the upper surface of the wiring layer but also with the side surface of the wiring layer, so that a reliable connection can be obtained. Moreover, unlike the conventional case, it is not necessary to provide a margin for misalignment in the wiring layer, so that the margin of the wiring with respect to the connection hole can be reduced and a reliable connection between the wiring and the filling metal can be obtained. It becomes possible to provide a device.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a schematic diagram showing a wiring structure in a semiconductor device of the present invention. 1A is a top view, and FIG. 1B is a sectional view taken along line XX ′ of FIG. In the figure, 1 is a semiconductor substrate, 2 is a wiring layer, 7 is a first insulating layer, 8 is a second insulating layer, and 4 is a filling metal layer. As the second insulating layer 8, an insulating layer having etching selectivity with respect to the first insulating layer 7 is used. As can be seen from FIG. 1, the wiring layer 2 has no margin for misalignment. This is because the filling metal layer 4 comes into contact with the upper surface and the side surface of the wiring layer 2 and a sufficient contact area can be obtained. FIG. 1 shows the case where the misalignment occurs, but when the misalignment does not occur, the state is as shown in FIG. 2, and good connection can be obtained at the upper surface portion of the wiring layer 2.

FIG. 3 is a process explanatory view of the method for forming the wiring structure of FIG. First, as shown in FIG. 3A, a wiring layer 2 is formed on a semiconductor substrate 1 on which elements are formed, a second insulating layer 8 thinner than the thickness of the wiring layer 2 is formed, and a first insulating layer 8 is formed thereon. The insulating layer 7 is formed. Next, as shown in FIG. 3B, a connection hole for connecting the wiring layer 2 and the upper wiring is formed by etching. At this time, since the second insulating layer 8 has etching selectivity with respect to the first insulating layer 7, the connection hole can be opened only to the first insulating layer 7.
Next, as shown in FIG. 3C, the filling metal layer 4 is formed in the connection hole by a selective growth method using the wiring layer 2 exposed in the connection hole as a nucleus, and the upper surface portion of the wiring layer 2 and Connect to the side part.

If the second insulating layer 8 is not provided, in order to adjust the depth of the connection hole to the height of the side surface of the wiring layer 2, it is necessary to accurately adjust the etching. If the etching adjustment is inappropriate, for example, as shown in FIG. 3D, a connection hole will be opened up to the upper surface of the semiconductor substrate 1, and if a filling metal layer is filled therein, the semiconductor substrate will be formed as shown in FIG. 3E. There is a possibility that they may also come into contact with each other and cause a short circuit with the element. The second insulating layer 8 is effective for easily and reliably connecting the wiring layer and the filling metal layer 4.

[0013]

As described in the above embodiments of the present invention, according to the present invention, the filled metal contacts not only the upper surface of the wiring layer but also the side surface of the wiring layer, so that a reliable connection can be obtained. You can Moreover, unlike the conventional case, since it is not necessary to provide a margin for misalignment in the wiring layer, the margin of the wiring with respect to the connection hole can be reduced and a reliable connection between the wiring and the filling metal can be obtained.

[Brief description of drawings]

FIG. 1 is a schematic diagram of a wiring structure according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of a wiring structure according to an embodiment of the present invention.

FIG. 3 is a process explanatory view of a method for forming a wiring structure according to an embodiment of the present invention.

FIG. 4 is a schematic diagram of a conventional wiring structure.

FIG. 5 is a process explanatory view of a conventional method for forming a wiring structure.

FIG. 6 is a schematic diagram of a conventional wiring structure when misalignment occurs.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Wiring layer 3 Insulating layer 4 Filling metal layer 5 Misalignment margin 6 Misalignment 7 First insulating layer 8 Second insulating layer

Claims (3)

[Claims] 1. Wirings of different layers are arranged in multiple layers sandwiching an insulating layer, connection holes are provided in the insulation layer, and wirings of different layers are connected via a metal layer filled in the connection holes. In the semiconductor device, the depth of the connection hole reaches the height of the side surface of the wiring. 2. The wirings of different layers are arranged in multiple layers with a first insulating layer and a second insulating layer having etching selectivity with respect to the first insulating layer sandwiched between the first insulating layer and the first insulating layer. In a semiconductor device in which a connection hole is provided in a layer and wirings of different layers are connected through a metal layer filled in the connection hole, the depth of the connection hole is up to the height of the upper surface of the second insulating layer. A semiconductor device characterized by having reached. 3. A step of forming a wiring layer on a semiconductor substrate, a step of forming a first insulating layer for insulating the wiring layer, and an etching selectivity with respect to the first insulating layer. A method of manufacturing a semiconductor device, comprising: a step of forming a second insulating layer; a step of forming a connection hole in the first insulating layer; and a step of filling the connection hole with a metal.