JP2705111B2 - Method for manufacturing multilayer wiring structure of semiconductor integrated circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a method for manufacturing a multilayer wiring structure in which each layer is insulated by a gap.

[Conventional technology]

Conventionally, in a multilayer wiring structure of a semiconductor integrated circuit,
There has been proposed a configuration in which a gap is formed at the intersection of a layer wiring and a second layer wiring formed thereon with an insulating film interposed therebetween, and the gap is used to insulate both wirings.

That is, as shown in FIG. 4, a silicon oxide film 2 is formed on a silicon substrate 1, a first layer wiring 3 is formed in a concave portion of the silicon oxide film 2, and intersects with the first layer wiring 3. The second layer wiring 5 is formed on the silicon oxide film 2.
In this configuration, a gap 6 corresponding to the difference between the thickness of the first layer wiring 3 and the depth of the recess is defined in the recess of the silicon oxide film 2, and the intersection between the first layer wiring 3 and the second layer wiring 5 is formed. In the portion, the gap 6 functions as an insulating layer.

[Problems to be solved by the invention]

In the above-described wiring structure, the first layer wiring 3 and the second layer wiring 5
Since the insulation at the intersection of is air, the dielectric constant is low, the capacitance between both wirings is reduced, and high-speed operation is possible. However, in this configuration, the wiring is exposed to the atmosphere,
There is a problem that it is susceptible to external contamination and moisture in an assembly process and the like. Further, when a metal piece or the like is mixed in the gap 6, there is a problem that the first layer wiring 3 and the second layer wiring 5 are short and the reliability is reduced.

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned problems and to provide a multilayer wiring structure of a semiconductor integrated circuit with improved reliability.

[Means for solving the problem]

According to the manufacturing method of the present invention, a step of embedding a first layer wiring in a concave portion of an insulating film provided on a semiconductor integrated circuit substrate, a step of covering the surface of the first layer wiring with a first insulating film, Filling the inside with a second insulating film to planarize the surface thereof, forming a third insulating film on the surface of the second insulating film, and forming the first layer wiring and the second layer in the concave portion. A step of selectively etching the third insulating film, the second insulating film, and the first insulating film at a place where electrical connection with wiring is required to form a through-hole; and forming the second insulating film in the through-hole. Forming a fourth insulating film connected to the first insulating film and the third insulating film on the inner surface of the semiconductor device, and forming a second layer wiring on the first insulating film, the third insulating film, and the fourth insulating film Forming a fifth insulating film on the surface of the second layer wiring; And a step of removing the second insulating film in the serial recess.

[Action]

In the above-described configuration, since the two wirings are insulated by the gap, the capacity between the wirings is reduced, and the surfaces of the two wirings are covered with the insulating film, thereby preventing external influences and short circuits due to metal pieces and the like.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a longitudinal sectional view of a main part of one embodiment of the present invention. In the figure, this multilayer wiring structure is a silicon substrate 1
A recess is formed in the silicon oxide film 2 formed thereon, and a first aluminum film having a thickness smaller than the depth of the recess is formed in the recess.
The layer wiring 3 is formed. At this time, the CVD oxide film 4 is formed on the upper surface of the first layer wiring 3. Then, after removing a part of the CVD oxide film 4, a second layer wiring 5 is formed of an aluminum film on the silicon oxide film 2, and is connected to or crosses the first layer wiring 3. . At this time, a gap 6 as shown in the drawing is formed between the first layer wiring 3 and the second layer wiring 5 in the recess, and both wirings are insulated through the gap 6. Note that CVD oxide films 7, 8, and 9 are formed on the side surface, the lower surface, and the upper surface of the second layer wiring 5, respectively.

An example of a method for manufacturing this multilayer wiring structure will be described with reference to the vertical sectional views of FIGS. 2 (a) to 2 (c).

First, as shown in FIG.
A μm silicon oxide film 2 is formed. A photoresist film having a required pattern is formed thereon, and a silicon oxide film in a portion where a first layer wiring is to be formed is formed by using the photoresist film as a mask.
A recess is formed by etching by 2 μm. The photoresist is left as it is, and a 0.5 μm aluminum layer is grown on the silicon oxide film 2 and the photoresist by a sputtering method. Then, by removing and removing the photoresist, the aluminum layer formed on the photoresist is simultaneously removed, and the first layer wiring 3 is formed with the remaining aluminum layer. Further, a 1000 ° oxide film 4 is formed on the entire surface by the CVD method, and a silicon polyimide film 11 is applied thereon to flatten the upper surface.

Next, as shown in FIG. 2B, the silicon polyimide film 11 is etched back until the CVD oxide film 4 is exposed, and the concave portion of the silicon oxide film 2 is flattened. On top of this, CV again
An oxide film 8 of 1000 ° is formed by the method D, and a photoresist 12 is further applied on the entire surface. After that, the photoresist 12 at a position where a through hole for connecting the second layer wiring to the first layer wiring 3 is to be formed is removed, and the CVD oxide film 8 is etched in a CF ₄ gas. Further, the CVD oxide film 4 below the silicon polyimide film 11 exposed in the through-hole opening 13 is continuously etched in a CF ₄ + O ₂ -based gas.

Thereafter, as shown in FIG. 2C, the photoresist 12 is removed, an oxide film is formed by a CVD method, and the CVD oxide film deposited on the bottom of the through-hole opening 13 by anisotropic etching or the like is removed. By removing, the CVD oxide film 7 is formed only on the side surface of the through-hole opening 13. Moreover,
A 1.0 μm aluminum film to be a second layer wiring is formed by a sputtering method, and the second layer wiring 5 having a required pattern is formed by etching using a photoresist as a mask.

Thereafter, it is exposed to a portion other than the second layer wiring 5.
The CVD oxide film 8 is etched, and the exposed silicon polyimide film 11 is removed. Finally, the second layer wiring 5
The second layer wiring 5 is covered with the CVD oxide film 9 by growing a CVD oxide film 9 on the
A wiring structure having a layer structure can be formed.

According to this configuration, since the gap 6 is formed at the intersection of the first layer wiring 3 and the second layer wiring 5, the wiring delay due to the capacitance using the first layer wiring 3 and the second layer wiring 5 as electrodes. Needless to say, is minimized. In addition, this gap 6
Both surfaces of the first layer wiring 3 and the second layer wiring 5 opposed to each other are covered with an insulating film composed of the CVD oxide films 4, 7, 8, and 9, so that contamination and moisture in the assembling process and the like are prevented. It is not affected, and both wires do not short-circuit even when a metal piece or the like enters.

The coating film used in this embodiment is not limited to a silicon polyimide film, and may be any material that does not peel off when the photoresist is peeled off. In addition, it is natural from the gist of the present invention that aluminum used for the wiring may include silicon or copper.

FIG. 3 is a cross-sectional view showing another embodiment of the present invention, particularly showing a response during the manufacturing process. The same parts as those in FIGS. 1 and 2 are denoted by the same reference numerals.

In this embodiment, the CVD formed on the lower side of the second layer wiring 5 is performed.
The film is a nitride film 8A, and the coating film used to form the gap 6 defined between the first layer wiring 3 and the second layer wiring 5 is a photoresist 11A.

That is, in this example, as in the embodiment of FIG. 1, a first layer wiring 3 is formed and a CVD
After forming the oxide film 4, a photoresist 11A is applied,
Etch back until the CVD insulating film 4 on the silicon oxide film 2 is exposed. Next, a nitride film 8A of 1000 ° is formed thereon by the CVD method. And a photoresist on top of this
A mask is formed at 12, and a through-hole opening 13 is opened. Thereafter, the CVD nitride film 8A is removed by etching, and the photoresist 11A and the photoresist 12 in the exposed through-hole openings are removed by etch-back. This can be realized by setting the etch-back time to a time sufficient to etch back a method having a large film thickness of the two types of photoresist.

Then, the CVD oxide film 4 exposed at the bottom of the through hole is
Etching is removed using the VD nitride film 8A as a mask. Thereafter, a CVD film for covering the side wall of the through hole is formed in the same manner as in the embodiment of FIG. 1, and the CVD film remaining on the bottom surface of the through hole portion is removed by etch back to remove the second layer wiring. Form.

According to this embodiment, the only coating film to be used is a photoresist, and the etching process is simplified as compared with the above embodiment.

〔The invention's effect〕

As described above, according to the present invention, the first insulating film, the second insulating film, and the third insulating film are formed after the first layer wiring is buried in the concave portion, and the fourth insulating film is formed after opening the through hole. Forming a second layer wiring thereon, forming a fifth insulating film, and then removing the second insulating film, so that the first layer wiring and the second layer wiring are formed in the recess. Third
And a multilayer wiring structure in which an insulating film is interposed between the fourth insulating film and the air gap, whereby the capacitance between the two wirings can be reduced to suppress wiring delay, and the surfaces of both wirings are exposed to the outside. It is possible to obtain a highly reliable multilayer wiring structure by eliminating the influence of external contamination and moisture, and preventing short-circuiting due to metal pieces and the like.

[Brief description of the drawings]

FIG. 1 is a longitudinal sectional view of one embodiment of a multilayer wiring structure of a semiconductor integrated circuit according to the present invention, and FIGS. 2 (a) to 2 (c).
Is a longitudinal sectional view showing a method of manufacturing the structure of FIG. 1 in the order of steps, FIG. 3 is a longitudinal sectional view in the middle of a manufacturing step in another embodiment of the present invention, and FIG. It is a longitudinal cross-sectional view of a structure. DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 2 ... Silicon oxide film, 3 ... First layer wiring, 4 ... CVD oxide film, 5 ... Second layer wiring, 6 ...
… Voids, 7-9 …… CVD oxide film, 8A …… CVD nitride film, 11…
… Silicon polyimide film, 11A …… Photoresist, 12
...... Photoresist, 13 ... Through hole opening.

Claims (1)

(57) [Claims] An insulating film provided on a substrate of a semiconductor integrated circuit, wherein a first layer wiring formed thinner than a depth of the recess and a second layer wiring formed on the insulating film are formed. A multilayer insulated by a gap defined in the recess of the insulating film at the intersection of the two wirings, and at least the surfaces of the first-layer wiring and the second-layer wiring facing the gap are each covered with an insulating film. A method for manufacturing a wiring structure, comprising: burying a first layer wiring in a recess of an insulating film provided on the semiconductor integrated circuit substrate; and forming a surface of the first layer wiring with the first insulating film. A step of coating, a step of filling a second insulating film in the recess to flatten the surface thereof, a step of forming a third insulating film on the surface of the second insulating film, and a step of forming a third insulating film in the recess. Where the electrical connection between the first layer wiring and the second layer wiring is required. The third insulating film, a second insulating film and the first
Forming a through hole by selectively etching the insulating film; and forming a fourth insulating film connected to the first and third insulating films on the inner surface of the second insulating film in the through hole; Forming a second layer wiring on the first insulating film, the third insulating film, and the fourth insulating film; forming a fifth insulating film on the surface of the second layer wiring; Removing the second insulating film. A method for manufacturing a multilayer wiring structure of a semiconductor integrated circuit, comprising: