JPH07211697A - Formation of metal wiring and fabrication of semiconductor device - Google Patents

Abstract

PURPOSE:To increase the fabrication yield while enhancing the reliability by preventing crack in the insulation film formed on a wiring and corrosion of wiring. CONSTITUTION:A first metal film 2 is deposited on an insulating substrate 1 and a second metal film 3, having the etching selectivity with respect to the first metal film, is deposited thereon. A resist pattern 4 corresponding to a wiring pattern is then formed on the second metal film 2 and the first and second metal films 2, 3 are subjected to collective patterning by a first anisotropic dry etching means thus forming a laminate pattern of first and second metal film patterns 2P, 3P matching the resist pattern 4. The side wall face of the second metal film pattern 3P is then etched into a forward tapered shape 7A while retreating the outer peripheral surface of the resist pattern by a second anisotropic dry etching means having selective etching properties with respect to the resist and the second metal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a metal wiring forming method and a semiconductor device manufacturing method using the metal wiring forming method, and more particularly to a method for forming a laminated metal wiring using two kinds of metals and a method for forming the laminated wiring. The present invention relates to a method for manufacturing a semiconductor device.

In recent years, due to high integration of semiconductor devices, metal wirings arranged in these semiconductor devices have become finer and higher in density, and a laminated layer containing a barrier metal in order to prevent element deterioration due to diffusion of wiring metal. Metal wiring has been widely used.

When the metal wiring is made fine and has a high density, it is important to reduce the resistance of the metal wiring and control the cross-sectional shape in order to improve the performance and reliability of the semiconductor device.

[0004]

2. Description of the Related Art Inverse staggered thin film transistors (TF)
The gate wiring (electrode) used for T) is a two-kind metal in which a titanium (Ti) film serving as a barrier metal is laminated on an aluminum (including an alloy containing aluminum as a main component) (Al) film which is a main conductive metal. Is used.

The two-layer metal gate wiring formed by laminating two kinds of metals as described above has conventionally been formed by the method described below with reference to FIG. Refer to FIG. 3 (a) That is, first, the Al film 52 of the main conductive metal is formed on the insulating substrate 51 such as a glass plate by a sputtering method or the like.
The Ti film 53 serving as a barrier metal is formed on the Al film 52 by a sputtering method or the like, and then a resist pattern 54 having a pattern shape corresponding to the gate wiring is formed on the Ti film 53 using a photolithography technique. .

Next, referring to FIG. 3B, the Ti film 53 and the Al film are formed by anisotropic reactive ion etching (RIE) using the resist pattern 54 as a mask and chlorine (Cl) -based gas as an etching gas. 52
Are collectively patterned into the shape of the gate wiring pattern. 52P and 53P indicate the Al film pattern and the Ti film pattern which have been patterned.

Here, a large amount of Cl contained in the etching gas is adsorbed on the exposed surfaces of the resist pattern 54, the Ti film pattern 53P and the Al film pattern 521P. Next, refer to FIG. 3 (c).
In order to prevent corrosion of the Al film pattern 52P due to hydrochloric acid (HCl) generated by the hydrolysis of Cl adsorbed on the sidewalls of the film pattern 52P and the Ti film pattern 53P, the RIE treatment is performed in the same apparatus as the RIE treatment. Then, an ashing process using oxygen (O ₂ ) plasma is performed to quickly remove the resist pattern 54 that adsorbed Cl, and at the same time, adsorbed on the side wall surfaces of the Al film pattern 52P and the Ti film pattern 53P.
After removing Cl, take it out from the device and
This is a method of completing the formation of the two-layer metal gate wiring 55 in which the Ti film pattern 53P is laminated on P.

[0008]

However, according to the above-mentioned conventional method, as described with reference to FIG. 3 (b), the upper Ti film is formed.
Since both 52 and the lower Al film 53 are aligned with the resist pattern 54 and collectively patterned by the RIE means, the two-layer metal gate wiring 55 to be formed has a cross-sectional shape in which the side wall surface is substantially vertical.

Therefore, as shown in FIG. 4 showing the problem,
When the gate insulating film 56 is formed by vapor phase growth means so as to cover the surface on which the above-mentioned two-layer metal gate wiring 55 is formed, an inverse taper shape is formed on the gate insulating film 56 corresponding to the steep step 57 of the wiring 55. The step 58 is formed, and a crack 59 is generated from the corner of the insulating film step 58 toward the corner of the wiring step, which causes a problem that the withstand voltage of the gate insulating film 56 deteriorates.

Further, in the above conventional method, as shown in FIG.
As described with reference to (b), the upper Ti film 53 and the lower Al film
Since the patterning of the two-layer metal gate wiring 55 is completed in the state where 52 and 52 are collectively patterned using a Cl-based etching gas, a large amount of Cl is adsorbed on the side wall surface of the gate wiring 55 on which the pattern formation is completed. Maintained in a state. Therefore, the Cl adsorbed on the side wall surface of the double-layered gate metal wiring 55 cannot be sufficiently removed only by the ashing treatment with O ₂ plasma shown in FIG. Corrosion occurs in the Al film pattern 52 forming the gate metal wiring 55, and there is a problem in that the yield and reliability of the TFT are reduced due to defects in the gate metal wiring 55 caused by the corrosion of Al.

Therefore, conventionally, immediately after the patterning of the gate metal wiring 55, a plasma treatment with water vapor (H ₂ O) or a washing treatment is additionally performed to remove Cl adsorbed on the side wall surface of the gate metal wiring 55. However, even with this method, the above-mentioned removal of Cl was not sufficient, and it was not possible to sufficiently prevent the yield and reliability from being deteriorated due to the corrosion. Further, there has been a problem that the process is complicated by adding the above process.

Therefore, the present invention provides a method for forming a laminated metal wiring in which the side wall surface is formed with a forward taper and the occurrence of corrosion is prevented without complicating the process. The purpose is to improve the performance and reliability of a semiconductor device provided.

[0013]

The solution to the above problems is to form a laminated metal wiring in which two kinds of metals are laminated.
A step of forming a first metal film on an insulating substrate, and
A step of forming a second metal film on the second metal film, which has etching selectivity with respect to the first metal film, and a resist having a pattern shape corresponding to the wiring pattern on the second metal film. A step of forming a pattern, and the first and second metals matching the resist pattern by collectively patterning the second and first metal films by the first anisotropic dry etching means using the resist pattern as a mask. A step of forming a laminated pattern of film patterns, and a step of forming the resist pattern by a second anisotropic dry etching means having a selective etching property with respect to the resist and the second metal using the resist pattern as a mask. Or a step of etching the side wall surface of the second metal film pattern in a forward tapered shape while retreating the outer peripheral surface, or It is achieved by a method of manufacturing a semiconductor device according to the present invention using a metal wiring forming method for forming a multilayer wiring.

[0014]

1 is a process sectional view for explaining the principle of the metal wiring forming method according to the present invention. In the method for forming a laminated metal wiring in which two kinds of metals are laminated according to the present invention, as shown in FIG. 1 (a), a first metal film 2 and the first metal film 2 are formed on an insulating substrate 1.
A second etching selectivity with respect to the metal film 2 of
After the metal film 3 is formed, a resist pattern 4 having a pattern shape corresponding to the wiring pattern is formed on the second metal film 3, and then, as shown in FIG. 1 (b),
Using the resist pattern 4 as a mask, the second metal film 3 and the second metal film 3 are formed by anisotropic dry etching using an etching gas having etching properties for both the second metal film 3 and the first metal film 2. The first metal film 2 and the second metal film pattern 3P are formed by patterning the first metal film 2 in a lump and the side wall surfaces of the first metal film pattern 2P and the second metal film pattern 3P are formed substantially vertically so that the side wall surfaces thereof are aligned with the side wall surfaces of the resist pattern 4. A pattern 5 is formed, and then using the resist pattern 4 as a mask again, an etching gas that selectively etches the resist and the second metal film and does not etch the first metal is used. By the anisotropic dry etching means used, as shown in FIG. 1 (c), the second metal film pattern 3P is etched while the outer peripheral surface of the resist pattern 4 is being etched back. The second metal film pattern 3P
A forward taper 7A is formed on the side wall surface of.

By doing so, as shown in FIG. 1D, the laminated metal wiring 5L obtained by removing the resist pattern 4 has the first metal film pattern 2P having substantially vertical side wall surfaces. And a second metal film pattern 3P having a forward taper 7A on the side wall surface are laminated, and the upper portion is formed in a mountain shape having the forward taper 7A.

Therefore, as shown in FIG. 1 (e), when the insulating film 6 is formed on the surface of the laminated metal wiring 5L by vapor phase growth, the insulating film 6 has a step of the laminated metal wiring 5L. The corresponding stepped portion 8 is formed by the second metal film pattern 3P.
Of the insulating film 6 in the step portion 8 having a gentle forward taper slope 7B along the forward taper 7A of the side wall surface of the
The generation of cracks is prevented.

Further, in the method of the present invention, when a laminated metal wiring is formed by using Al (including an Al alloy) as the first metal film and Ti as the second metal film, respectively, the upper Ti film is formed. the resisted etching the etching gas is selectively etched in a tapered shape is and Al is not etched SF ₆ and O ₂
By using a mixed gas with Cl, Cl adsorbed on the side wall surface of the Al film pattern when the upper Ti film and the lower Al film are collectively patterned is SF ₆ in the etching gas.
It is replaced by fluorine (F) contained in. Therefore Al
Corrosion of the film pattern is prevented, and the yield of wiring formation and the reliability of wiring are improved.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A metal wiring forming method according to the present invention and a method of manufacturing a semiconductor device using the metal wiring forming method will be described below with reference to FIG. A specific description will be given with reference to process cross-sectional views. Note that the same object is denoted by the same reference numeral throughout the drawings.

See FIG. 2A. According to the method of the present invention, for example, a TFT having a laminated metal gate wiring in which Al of a main conductive layer (including an alloy containing Al as a main component) and Ti of a barrier metal are laminated. In forming the film, first, an Al (including an alloy containing Al as a main component) film 12 having a thickness of about 150 nm, which is a main conductive layer of the wiring, is formed on a glass plate 11 which is an insulating substrate by a sputtering method or the like. Then, a Ti film 13 with a thickness of about 100 nm to be a barrier metal is formed on the Al film 12 by a sputtering method or the like, and then a photolithography method similar to the conventional one is used to correspond to the gate wiring pattern on the Ti film 13. A resist pattern 14 having a pattern shape to be formed is formed.

Referring to FIG. 2B, the first RI is then formed using the resist pattern 14 as a mask.
The Ti film 13 and the Al film 12 are collectively patterned by the E treatment to form a laminated pattern 15 of the Al film pattern 12P and the Ti film pattern 13P whose sidewalls are aligned with the sidewalls of the resist pattern 14 and are substantially vertical. .

The conditions of the first RIE process when the Ti film 13 and the Al film 12 are collectively patterned are as follows. Here, on the exposed surfaces of the resist pattern 14, the Ti film pattern 13P, and the Al pattern 12P, Cl contained in the etching gas is
Is adsorbed in large quantities.

Referring to FIG. 2 (c), a second RIE process using a mixed gas of sulfur hexafluoride (SF ₆ ) and O ₂ as an etching gas in which the resist and Ti are selectively etched and Al is not etched is then performed. By using the resist pattern 14 as an etching mask again,
The film pattern 13P is etched. By this etching, the resist pattern 14 is etched, and the outer peripheral surface of the resist pattern 14 is sequentially receded.
P is sequentially etched from the peripheral portion of the upper surface, and a forward taper 17A is formed on the side wall surface of the Ti film pattern 13P. The etching conditions are as follows, for example.

[0023] Under this condition, the angle of the forward taper 17A is formed around 60 degrees.

In the second RIE process, the Al film pattern 12P and the Ti film pattern are formed by the first RIE process.
Cl adsorbed on the exposed surface of 13P and resist pattern 14, etc.
Is replaced by fluorine ions (F ⁺ ) formed in the plasma of the etching gas and is released into the etching gas, and is discharged and removed together with the etching gas.

Next, as shown in FIG. 2D, the resist pattern 14 is removed by an ashing process using a normal O ₂ plasma or the like, and a rising angle of about 60 degrees is formed on the Al film pattern 12P having substantially vertical sidewall surfaces. A two-layer metal gate wiring 15L is formed by stacking the Ti film pattern 13P having a sloped side wall surface having a forward taper 17A.

The gate wiring 15L is as described above.
Since Cl adsorbed on the surface has been removed by the replacement with F ⁺ , even if it is exposed to the atmosphere, corrosion does not occur rapidly.

2 (e) Next, a glass plate having the above-mentioned two-layer metal gate wiring 15L.
A gate insulating film 16 made of, for example, silicon nitride (Si ₃ N ₄ ) having a thickness of about 400 nm is formed on 11 by a normal CVD method,
Next, a non-doped amorphous silicon (a-Si) film 20 having a thickness of about 10 nm to be a channel layer is formed on the surface on which the gate insulating film 16 is formed by a normal CVD method, and then this a-Si film is formed.
A Si ₃ N ₄ film with a thickness of about 150 nm is formed on 20 by a normal CVD method, and then the upper portion of the gate wiring 15L is covered along the gate wiring 15L by a normal lithography means on the Si ₃ N ₄ film. A resist pattern is formed, the resist pattern is used as a mask, and the Si ₃ N ₄ film is patterned by, for example, wet etching, the resist pattern of the mask is removed, and the gate wiring 15L on the a-Si film 20 to be the channel is formed. Si ₃ N ₄ covering the upper part along the gate wiring 15L
The protection pattern 21 is formed.

Next, referring to FIG. 2 (f), an n ⁺ -type a-Si film having a thickness of about 60 nm to be a contact layer is formed on the substrate which has undergone the above steps by a CVD method,
Next, a thickness is formed on the n ⁺ type a-Si film by a sputtering method or the like.
A Ti film of about 80 nm and an Al film of about 50 nm in thickness are sequentially stacked, and then the n ⁺ type a-Si film is formed on the Si ₃ N ₄ protective pattern 21 by a normal resist process and RIE process. Side and the drain region side and the peripheral part is demarcated and removed, and the source contact layer 22S or the drain contact layer 22D made of the n ⁺ type a-Si film is formed on the channel layer made of the non-doped a-Si film 20. Via the source electrode 23S having a laminated structure of the Ti film and the Al film
And a drain electrode 22D, and a TFT having a two-layer metal gate wiring 15L formed by the metal wiring forming method according to the present invention.
Is completed.

In the above embodiment, the TFT 2
Layer metal gate wiring is Al (including alloy containing Al as the main component)
And Ti, and a Cl-based etching gas was used for the first RIE treatment and a mixed gas of a fluorine compound and oxygen was used for the second RIE treatment. The laminated metal wiring to which the present invention is applied has the above-mentioned constitution. Therefore, the etching gas used for the first and second RIE processes is not limited to the above.

[0030]

As described above, according to the metal wiring forming method of the present invention, since the side wall surface of the wiring can be formed in a sloped shape having a forward taper, the insulating film formed on the metal wiring can be formed. Generation of cracks in the wiring step portion is avoided, and deterioration of the withstand voltage of the insulating film is prevented. Further, according to the metal wiring forming method of the present invention, corrosive gas (for example, Cl) is not adsorbed on the surface of the metal wiring (for example, wiring including an Al film) at the time of completion of patterning. Corrosion is prevented.

Therefore, according to the method of manufacturing a semiconductor device of the present invention using the above-described method for forming a metal wiring, deterioration of withstand voltage due to cracks in the insulating film on the wiring and disconnection due to corrosion of the metal wiring can be prevented. The manufacturing yield and reliability of the semiconductor device having the electrode wiring of the seed metal laminated structure are improved.

[Brief description of drawings]

FIG. 1 is a process sectional view for explaining the principle of a metal wiring forming method according to the present invention.

FIG. 2 is a process sectional view of an embodiment of a method for manufacturing a semiconductor device according to the present invention.

FIG. 3 is a process sectional view of a conventional metal wiring forming method.

FIG. 4 is a schematic cross-sectional view showing a conventional problem

[Explanation of symbols]

 1 Insulating Substrate 2 1st Metal Film 2P 1st Metal Film Pattern 3 2nd Metal Film 3P 2nd Metal Film Pattern 4 Resist Pattern 5 Laminated Metal Film Pattern 5L Laminated Metal Wiring 6 Insulating Film 7A Forward Taper 7B Order Slope with taper

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display area N

Claims (5)

[Claims] 1. When forming a laminated metal wiring in which two kinds of metals are laminated, a step of forming a first metal film (2) on an insulating substrate (1) and the first metal film ( 2) a step of forming a second metal film (2) on which etching selectivity is obtained with respect to the first metal film, and a wiring pattern on the second metal film (2) Forming a resist pattern (4) having a pattern shape, and using the resist pattern (4) as a mask, the second and first metal films (3, 2) are collectively formed by a first anisotropic dry etching means. A step of patterning to form a laminated pattern of first and second metal film patterns (2P, 3P) matching the resist pattern (4); and using the resist pattern (4) as a mask, the resist pattern (4 ) And a second anisotropic having selective etching property with respect to the second metal. A step of etching the side wall surface of the second metal film pattern (3P) into a forward tapered shape (7A) while retreating the outer peripheral surface of the resist pattern (4) by dry etching means. Wiring formation method. 2. A metal film that is etched by a chlorine-based etching gas and is not etched by a fluorine-based etching gas is used for the first metal film, and a chlorine-based and fluorine-based etching gas is used for the second metal film. The method for forming metal wiring according to claim 1, wherein a metal film formed by using the same is used. 3. The metal according to claim 1, wherein the first metal film is an aluminum film or an alloy film containing aluminum as a main component, and the second metal film is a titanium film. Wiring formation method. 4. The etching gas in the first anisotropic dry etching is a mixed gas of boron trichloride and chlorine, and the etching gas in the second anisotropic dry etching is sulfur hexafluoride and oxygen. The method for forming metal wiring according to claim 1, 2 or 3, which comprises the mixed gas of. 5. A method of manufacturing a semiconductor device, comprising a step of forming a metal wiring by using the metal wiring forming method according to claim 1.