JPH05114656A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the generation of voids in a metal wiring during cleaning a photoresist with water and inhibit the generation of via hole contact failure by forming a surface protective film on a metal wiring exposed on the bottom of the via hole prior to the removal of the photoresist after having opened the via hole on a layer insulating film. CONSTITUTION:With a photoresist 7 as a mask, an upper layer insulating film 6, an SOG film 5 and a lower insulating film 4 are consecutively bored on an aluminum film, thereby forming a via hole 10. A reactant based on a plasma processing is adsorbed on the aluminum film 3 exposed on the bottom of the via hole 10 and the end face of each film 4, 5 and 6 exposed on the side of the via hole 10, thereby forming a surface protective film 9 all over the areas of the via hole 10. This construction makes it possible to prevent a direct contact between the aluminum film 3 and moisture by the surface protective film 9 when cleaning the photoresist 7 with water to eliminate and inhibit the generation of voids of the aluminum film 3 by the reaction with the moisture.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device in which a multi-layered metal wiring is laminated on a semiconductor substrate with an interlayer insulating film interposed therebetween, and more particularly to a measure for preventing a defective via hole contact.

[0002]

2. Description of the Related Art With recent miniaturization and high density of semiconductor devices, manufacturing technology for obtaining stable multi-layer wiring is required to be more sophisticated. The step of forming a hole (so-called via hole) for connecting the metal wiring is one of the most difficult steps.

Now, a conventional via hole forming process of a semiconductor device will be described with reference to FIGS. 2 (a) to 2 (c).

First, as shown in FIG. 2A, the insulating film 2 is formed on the semiconductor substrate 1 prior to the formation of the via hole.
And an aluminum film 3 (metal wiring) connected to a device such as a transistor on the semiconductor substrate 1 through a contact hole (not shown) is provided thereon. Next, after forming the lower insulating film 4 thereon, the SOG film 5 is formed by applying a fluid silica-based compound to flatten the unevenness. Then, in order to form the via hole 10 in each of the films 4, 5, and 6, the photoresist 7 is patterned by a normal lithography technique so that only the region corresponding to the via hole 10 is opened.

Next, as shown in FIG. 2B, the photoresist 7 is used as a mask and dry etching is performed.
The upper insulating film 6, the SOG film 5, and the lower insulating film 4 are sequentially opened toward the aluminum film 3 to form a via hole 10.

Further, as shown in FIG. 2C, the unnecessary photoresist 7 is removed by ashing, and finally, the photoresist 7 is completely removed by washing with water.

[0007]

However, in the above conventional manufacturing process, as shown in FIG.
At the time of washing with water to remove the photoresist 7, a void 8 may be generated in the aluminum film 3 exposed at the bottom of the via hole 10 due to a reaction with moisture, and an aluminum film as an upper metal wiring (not shown) may be formed by a sputtering technique. Even if an attempt was made to connect the wires, there was a fear that good contact could not be obtained.

A flattening SOG is provided between the insulating films 4 and 6.
When the film 5 is provided, the end surface of the flattening SOG film 5 is exposed on the side wall of the via hole 10. However, since the SOG film 5 is formed by coating a fluid silica-based compound, gas is not contained inside. If the residual gas is left and is released from the SOG film 5 when the upper metal wiring is sputtered or in the subsequent step, the via hole contact may be adversely affected.

The present invention has been made in view of the above problems, and its purpose is to prevent generation of voids in the metal wiring exposed at the bottom of the via hole and degassing from the SOG film exposed at the sidewall of the via hole. An object of the present invention is to provide a method for manufacturing a semiconductor device, which can suppress defective contact caused by the semiconductor device.

[0010]

In order to achieve the above object, a solution of the present invention is to form a surface protective film on an exposed portion in a via hole in a manufacturing process of a semiconductor device.

Specifically, the means taken by the invention of claim 1 is as follows.
The present invention is directed to a method for manufacturing a semiconductor device in which an upper metal wiring is laminated on a metal wiring provided on a semiconductor substrate via an interlayer insulating film.

Then, as a method of manufacturing a semiconductor device, a step of etching the interlayer insulating film using a photoresist as a mask to open a hole for connecting an upper metal wiring to the metal wiring, and the photoresist are used. Before the removal, the method includes a step of forming a surface protective film that covers the surface of the metal wiring exposed at the bottom of the hole by the etching step.

According to a second aspect of the present invention, the means taken is that an interlayer insulating film and an SOG are formed on a metal wiring provided on a semiconductor substrate.
The present invention is directed to a method for manufacturing a semiconductor device in which an upper metal wiring is laminated via a planarizing coating film such as a film.

Then, as a method of manufacturing a semiconductor device, the interlayer insulating film and the flattening coating film are etched by using a photoresist as a mask, and a hole for connecting the upper metal wiring is opened toward the metal wiring. And a step of forming a surface protective film covering the surface of the metal wiring exposed at the bottom of the hole and the end surface of the flattening coating film exposed at the side wall of the hole by the etching step before removing the photoresist. And a step of removing only the hole bottom portion of the surface protection film after removing the photoresist and before stacking the upper metal wiring on the interlayer insulating film.

[0015]

With the above method, in the invention of claim 1, the surface protective film is formed on the metal wiring exposed at the bottom of the via hole after the formation of the via hole. Therefore, when removing the photoresist by rinsing with water thereafter, The direct contact between the wiring and moisture is prevented, and the generation of voids in the metal wiring is prevented. Therefore, the defective contact of the via hole at the time of forming the upper metal wiring can be reduced.

According to the second aspect of the invention, when a coating film such as an SOG film is provided in addition to the interlayer insulating film, the surface protective film is formed on the bottom of the via hole and the sidewall of the via hole after the via hole is formed. Therefore, when the photoresist is washed with water, voids are prevented from being generated in the metal wiring due to the same effect as that of the first aspect of the invention. Further, after the photoresist is removed and before the upper layer metal wiring is laminated, only the bottom portion of the via hole of the surface protective film is removed, so that the upper layer metal wiring is smoothly laminated and the sidewall of the via hole side wall portion is also removed. Outgassing from the coating film is prevented, and the occurrence of defective via-hole contact is suppressed.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIGS. 1A to 1C show a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps. First, as shown in FIG. 1A, prior to formation of a via hole. An insulating film 2 is formed on the semiconductor substrate 1 made of silicon.
Are formed. Although not shown, a transistor and its electrode portion are formed on the semiconductor substrate 1, and the insulating film 2 electrically insulates the semiconductor substrate portion and the metal wiring. Although not shown, an aluminum film 3 which is a metal wiring connected to the semiconductor substrate 1 through a contact hole is provided on the insulating film 2, and silicon oxide or the like is further formed on the aluminum film 3 by a CVD method or the like. The lower insulating film 4 laminated by the above, a planarizing SOG film 5 formed by applying fluid silica to planarize the irregularities generated in the aluminum film 3, and CV of silicon oxide or the like thereon.
An upper insulating film 6 formed by stacking by the D method or the like is provided. Here, the upper insulating film 6 and the lower insulating film 4 are the inter-layer insulating films in the present invention.

The metal wiring provided on the semiconductor substrate in the present invention is not limited to the one directly connected to the transistor or the like of the semiconductor substrate 1 as in the present embodiment, but a large number of metal wirings and interlayer insulating films. Including metal wiring stacked on top of. That is, it relates to formation of a via hole between each wiring in the multilayer metal wiring.

First, as shown in FIG. 1A, a photoresist 7 having an opening corresponding to the position and size of the via hole is patterned on the upper insulating film 6 by a normal lithography technique. .

Next, as shown in FIG. 1 (b), the photoresist 7 is used as a mask and dry etching is performed.
Towards the aluminum film 3, the upper insulating film 6, SOG
The film 5 and the lower insulating film 4 are sequentially opened to form the aluminum film 3
A via hole 10 is formed to connect the metal wiring (not shown) to the upper layer. Then, by using CF ₄ gas or the like, the reactants by the plasma treatment are adsorbed to the end faces of the aluminum film 3 exposed at the bottom of the via hole 10 and the respective films 4, 5, 6 exposed at the sidewalls of the via hole 10 to form a via hole. The surface protective film 9 is formed over the entire area 10.

Thereafter, as shown in FIG. 1C, the photoresist 7 is removed, and the process proceeds to the step of forming the next upper metal wiring. Prior to the sputtering vapor deposition for forming the upper metal wiring, By anisotropic sputter etching, only the bottom portion of the via hole 10 of the surface protective film 9 is removed.

In the above embodiment, after the via hole 10 is opened, the surface protective film 9 is formed on the aluminum film 3 exposed at the bottom of the via hole 10 as shown in FIG. 1B. After the via hole 10 is opened, the surface protection film 9 prevents direct contact between the aluminum film 3 and moisture during washing with water to remove the photoresist 7, and a void is generated in the aluminum film 3 due to a reaction with moisture. Is blocked. Therefore, when the upper metal wiring is connected to the aluminum film 3, it is possible to suppress the occurrence of defective via hole contact.

In particular, as in the above embodiment, the surface protective film 9 is exposed to the side wall of the via hole 10 for flattening S.
In a case where it is provided over the end surface of the OG film 5 and only the bottom portion of the via hole 10 of the surface protection film 9 is removed after the photoresist 7 is removed, the SOG film 9 from the SOG film 9 in the subsequent lamination of the upper metal wiring is Outgassing is prevented, and the effect of suppressing poor via-hole contact is further improved.

Although the planarizing SOG film 5 is interposed between the upper insulating film 6 and the lower insulating film 4 in the above embodiment, the SOG film 5 is not necessarily provided in the invention of claim 1. It is not necessary to provide the metal wiring of the next layer immediately on the lower insulating film 4, for example. However,
Generally, when forming a multi-layered metal wiring, a flattening coating film such as an SOG film is often formed in order to avoid the accumulation of irregularities. In such a case, the coating film is applied. It is possible to suppress the failure of the bayer hole contact due to the degassing from the gas, and therefore, the remarkable effect is exhibited.

[0026]

As described above, according to the first aspect of the present invention, the semiconductor is such that the upper metal wiring is laminated on the metal wiring provided on the semiconductor substrate with the interlayer insulating film interposed therebetween. As a method for manufacturing the device, after opening the via hole in the interlayer insulating film and before removing the photoresist, a surface protective film was formed on the metal wiring exposed at the bottom of the via hole. It is possible to prevent the occurrence of voids in the metal wiring, and thus it is possible to suppress the occurrence of defective via-hole contacts.

According to the second aspect of the present invention, the upper metal wiring is laminated on the metal wiring provided on the semiconductor substrate via the interlayer insulating film and the flattening coating film such as SOG. As a method of manufacturing a semiconductor device, an interlayer insulating film and S
After opening the via hole in the OG film and before removing the photoresist, the metal wiring exposed at the bottom of the via hole and the SOG film exposed at the sidewall of the via hole are covered with the surface protective film, while the metal of the upper layer after the photoresist is removed. Since only the bottom part of the via hole of the surface protective film was removed before the wiring was laminated, the occurrence of voids in the metal wiring when the photoresist was washed with water and the SOG film from the SOG film when laminating the upper metal wiring were stacked. Generation of degassing can be prevented, and therefore, the effect of suppressing poor contact of the via hole can be remarkably exhibited.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment in the order of steps.

FIG. 2 is a cross-sectional view showing a method of manufacturing a conventional semiconductor device in the order of steps.

[Explanation of symbols]

 1 semiconductor substrate 3 aluminum film (metal wiring) 4 lower layer insulating film (interlayer insulating film) 5 SOG film (coating film) 6 upper layer insulating film (interlayer insulating film) 7 photoresist 9 surface protection film

Claims (2)

[Claims] 1. A method of manufacturing a semiconductor device in which an upper metal wiring is laminated on a metal wiring provided on a semiconductor substrate via an interlayer insulating film, wherein the photoresist is used as a mask to form the interlayer. A step of etching the insulating film to open a hole for connecting the upper metal wiring toward the metal wiring; and a surface of the metal wiring exposed at the bottom of the hole by the etching step before removing the photoresist. And a step of forming a surface protection film covering the film. 2. A method of manufacturing a semiconductor device, wherein an upper metal wiring is laminated on a metal wiring provided on a semiconductor substrate with an interlayer insulating film and a flattening coating film such as an SOG film interposed therebetween. The step of etching the interlayer insulating film and the flattening coating film using the photoresist as a mask to open a hole for connecting the upper metal wiring to the metal wiring, and removing the photoresist Before the step of forming a surface protective film covering the surface of the metal wiring exposed at the bottom of the hole and the end surface of the flattening coating film exposed at the side wall of the hole by the etching step, and after removing the photoresist A step of removing only a hole bottom portion of the surface protection film before stacking an upper metal wiring on the interlayer insulating film.