JPS61287245A - Multilayer interconnection method - Google Patents

Abstract

PURPOSE:To obtain flat multilayer interconnection by forming a photoresist spacer near a wiring pattern, rotatably coating a photoresist, etching back it to uniformly cut a raised portion with good controllability. CONSTITUTION:A PSG 30 is coated approx. 1.5mum thick on a wiring layer 20 of approx. 1mum thick on a GaAs substrate 10. A resist spacer 80 of approx. 7mum thick is formed by photocomposing technique by avoiding on the layer 20, and a projection of an interval l 2mum is formed on the entire surface of a wafer. Then, a photoresist 85 is rotatably coated, and uniformly buried. Then, a photoresist and a PSG are etched at 900 at substantially equal speed with mixture gas of CF4+O2, and projections 35 of the PSG are simultaneously exposed. A light emitting spectrum of SiO2 is altered at the moment. Thereafter, when the PSG is etched back at approx. 800nm only for the prescribed time and the resist is removed, a step B is reduced by approx. 200nm, and a step C is restricted to the value of 200nm. Thereafter, a window 60 is opened to provide he second wiring 70. According to this construction, multilayer interconnections are formed efficiently with good yield.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a multilayer wiring method used in semiconductor devices, integrated circuits, and the like.

[Background of the invention]

Multilayer interconnects used in semiconductor integrated circuits are created by flattening steep steps caused by metal interconnects and the like. This means that the thickness of the first wiring metal layer, such as At or Au, is approximately 1 μm.
This is because, if an interlayer insulating film is attached and a second wiring metal is formed while leaving these unevenness, it is undesirable because it causes wire breakage and machining residue. Conventionally, this problem has been solved by processing the cross section of the first wiring metal layer into a tapered shape, or by flattening the steep first wiring metal layer during processing of the insulating film. However, tapered processing is not preferable for miniaturization.

Therefore, it is generally called the etch-back method, as can be seen in the document "Planarized Multilayer Interconnection of GaAS LSI" by Asai, Jobu, and Higashisaka in 1983 National Conference of the Institute of Electronics and Communication Engineers, 2-225 (1983). Multilayer wiring is performed using planarization technology. In the conventional method, as shown in the manufacturing process diagram of FIG. 1, an interlayer insulating film 3 is deposited on the first layer wiring 2 formed on the semiconductor substrate 1, and then a photoresist 4 is applied to fill the protrusions ( a). After this, the photoresist 4 is scraped, and the exposed interlayer insulating film 5 is further scraped to flatten the protrusion (b), and then the contact hole 6 is opened to form the second layer wiring 7 (C). is formed. This type of etchback flattening is
Rotating photoresist coating has pattern dependence,
There is a drawback that the thickness of the interlayer insulating film after planarization varies depending on the pattern size. In other words, it is dense, thick on small patterns, and isolated.

The large pattern was processed thinly. As a result, in extreme cases, a short circuit may occur between the first layer and the second layer. Further, large variations in the thickness of the interlayer insulating film cause uneven etching when forming contact holes, which also causes poor conductivity in the through holes. Furthermore, since the exposed area of the interlayer insulating film increases with the etching time (for example, the area A in FIG. 1), it is difficult to determine the end point of etching. FIG. 2 is a schematic diagram of the surface state of the sample 100 that has been subjected to etch-back for planarization, viewed from the surface.

It is well known that the rotational application of photoresist causes uneven flattening of relatively large-area patterns 200 such as bonding pads and thin wiring patterns 201. The periphery of the fine pattern 201 and the dog turn 200 tends to be thick, and the flat area tends to be thin. For this reason, when you etch back, it becomes AI.

The surface of PSG300 appears in the part corresponding to A2, and the part corresponding to B
Portions corresponding to B2 and B3 are covered with photoresist 400. As the etching progresses in this manner, the area ratio of A and B changes, resulting in the drawback that it is difficult to determine the end point as described above.

[Purpose of the invention]

An object of the present invention is to provide a method with good controllability and good uniformity in planarizing multilayer wiring.

[Summary of the invention]

The present invention is based on the etch-back planarization method, in which the wiring pattern to be planarized is uniformly filled with photoresist regardless of its size or shape, and the protrusions are uniformly shaved off by etch-back.

In order to uniformly fill in the photoresist regardless of the wiring pattern size, the present invention is characterized in that a photoresist spacer is provided near the wiring pattern, and then the photoresist is spin-coated.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIG. Third
The figure describes the process of two-layer wiring in the GaAsLSI process. First layer wiring layer 2 on substrate crystal 10
0 was formed with a thickness of about 1 μm. A PSG film 30 with a thickness of 1.6 μm was deposited on this to form an interlayer insulating film (a). Next, the first layer wiring layer was coated with a thickness of 2 μm and a pattern that had been reversed was used to create a thickness of ~1 μm.
The photoresist spacer 80 was formed using photolithography technology. As a result, a gap t (middle 2
A concave portion corresponding to .mu.m) was made. For this purpose, a normal positive resist (for example, OFP 几-800, manufactured by Tokyo Ohka Steel) was used. After that, the photoresist spacer 80 is cured by irradiation with UV light (wavelength of about 250 nm), and then
Photoresist 85 was spin-coated to a thickness of Q nm (
b). As a result, the raised portions 20 are formed over the entire surface of the wafer.
were evenly filled with photoresist. After this, photoresist! : As the PSG is etched from the surface under dry etching conditions (using a mixed gas of CFa and Ol) at almost the same speed (900), the convex portions 35 of the PSG eventually become etched.
became exposed all at once. At this moment, a change appeared in the emission spectrum involving 5ift. After this, I etched it back for the time determined based on the etching rate.

Here, P2O was etched back to a thickness of about 800 nm (C). After this, the photoresist was removed. Approximately 1μ
As a result, the step B, which was m, was reduced to about 200 nm,
Moreover, the height difference C was suppressed to a value of 2QQnm over the entire wafer surface. In the etch-back process, etching may be performed until the photoresist used for the spacer is completely removed. In this case, the end point can be detected by monitoring the emission spectrum of the photoresist. Subsequently, the contact hole 60 was opened and the second layer wiring 70 was processed in the same manner as in a normal process.

FIG. 4 shows the embodiment of the invention described in FIG. 3 from the top of the sample after the etch bank. Wiring patterns 200 and 2 are formed by photoresist spacers 400 and 401.
01 is uniformly buried, and after etching back, the photoresist remains at 400, 401°, 450, 451, and the PSG is exposed at the convex portions A1 and A2. This allowed etching back without pattern dependence.

Other embodiments of the invention will be described below. An interlayer insulating film is deposited on the first wiring layer having a thickness of about 1 μm to a thickness of 800 nm, which is the same thickness as the first wiring layer or less. Next, after forming a photoresist spacer pattern, the photoresist is planarized. This process procedure is the same as the method described in FIG.

Next, approximately 8001 m of PSG is removed by etch-back to expose the surface of the first wiring layer. After this, the photoresist is removed and an interlayer insulating film is deposited again to a thickness of ~600 nm. As a result, the entire surface of the wafer is approximately 200 nm
It was flattened with unevenness of less than m.

The subsequent second layer wiring is the same as before.

The embodiments of the present invention have been described above, but in order to have a sufficient effect on planarization and embedding, the gap t (see t in Figures 3 and 4) formed between the photoresist spacer pattern and the first wiring layer must be It's better to keep it short. According to the experimental results, ~5μ
m or less is preferable, and the minimum value is a value (~0.5 μm) determined by the alignment accuracy of photolithography.

In the above embodiments, a spacer pattern of photoresist and a buried photoresist layer have been used to achieve uniform planarization, but when the etching rate is increased, the surface of the photoresist may become rough due to a rise in temperature. Needless to say, polyimide resin, silicone resin, etc. can be used instead of the above-mentioned photoresist material.

〔Effect of the invention〕

According to the present invention, implant planarization can be performed uniformly within the wafer surface, thereby solving the disadvantages of conventional etching back, such as non-uniformity and uncertainty in end point detection. . Therefore, it was possible to significantly improve the working efficiency and the yield rate. Furthermore, the process is extremely simple, requiring only one additional photoresist process for the spacer pattern.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of the device for the process steps of the conventional etch-back planarization method, FIG. 2 is a top view of the device, and FIG. 3 is a cross-sectional view of the device for the process steps of the planarization method according to the present invention. FIG. 4 is a top view of this element. 1.10... Semiconductor substrate crystal, 2.20... First layer wiring pattern, 3.30... Interlayer insulating film layer, 80...
・Spacer pattern, 85... Photoresist for embedding, 7.70... First layer wiring pattern, 6.60...
contact hole. Figure 2, Figure i

Claims (3)

[Claims] 1. In a multilayer wiring method for forming at least two or more wiring metal layers and at least one or more interlayer insulating layer on a semiconductor substrate crystal, a step of depositing an interlayer insulating layer on a first wiring metal layer, and a photoresist. A step of providing a spacer pattern on the first wiring metal layer, a step of applying a photoresist as an interlayer insulating layer on the first wiring metal layer and the spacer pattern, and a step of applying a photoresist as an interlayer insulating layer on the first wiring metal layer and the spacer pattern; A multilayer wiring method comprising the steps of etching an insulating layer, providing a contact hole in the interlayer insulating film, and providing a second wiring metal layer. 2. The multilayer wiring method according to claim 1, further comprising the step of removing the photoresist layer after the etching step. 3. The multilayer wiring method according to claim 1, further comprising the step of forming an interlayer insulating layer again after the etching step.