JPH06295908A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain simply a buried film having high flatness as a whole without proceeding to excessive polishing as the flatness is damaged by a method wherein after the buried film is deposited on a semiconductor substrate having projected parts and recessed parts, a stopper film for preventing the excessive polishing from being generated is formed on the surface of the wide recessed part. CONSTITUTION:A first stopper layer 201 is formed on the upper surfaces of projected parts 103 of a semiconductor substrate 101. Then, a buried film 102, with which recessed parts 104 are filled, is evenly formed extending over the whole surfaces of the recessed and projected parts of the surface of the substrate 101. In the recessed part 104 having the comparatively large area of a width, a second stopper layer 301 is formed on the surface of the recessed part of the film 102. Then, the film 102 is polished two-dimensionally until the surface of the layer 201 is exposed by a mechanical polishing. Subsequently, the layers 201 and 301 are removed and the surfaces of the projected parts 103 of the substrate 101 are exposed. In such a way, the surface of the substrate 101 is flattened.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for filling a recessed portion of a semiconductor substrate surface having an uneven surface with a filling material to flatten the surface.

[0002]

2. Description of the Related Art When manufacturing a highly integrated semiconductor device such as a VLSI, it may be necessary to reduce a step formed on the surface of a semiconductor substrate. For example, in the multilayer wiring technique, if an interlayer insulating film is deposited on the first-layer metal wiring and the second-layer metal wiring is formed on the first-layer metal wiring, a step may occur in the second-layer metal wiring, resulting in cutting. There is a problem that reliability is deteriorated due to increase in resistance. Therefore, the interlayer insulating film deposited between the metal wirings is flattened.

Further, when a trench is formed on the surface of a semiconductor substrate in a DRAM or the like and is used as an element isolation or a capacitor, it is necessary to similarly fill the recessed groove.

A conventional example of a technique for flattening the surface of a semiconductor substrate by filling a recess formed on the surface of the semiconductor substrate will be described below.

FIG. 39 illustrates a conventional technique for such flattening. The convex portion 1 is formed on the surface of the semiconductor substrate 101.
03 and a recess 104 are formed. Therefore, a burying material is deposited on the entire surface of the semiconductor substrate 101 to form a burying film 102 and bury the recess 104. After that, by planarly polishing from the upper part to the surface of the convex portion 103 as shown by the dotted line in the figure, only the concave portion 104 can be filled with the burying film 102 and the surface of the semiconductor substrate can be planarized. However, in such a method, a large recess or the like causes a large depression, and the flatness of the surface obtained as a whole is not necessarily good.

Another conventional example in which such a point is solved will be described with reference to FIGS. In each of these drawings, the same reference numerals are given to the portions corresponding to FIG. First, a stopper layer 201 is formed corresponding to the convex portion 103 on the surface of the semiconductor substrate 101, the polishing rate of which is lower than that of mechanical polishing performed later (FIG. 40).

Next, a burying material is deposited on the entire surface of the semiconductor substrate 101 to form a burying film 102 (FIG. 41).
In this state, the buried film 102 is also a recess 105 in the recess 104 having a relatively large area. A flattening block (resist layer) 202 is selectively formed in the recess 105 of the buried film 102 (FIG. 42). Next, a flattening material having high fluidity is applied to the uneven portion and dried to form a flattening film 203 (FIG. 43). Subsequently, the flattening film 203, the flattening block 202, and the embedded film 102 are etched back to the vicinity of the stopper layer 201 by reactive ion etching (RIE) which is anisotropic etching (FIG. 4).
4). Finally, the unevenness 204 on the substrate surface caused by the difference in RIE etching rate between the materials is removed by mechanical polishing. At that time, the end point is controlled by the stopper layer 201 (FIG. 45).

The mechanical polishing used at this time is usually called a polishing method (lapping method),
A flat plate is pressed and rotated on the surface of a semiconductor substrate, and at this time, a material suitable for cutting the substrate surface material is added between the flat plate and the substrate surface to scrape the material on the substrate surface in one plane. . This abrasive is generally composed of spherical particles of a silicon oxide film having a uniform particle size of about several tenths of a micron to several microns, and a liquid containing each of these particles separated and uniformly without gelation. Become.

Then, the stopper layer 201 is removed later to complete a structure in which the recess 104 of the semiconductor substrate is filled with the buried film 102 having a flat plane with the surface layer of the protrusion 103 of the semiconductor substrate 101. (FIG. 46).

[0010]

However, in the above method, the planarization block 202, the two planarization layers 102 and 203 must be formed, and the number of manufacturing steps increases. Further, from the viewpoint of improving the flatness, the planarization block and the planarization layer must have a uniform RIE etching rate with respect to the filling material. However, it is practically extremely difficult to select the material and the conditions for keeping the RIE etching rate constant for the three layers in this manner, and mechanical polishing is added to the last remaining unevenness to realize planarization. is doing. In other words, the planarization step requires two steps of RIE and mechanical polishing, which also increases the number of manufacturing steps.

It is possible to consider a method in which the planarization block and the planarization layer are formed and then the surfaces are collectively planarized only by mechanical polishing. In this method, the polishing rate in the mechanical polishing is considered from the viewpoint of manufacturing efficiency. Must be increased.
Moreover, in-plane variation of polishing increases in proportion to the polishing rate, and it becomes difficult to control mechanical polishing by the stopper layer. Also in this case, similar to RIE, it is necessary to make the mechanical polishing rate uniform for the three layers from the viewpoint of flatness, but this is more difficult than in RIE. If mechanical polishing is performed without forming the flattening block 202 or the flattening layer 203 in order to shorten the polishing time, the polishing rate of the concave portion is lower than that of the convex portion, but the area is smaller. In the central portion of the wide concave region, the polishing rates of the both approaches, and the filling material in the concave portion is polished and removed, and as a result, flattening cannot be realized.

Therefore, an object of the present invention is to provide a method for easily realizing a highly accurate flattening structure.

[0013]

According to a method of manufacturing a semiconductor device of the present invention, a step of forming a first stopper layer on the surface of the convex portion of a semiconductor substrate having a concave portion and a convex portion on the surface, Forming a buried film for filling the recess of the substrate surface over the entire surface of the semiconductor substrate; selectively forming a second stopper layer on the surface of the buried film on the recess region; Planarly removing the buried film until the surface of the first stopper layer is exposed by mechanical polishing.

It is preferable that the film thickness of the second stopper layer is thinner than the step of the unevenness on the surface of the semiconductor substrate.

The first and second stopper layers are silicon nitride films or polysilicon films, or are made of a group consisting of a carbon film, a tungsten film, a titanium film or a compound of them and other substances having a polishing property. It should be selected.

Only when two adjacent convex portions are at a distance larger than twice the thickness of the embedded film plus the minimum processing dimension, on the embedded film embedded in the concave portion between both convex portions. It is preferable that the second stopper layer be formed.

It is preferable that the thickness of the buried film is selected within a range of 80 to 120% of the step difference of the unevenness on the semiconductor substrate.

The convex portion is the initial surface of the semiconductor substrate,
When the concave portion is a groove portion formed in the semiconductor substrate, the convex portion is a first metal wiring layer laminated on the semiconductor substrate via a silicon oxide film, and the concave portion is an initial surface of the semiconductor substrate. The invention is provided in each case.

After the first stopper layer and the second stopper layer are removed, a step of depositing a silicon oxide film to be an interlayer insulating film and a second metal wiring layer are formed on the silicon oxide film. And a process.

Further, according to the present invention, a step of forming an embedding film for embedding the recess on the surface of a semiconductor substrate having a recess and a protrusion on the surface, and a step of forming a buried film on the surface of the recess on the recess region. The method further comprises the step of selectively forming the first stopper layer and the step of planarly removing the embedded film by mechanical polishing until the surface of the convex portion is exposed.

Only when the two adjacent protrusions are at a distance larger than twice the thickness of the embedding film plus the minimum processing dimension, on the embedding film embedded in the recesses between the both protrusions. It is preferable that the second stopper layer is formed on the substrate.

Further, according to the present invention, a step of forming a first polysilicon layer as a first stopper layer on the surface of the convex portion of the semiconductor substrate having a concave portion and a convex portion on the surface, and the semiconductor substrate. A step of forming a buried film for filling the recess on the substrate surface over the entire surface of the substrate, and a second stopper layer on the surface of the buried film on the recess region.
And a step of selectively forming the polysilicon layer by anisotropic etching, and a step of removing the buried film by mechanical polishing until the surface of the first stopper layer is exposed. .

In the step of selectively forming the second polysilicon layer, a silicon oxide film is further formed on the deposited second polysilicon layer so as to have a thickness equal to or larger than a step existing in the second polysilicon layer. After that, it is preferable to pattern this together with the second polysilicon layer.

Only when the two adjacent protrusions are at a distance larger than twice the thickness of the embedding film plus the minimum processing dimension, on the embedding film embedded in the recess between both protrusions. It is preferable that the second stopper layer be formed.

[0025]

After the buried film is deposited on the semiconductor substrate having the convex portion and the concave portion, a stopper film for preventing excessive polishing and etching is formed in the wide concave portion. Excessive polishing that impairs flatness does not proceed in the step of performing etch back, and a buried film with high flatness as a whole can be easily obtained. The relationship between the concave portion and the convex portion is applied to the cell structure of the RAM or the multilayer wiring structure. However, when the distance between the adjacent convex portions is equal to or smaller than a predetermined dimension, the stopper film is not formed there. The mask can be simplified.

By providing the stopper layer also on the convex portion on the semiconductor substrate, it becomes easy to control the end point of polishing or etching.

Further, due to the combination of the materials of the first and second stopper layers (the selectivity of the polishing rate with the embedding material in the mechanical polishing and the optimization of the film thickness), it is required in the conventional planarization process. Further, the steps of forming a block resist, a planarizing resist, RIE etchback before polishing, etc. can be omitted, and a planarized structure can be realized more easily and more accurately than in the prior art.

[0028]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, the basic manufacturing process of the present invention will be described with reference to FIGS. In each figure, parts corresponding to those of the conventional example are designated by the same reference numerals. In FIG. 1, a first stopper layer 201 is formed on the upper surface of the convex portion 103 of the semiconductor substrate 101 (FIG. 1). This first stopper layer 20
1 is formed of a material having a polishing rate smaller than that of the embedding material so as to serve as a polishing stopper when polishing the embedding material laminated on the surface of the convex portion 103 on the surface of the substrate 101 in the subsequent polishing step. To be done. Buried film 102 filling the recess 104
Are uniformly formed over the entire surface of the uneven portion on the surface of the semiconductor substrate 101 (FIG. 2).

In the recess 104 having a relatively large area, a second stopper layer 301 is formed on the surface of the recess 105 of the buried film 102 (FIG. 3). This second stopper layer 30
Reference numeral 1 also serves as a stopper when polishing the embedded film 102 formed on the surface of the convex portion 103 on the surface of the substrate 101 in the subsequent polishing process. The material of the stopper layer 301 is selected so that the polishing rate is lower than that of the material of the embedded film 102.

Next, the embedded film 10 is planarly planarized by mechanical polishing until the surface of the first stopper layer 201 is exposed.
2 is polished (FIG. 4). Then, the first stopper layer 201
Then, the second stopper layer 301 is removed to expose the surface of the convex portion 103 of the semiconductor substrate 101. Thus, the surface of the semiconductor substrate 101 is flattened (FIG. 5).

In the above manufacturing process, for example, the buried film 1
Let 02 be an insulating film, the recess 104 filled with the insulating film by the above method be an element isolation region, and the substrate surface of the protrusion 103 be an element region.
Elements can be formed on this element region 103 separated by 02 by a known method.

In the above method, there is a difference in the polishing rate between the material of the second stopper layer 301 and the material of the buried film 102 by mechanical polishing, and at least the second stopper material 3 is used.
No. 01 has a lower polishing rate, and the thickness of the second stopper layer 301 is smaller than the unevenness of the surface of the substrate 101 in order to secure the polishing rate. Further, the embedded film 102 has a flatness. Is close to the step of the unevenness on the surface of the semiconductor substrate 101, and has a large height difference between the surface of the convex portion 103 and the surface of the embedding material 102 embedded in the concave portion 104 having a width wider than twice the embedding film 102. No difference is required. In addition, it is desirable that the material of the first stopper layer 201 ideally has a mechanical polishing rate lower than that of the material of the buried film 102, like the second stopper material 301. This is not the case when the stopper effect of the material of the layer 301 is large.

A specific example of the manufacturing process will be described with reference to the drawings. 6 to 15 are sectional views for explaining the first embodiment of the present invention by process, and particularly show the case of application to element isolation.

First, the p-type (100) has a specific resistance of 1 to 2 Ω.
The silicon semiconductor substrate 401 having a thickness of 10 cm is oxidized in an oxidizing atmosphere at 1000 ° C. to form a silicon oxide film 402 having a thickness of 15 nm as a protective film on the surface thereof. Further, a first silicon nitride film 403 having a film thickness of 100 nm is deposited as a first stopper material on the silicon oxide film 402 by the CVD method (chemical vapor deposition method) (FIG. 6).

Next, a photoresist is applied on the silicon nitride film 403, and a resist pattern 404 obtained by photolithography of the photoresist is used as a mask to form a first silicon nitride film 403 and a first silicon nitride film 403 on a region where an element isolation portion is to be formed. The silicon oxide film 402 thereunder is selectively removed to expose the surface of the semiconductor substrate 401. An RIE method (reactive ion etching), which is anisotropic etching, is used for this removal (FIG. 7).

Next, the semiconductor substrate 4 is formed by using the resist pattern 404 and the silicon nitride film 403 thereunder as a mask.
01 is further etched by the RIE method under another condition to form a groove 405 having a depth of about 0.5 μm on the surface of the semiconductor substrate 401 (FIG. 8).

Subsequently, the resist pattern 40 is no longer needed
4 is removed to expose the groove 405 of the semiconductor substrate 401.
Perform a general decontamination process on the inner surface. After that, the surface 401 of the substrate is oxidized in an oxidizing atmosphere at 900 ° C. to form a silicon oxide film 406 having a thickness of 10 nm as an insulating film on the surface. A convex portion 410 and a concave portion 405 are formed on the substrate surface 401 (FIG. 9).

Next, a silicon oxide film is deposited as a burying material by a low pressure CVD method to form a silicon oxide film layer 407 having a film thickness of 600 nm and the trench 405 is buried. at this point,
Inside the groove 405, a silicon oxide film 406 as an insulating film and C
Completely filled with VD silicon oxide film 407 (see FIG. 1).
0).

Next, a second silicon nitride film 408 as a second stopper is formed with a thickness of 150 nm by the CVD method (FIG. 11).

Next, a resist pattern 40 is formed by applying a resist on the entire surface and patterning the resist by photolithography.
Using the mask 9 as a mask, the second silicon nitride film 408 on and around the element region 410 (substrate surface convex portion) is selectively removed (FIG. 12).

Next, the unnecessary resist pattern 40
9 is removed, and the protruding CVD silicon oxide film 407 is polished and removed by polishing until the first silicon nitride film 403 is uniformly exposed from above. The polishing conditions at this time are that the CVD silicon oxide film 407 has a polishing rate of 150 nm / min, and the silicon nitride films 403 and
8 is set to 30 nm / min, and the polishing time is CV
20% over-polishing amount for D silicon oxide film 407
5 minutes so that

Therefore, since the second silicon nitride film 408 exposed from the beginning of polishing is polished at the designed polishing speed of the designed silicon nitride film 408 particularly at a position apart from the step portion, almost the entire film is polished. The thickness is cut. However, in the vicinity of the step portion, the pressure applied to the second silicon nitride film 408 at the time of polishing is weakened due to the influence of the convex portion 410, and the polishing speed is reduced, so that the entire film thickness is not removed and some remains. (FIG. 13).

Next, as shown in FIG. 14, the exposed first silicon nitride film 403 and the remaining second silicon nitride film 408 can be removed. By performing such removal, the gettering effect can be improved.

The silicon oxide film 402 on the element region 410 (convex portion) of the semiconductor substrate 401 is removed by etching with a hydrofluoric acid solution (ammonium fluoride solution) for 15 seconds to a film thickness of 25 nm to remove the surface of the semiconductor substrate 401. Expose it. After that, by using a known method, a MOS gate structure, a source / drain diffusion layer, an inter-wiring insulating layer, a lead electrode wiring, etc. are formed on the exposed surface of the substrate of the element region 410 to form a necessary element (see FIG. 15).

In this way, the method of the present invention enables a simple and simple embedding of the embedding material in the embedding element isolation region.
In order to prevent the polishing speed of the protruding embedding material 407 from being impaired, the surface height of the second stopper material has a polishing loss relative to the surface height of the protruding portion of the embedding material 407. It is set low so that it becomes small. Further, it is desirable to select a material having a very low polishing rate as the second stopper material and reduce its film thickness. Therefore, as an application of the embodiment, a material having abrasion resistance and a slower polishing rate, for example, a carbon film having a high hardness and a low mechanical polishing rate, a refractory metal such as a tungsten (W) film or a titanium (Ti) film is used. By selecting a film or a compound film thereof as the second stopper material, a better polished flat surface can be realized.

Further, the molding position of the second stopper layer is different from the optimum position due to the relative relationship of the polishing rate with the embedding material, and when the selection ratio is small, even up to the side wall of the embedding material convex portion. This may be done.

16 to 22 are sectional views of elements according to steps showing a second embodiment of the present invention, showing an example in which the present invention is applied to a multilayer wiring structure.

First, the p-type (100) has a specific resistance of 1 to 2 Ω.
cm silicon semiconductor substrate 401 is prepared, a first silicon oxide film 411 is grown to a thickness of 800 nm by a vapor deposition method, and a first aluminum film 412 is formed to a thickness of 600 nm by a sputtering method. The first silicon nitride film 413 is formed to a thickness of 50 nm. Next, a resist 414 is applied on the entire surface and patterned by photolithography (FIG. 16).

Next, this patterned resist 41 is formed.
Using the mask 4 as a mask, the first silicon nitride film 413 and the first aluminum film 412 are removed by etching by the RIE method and patterned to expose the silicon oxide film 411 (FIG. 17). After that, the resist 414 is removed.

Next, the second silicon oxide film 414 is formed by 60.
A second silicon nitride film 415 having a thickness of 0 nm is formed thereon.
Are sequentially deposited with a thickness of 50 nm. After this deposition,
In the recess having a relatively large area, the second silicon nitride film is also a recess.

Next, a resist is applied, and the resist pattern layer 416 corresponding to the recess is formed by photolithography.
Selectively remain (FIG. 18).

Then, using the resist pattern layer 416 as a mask, the second silicon nitride film 415 is etched by the RIE method to leave the second silicon nitride film 415 only in the wide concave portion. Then, the resist layer 416 is peeled off (FIG. 19).

Then, using the first silicon nitride film 413 and the second silicon nitride film 415 as stoppers, the second silicon oxide film 414 is polished to planarize the entire surface. The polishing conditions are the same as described with reference to FIG.

Next, the first silicon nitride film 413 and the second silicon nitride film 415 are removed by chemical dry etching, and a third silicon oxide film 416 is formed thereon by 60.
It is deposited by vapor deposition to a thickness of 0 nm (Fig. 2
1).

Next, aluminum is deposited on the entire surface by sputtering, and this is patterned by photolithography to form a second aluminum wiring film 417 (FIG. 22).

In such a wiring structure, the upper surface of the interlayer insulating film between the multi-layered wiring is covered with the wiring of the first layer (aluminum film 41).
Since the wiring can be formed substantially flat without being affected by the step of 2), the second layer wiring (aluminum film 417) is free from etching residue and disconnection that are likely to occur at the step, and reliability is improved.

As a third embodiment which is a modification of this embodiment, the first silicon nitride film 4 formed in the step of FIG. 16 is used.
An example in which 13 is omitted is shown in FIGS. 23 and 24.

FIG. 23 corresponds to the step of FIG.
A second silicon nitride film 415 is deposited in the wide recess, but a silicon nitride film is not formed on the first aluminum film 412. In this state, polishing is performed using the second silicon nitride film 415 as a stopper, and the polishing is stopped when the surface of the first aluminum film 412 is exposed (FIG. 24). Such a first aluminum film 41
The second surface can be obtained by monitoring the torque of the motor and detecting a large change in the torque. In this case, the aluminum film 412 is always over-etched, but since this film is only used as wiring, there is no particular problem. Further, this aluminum film can be formed thicker from the beginning by allowing for overetching.

Hereinafter, the second aluminum wiring film may be formed by the same process as shown in FIGS. 21 and 22.

With this method, it is possible to obtain a highly reliable wiring structure similar to that of the previous embodiment.

25 to 32 are cross-sectional views for each step showing the fourth embodiment of the present invention.

First, the p-type (100) has a specific resistance of 1 to 2 Ω.
A silicon semiconductor substrate 421 having a thickness of 15 cm is oxidized in an oxidizing atmosphere at 1000 ° C. to form a silicon oxide film 422 having a thickness of 15 nm as a protective film on the surface thereof. Further, a 100 nm-thickness polysilicon film 423 is deposited as a first stopper material on the silicon oxide film 422 by the CVD method (chemical vapor deposition method) (FIG. 25).

Next, a photoresist is applied on the polysilicon nitride film 423, and a resist pattern 424 obtained by photolithography of this is used as a mask to form a polysilicon film 423 on the region where the element isolation portion is to be formed by RIE. Then, the silicon oxide film 422 underneath is selectively removed to expose the surface of the semiconductor substrate 421 (FIG. 26).

Next, the semiconductor substrate 4 is formed by using the resist pattern 424 and the underlying polysilicon film 423 as a mask.
21 is further etched by the RIE method under another condition to form a groove 425 having a depth of about 0.5 μm on the surface of the semiconductor substrate 421 (FIG. 27).

Next, the unnecessary resist pattern 42
4 to remove the exposed groove 425 of the semiconductor substrate 421.
Perform a general decontamination process on the inner surface. After that, the substrate surface 421 is oxidized in an oxidizing atmosphere at 900 ° C. to form a silicon oxide film 426 having a film thickness of 10 nm as an insulating film on the surface. In this way, the convex portion 410 and the concave portion 425 are formed on the substrate surface 421 (FIG. 28).

Next, a silicon oxide film is deposited as a burying material by the low pressure CVD method to form a silicon oxide film layer 427 having a film thickness of 600 nm to fill the groove 425. At this point, the inside of the groove 425 has a silicon oxide film 426 as an insulating film.
And is completely filled with the CVD silicon oxide film 427 (FIG. 29).

Next, a second polysilicon film 428 as a second stopper is formed with a thickness of 150 nm by the CVD method (FIG. 30).

Next, a resist is applied to the entire surface and patterned by photolithography, and the resist pattern 429 left in a wide recess is used as a mask to form the element region 43.
The second polysilicon film 428 on and above 0 (substrate surface convex portion) and its periphery are selectively removed by the RIE method (FIG. 3).
1). At this time, a side wall 431 is formed at the step portion of the CVD silicon oxide film 427.

Next, the resist pattern 42 that has become unnecessary
9 is removed and mechanical polishing is performed to form the first polysilicon film 4
Polish until 23 is exposed. The polishing conditions at this time are
The polishing rate is 240 nm / for the CVD silicon oxide film 427.
The polysilicon films 423 and 428 are 30 nm
The polishing time is set to 3 minutes so that the over-polishing amount of the CVD silicon oxide film 427 is 20%. Further, the polysilicon film 428 partially remains for the same reason as described in FIG.

Then, polysilicon films 423 and 42 are formed.
A substantially flat surface is obtained by removing 8 and a MOS gate structure, source and drain diffusion layers are formed on the exposed substrate surface of the element region 430 by using a known method.
An inter-wiring insulating layer, lead electrode wiring, etc. are formed and necessary elements are built. In this case, the silicon oxide film 427 becomes an element isolation region.

In place of the step shown in FIG. 30, a third silicon oxide film 4 is further formed on the polysilicon film 428.
41 is deposited by the CVD method (FIG. 33) and is etched back by the RIE method using the patterned resist 442, the polysilicon film 443 and the third silicon oxide film 441 are formed in the step portion of the silicon oxide film 427.
Remain (FIG. 34). After that, when the resist is removed and polishing is performed, the state shown in FIG. 32 is obtained.

In this embodiment, since the silicon oxide film is also deposited on the wide concave portion, the flatness of the whole is improved before polishing and the flatness after polishing is improved.

FIG. 35 is a plan view showing an embodiment in which the second stopper layer is not formed in the concave portion between the element forming regions when the element forming regions are close to each other. In this example, two element formation regions 501 and 502 are close to each other by a distance x, and a second stopper layer 510 is formed in a wide concave portion around them in a distance a from the element formation region. . For this stopper layer, the thickness of the silicon oxide film deposited on the element formation region is W, and the minimum processing dimension is y. When (1) a> W (2) x <2a + y, the second layer is formed. Two conditions are defined: no stopper layer is deposited. Under such conditions, the mask for the stopper layer can be simplified.

Such masking is performed by the procedure shown in FIGS. 36 and 37. First, element formation regions 501 and 5
02 is expanded by the distance L1 (FIG. 36). This L1 is selected so as to satisfy the condition of L1> (2a + y) / 2. As a result, when the distance x is close, the expanded ranges of the two element regions are combined to form a pattern 503.

Next, as shown in FIG. 37, pattern 5
03 is reduced by L2 over the entire circumference. This L2 satisfies the condition of L2 <L1-a. Therefore, the second stopper layer is not formed between the element formation regions.

The formation of such a second stopper layer can be similarly applied when forming the wiring layer. FIG. 38 shows such an example. When the two wiring layers are close to each other, the stopper layer is not formed between them.

[0077]

As described above, in the method of manufacturing a semiconductor device of the present invention, after depositing a buried film on a semiconductor substrate having a convex portion and a concave portion, a stopper film for preventing excessive polishing in a wide concave portion. Therefore, excessive polishing that impairs the flatness does not proceed, and a buried film having a high flatness as a whole can be easily obtained.

Further, when the distance between the adjacent convex portions is equal to or smaller than a predetermined dimension, the mask can be simplified by not forming the stopper film there.

By providing the stopper layer also on the convex portion on the semiconductor substrate, it becomes easy to control the end point of polishing or etching.

Further, due to the combination of the materials of the first and second stopper layers (the selectivity of the polishing rate with the embedding material in the mechanical polishing and the optimization of the film thickness), it is required in the conventional planarization process. Further, the steps of forming the block resist layer and the flattening resist layer, the RIE etchback before polishing, etc. can be omitted, and a flattened structure can be realized more simply and more accurately than the conventional technique.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a basic semiconductor device manufacturing process of the present invention.

FIG. 2 is a cross-sectional view showing a basic semiconductor device manufacturing process of the present invention.

FIG. 3 is a cross-sectional view showing a basic semiconductor device manufacturing process of the present invention.

FIG. 4 is a cross-sectional view showing a basic semiconductor device manufacturing process of the present invention.

FIG. 5 is a cross-sectional view showing a basic semiconductor device manufacturing process of the present invention.

FIG. 6 is a cross-sectional view showing a more specific semiconductor device manufacturing process according to the first embodiment of the present invention.

FIG. 7 is a cross-sectional view showing a more specific semiconductor device manufacturing process according to the first embodiment of the present invention.

FIG. 8 is a sectional view showing a more specific semiconductor device manufacturing process according to the first embodiment of the present invention.

FIG. 9 is a cross-sectional view showing a more specific semiconductor device manufacturing process according to the first embodiment of the present invention.

FIG. 10 is a sectional view showing a more specific semiconductor device manufacturing process according to the first embodiment of the present invention.

FIG. 11 is a cross-sectional view showing a more specific semiconductor device manufacturing process according to the first embodiment of the present invention.

FIG. 12 is a cross-sectional view showing a more specific semiconductor device manufacturing process according to the first embodiment of the present invention.

FIG. 13 is a cross-sectional view showing a more specific semiconductor device manufacturing process according to the first embodiment of the present invention.

FIG. 14 is a cross-sectional view showing a more specific semiconductor device manufacturing process according to the first embodiment of the present invention.

FIG. 15 is a cross-sectional view showing a more specific semiconductor device manufacturing process according to the first embodiment of the present invention.

FIG. 16 is a cross-sectional view showing a semiconductor device manufacturing process according to the second embodiment of the present invention applied to a multilayer wiring structure.

FIG. 17 is a sectional view showing a semiconductor device manufacturing process according to the second embodiment of the present invention applied to a multilayer wiring structure.

FIG. 18 is a sectional view showing a semiconductor device manufacturing process according to the second embodiment of the present invention applied to a multilayer wiring structure.

FIG. 19 is a sectional view showing a semiconductor device manufacturing process according to the second embodiment of the present invention applied to a multilayer wiring structure.

FIG. 20 is a sectional view showing a semiconductor device manufacturing process according to the second embodiment of the present invention applied to a multilayer wiring structure.

FIG. 21 is a sectional view showing a semiconductor device manufacturing process according to the second embodiment of the present invention applied to a multilayer wiring structure.

FIG. 22 is a sectional view showing a semiconductor device manufacturing process according to the second embodiment of the present invention applied to a multilayer wiring structure.

FIG. 23 is a sectional view showing a semiconductor device manufacturing process according to the third embodiment of the present invention.

FIG. 24 is a sectional view showing a semiconductor device manufacturing process according to the third embodiment of the present invention.

FIG. 25 is a sectional view showing a semiconductor device manufacturing process according to the fourth embodiment of the present invention.

FIG. 26 is a sectional view showing a semiconductor device manufacturing process according to the fourth embodiment of the present invention.

FIG. 27 is a sectional view showing a semiconductor device manufacturing process according to the fourth embodiment of the present invention.

FIG. 28 is a sectional view showing a semiconductor device manufacturing process according to the fourth embodiment of the present invention.

FIG. 29 is a sectional view showing a semiconductor device manufacturing process according to the fourth embodiment of the present invention.

FIG. 30 is a sectional view showing a semiconductor device manufacturing process according to the fourth example of the present invention.

FIG. 31 is a sectional view showing a semiconductor device manufacturing process according to the fourth embodiment of the present invention.

FIG. 32 is a sectional view showing a semiconductor device manufacturing process according to the fourth embodiment of the present invention.

FIG. 33 is a sectional view showing a semiconductor device manufacturing process according to the fifth embodiment of the present invention.

FIG. 34 is a sectional view showing a semiconductor device manufacturing process according to the fifth embodiment of the present invention.

FIG. 35 is an explanatory diagram showing a positional relationship between a convex portion and a stopper layer provided in the concave portion.

FIG. 36 is an explanatory diagram showing a method of obtaining a mask pattern of a stopper layer when two recesses are close to each other.

FIG. 37 is an explanatory diagram showing a method of obtaining a mask pattern of a stopper layer when two recesses are close to each other.

FIG. 38 is an explanatory diagram showing a relationship between two metal wirings and a stopper layer.

FIG. 39 is a cross-sectional view showing the conventional semiconductor device manufacturing process.

FIG. 40 is a cross-sectional view showing a conventional semiconductor device manufacturing process.

FIG. 41 is a cross-sectional view showing a conventional semiconductor device manufacturing process.

FIG. 42 is a cross-sectional view showing a conventional semiconductor device manufacturing process.

FIG. 43 is a cross-sectional view showing a conventional semiconductor device manufacturing process.

FIG. 44 is a cross-sectional view showing the conventional semiconductor device manufacturing process.

FIG. 45 is a cross-sectional view showing a conventional semiconductor device manufacturing process.

FIG. 46 is a cross-sectional view showing a conventional semiconductor device manufacturing process.

[Explanation of symbols]

101, semiconductor substrate 201 first stopper material film 103 convex portion of semiconductor substrate surface 104 concave portion of semiconductor substrate surface 105 buried film 301 second stopper material film 401, 421 semiconductor substrate 402, 411, 422 silicon oxide film 403, 423 silicon nitride film 404, 409, 414, 416, 424, 429, 4
42 resist pattern 405, 425 concave portion 406, 426 silicon oxide film 407, 427, 441 CVD silicon oxide film (insulating film) 408, 428 second silicon nitride film 410, 430 element region (substrate surface convex portion) 412, 417 aluminum Films 413, 415 Silicon nitride films 431, 443 Side wall remaining silicon nitride films 501, 502 Element formation region 510

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI Technical display location H01L 21/304 321 M 8832-4M Z 8832-4M

Claims (14)

[Claims] 1. A step of forming a first stopper layer on the surface of the convex portion of a semiconductor substrate having a concave portion and a convex portion on the surface, and a step of filling the concave portion of the substrate surface on the entire surface of the semiconductor substrate. A step of forming a buried film; a step of selectively forming a second stopper layer on the surface of the buried film on the recessed region; A method of manufacturing a semiconductor device, comprising: a step of removing the embedded film. 2. The method of manufacturing a semiconductor device according to claim 1, wherein a film thickness of the second stopper layer is thinner than a step of the unevenness on the surface of the semiconductor substrate. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the first and second stopper layers are made of a material having a low etching rate. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the first and second stopper layers are made of a material having abrasion resistance. 5. An embedding embedded in a recess between both protrusions only when two adjacent protrusions are at a distance larger than twice the thickness of the embedding film plus the minimum feature size. The method of manufacturing a semiconductor device according to claim 1, wherein the second stopper layer is formed on the film. 6. The method of manufacturing a semiconductor device according to claim 1, wherein the thickness of the buried film is selected within a range of 80 to 120% of a step of the unevenness on the semiconductor substrate. 7. The convex portion is an initial surface of a semiconductor substrate,
The method of manufacturing a semiconductor device according to claim 1, wherein the recess is a groove formed in the semiconductor substrate. 8. The convex portion is a first metal wiring layer laminated on a semiconductor substrate via a silicon oxide film, and the concave portion is an initial surface of the semiconductor substrate. A method of manufacturing a semiconductor device according to item 1. 9. A step of depositing a silicon oxide film as an interlayer insulating film after the first stopper layer and the second stopper layer are removed, and a second metal wiring layer is formed on the silicon oxide film. The method of manufacturing a semiconductor device according to claim 8, further comprising a step of forming. 10. A step of forming an embedding film for embedding the recess on the surface of a semiconductor substrate having a recess and a protrusion on the surface, and selecting a first stopper layer on the surface of the embedding film on the recess region. And a step of planarly removing the embedded film by mechanical polishing until the surface of the convex portion is exposed, and a method of manufacturing a semiconductor device. 11. An embedding embedded in a concave portion between two convex portions only when two adjacent convex portions are at a distance larger than twice the thickness of the embedding film plus a minimum processing dimension. 11. The method of manufacturing a semiconductor device according to claim 10, wherein the second stopper layer is formed on the film. 12. A step of forming a first polysilicon layer as a first stopper layer on the surface of the convex portion of a semiconductor substrate having a concave portion and a convex portion on the surface, and a substrate surface on the entire surface of the semiconductor substrate. And a step of forming a buried film for filling the recess, and a second polysilicon layer as a second stopper layer is selectively formed on the surface of the buried film on the recess region by anisotropic etching. And a step of removing the buried film by mechanical polishing until the surface of the first stopper layer is exposed. 13. The step of selectively forming the second polysilicon layer further comprises forming a silicon oxide film on the deposited second polysilicon layer by a step not less than a step existing in the second polysilicon layer. 13. The method of manufacturing a semiconductor device according to claim 12, wherein the second polysilicon layer is patterned after the second polysilicon layer is deposited to a thickness of 13. 14. An embedding embedded in a recess between both protrusions only when two adjacent protrusions are at a distance larger than twice the thickness of the embedding film plus the minimum feature size. 13. The method of manufacturing a semiconductor device according to claim 12, wherein the second stopper layer is formed on the film.