JP3302142B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for filling a recessed portion of a semiconductor substrate surface having irregularities on its surface with an embedding material to flatten it.

[0002]

2. Description of the Related Art When manufacturing a highly integrated semiconductor device such as a VLSI, it is sometimes necessary to reduce a step formed on the surface of a semiconductor substrate. For example, in the multilayer wiring technology, if an interlayer insulating film is deposited on a first-layer metal wiring and a second-layer metal wiring is formed thereon, a level difference occurs in the second-layer metal wiring, and cutting is performed. In addition, there is a problem that the reliability is impaired due to the increase in resistance and resistance. Therefore, the interlayer insulating film deposited between the metal wirings is planarized.

Also, when a groove (trench) is formed on the surface of a semiconductor substrate in a DRAM or the like and is used as an element isolation or a capacitor, it is necessary to fill the groove which is a concave portion.

[0004] A conventional example of a technique for filling a concave portion formed on the surface of a semiconductor substrate to flatten the surface of the semiconductor substrate will be described below.

FIG. 39 illustrates a conventional technique for such flattening. The protrusion 1 is provided on the surface of the semiconductor substrate 101.
03 and the concave portion 104 are generated. Therefore, a burying material is deposited on the entire surface of the semiconductor substrate 101 to form a burying film 102 to bury the recess 104. Thereafter, as shown by a dotted line in the figure, the surface of the convex portion 103 is polished two-dimensionally from above, so that only the concave portion 104 is filled with the buried film 102 and the surface of the semiconductor substrate can be planarized. However, in such a method, a large concave portion or the like becomes a large depression, and the flatness of the surface obtained as a whole is not always good.

Another conventional example which solves such a problem will be described with reference to FIGS. In these figures, the same reference numerals are given to portions corresponding to FIG. First, a stopper layer 201 having a low polishing rate for mechanical polishing performed later is formed corresponding to the projections 103 on the surface of the semiconductor substrate 101 (FIG. 40).

Next, a burying material is deposited on the entire surface of the semiconductor substrate 101 to form a burying film 102 (FIG. 41).
In this state, the buried film 102 is also a recess 105 in the recess 104 having a relatively large area. A flattening block (resist layer) 202 is selectively formed in the recess 105 of the buried film 102 (FIG. 42). Next, a flattening material having high fluidity is applied to the uneven portions and dried to form a flattening film 203 (FIG. 43). Subsequently, the planarizing film 203, the planarizing block 202, and the buried film 102 are etched back to the vicinity of the stopper layer 201 by reactive ion etching (RIE) as anisotropic etching (FIG. 4).
4). Finally, the unevenness 204 on the substrate surface caused by the difference in the RIE etching rate between the materials is removed by mechanical polishing. At that time, the end point is controlled by the stopper layer 201 (FIG. 45).

The mechanical polishing used at this time is generally called a polishing method (lapping method).
A flat board is pressed and rotated on the surface of a semiconductor substrate. At this time, an abrasive suitable for cutting the material of the board surface is added between the flat board and the board surface to scrape the material of the board surface in one plane. . This abrasive is generally formed from a spherical particle of a silicon oxide film having a uniform particle size of several tenths to several microns of a tenth, and a liquid containing each of these particles separated and uniformly without gelation. Become.

Then, by removing the stopper layer 201 later, a structure in which the recess 104 of the semiconductor substrate is filled with the surface layer of the projection 103 of the semiconductor substrate 101 and the buried film 102 having a uniform plane is completed. (FIG. 46).

[0010]

However, in the above method, the planarizing block 202 and the two planarizing layers 102 and 203 have to be formed, which increases the number of manufacturing steps. Further, from the viewpoint of improving flatness, the flattening block and the flattening layer must have a uniform RIE etching rate with respect to the filling material. However, it is practically extremely difficult to select a material and conditions for keeping the RIE etching rate constant for the three layers as described above. are doing. In other words, the planarization process requires two processes of RIE and mechanical polishing, which also increases the number of manufacturing processes.

A method of forming the flattening block and the flattening layer and then flattening the whole by mechanical polishing alone can be considered. However, in this method, the polishing rate in mechanical polishing is considered from the viewpoint of manufacturing efficiency. Must be increased.
In addition, the in-plane variation of the polishing increases in proportion to the polishing rate, and the control of the mechanical polishing by the stopper layer becomes difficult. Also in this case, it is necessary to make the mechanical polishing rates uniform for the three layers as in the case of RIE from the viewpoint of flatness, but this is more difficult than in RIE. If mechanical polishing is performed without forming the flattening block 202 and the flattening layer 203 in order to shorten the polishing time, the polishing rate of the concave portion is smaller than that of the convex portion, but the area is small. At the center of the wide recessed region, the polishing rates of both become close to each other, and the filling material of the recessed portion is polished and removed. As a result, planarization cannot be realized.

Accordingly, an object of the present invention is to provide a method for easily realizing a highly accurate planarized structure.

[0013]

According to a method of manufacturing a semiconductor device according to the present invention, a step of forming a first stopper layer on a surface of a convex portion of a semiconductor substrate having a concave portion and a convex portion on the surface; Forming a buried film for burying the recess on the substrate surface over the entire surface of the semiconductor substrate, selectively forming a second stopper layer on the buried film surface over the recess region, Removing the buried film in a planar manner until the surface of the first stopper layer is exposed by selective polishing.

It is preferable that the thickness of the second stopper layer is smaller than a step of unevenness on the surface of the semiconductor substrate.

The first and second stopper layers are a silicon nitride film or a polysilicon film, or a group consisting of an abrasive carbon film, a tungsten film, a titanium film, or a compound of these and other substances. It is good that it is selected.

Only when the two adjacent protrusions are at a distance larger than a distance obtained by adding a minimum processing dimension to twice the thickness of the buried film, the buried film buried in the recess between the two protrusions. Preferably, the second stopper layer is formed.

It is preferable that the thickness of the buried film is selected in a range of 80 to 120% of a step of the unevenness on the semiconductor substrate.

The projection is an initial surface of the semiconductor substrate;
When the concave portion is a groove formed in the semiconductor substrate, the convex portion is a first metal wiring layer laminated on the semiconductor substrate via a silicon oxide film, and the concave portion is an initial surface of the semiconductor substrate. In any of the cases, the present invention is provided.

After the first stopper layer and the second stopper layer are removed, a step of depositing a silicon oxide film to be an interlayer insulating film, and forming a second metal wiring layer on the silicon oxide film And a step.

Further, according to the present invention, a step of forming a buried film for burying the concave portion on the surface of the semiconductor substrate having a concave portion and a convex portion on the surface, and forming a buried film on the surface of the buried film on the concave region. A step of selectively forming the first stopper layer and a step of planarly removing the buried film until the surface of the projection is exposed by mechanical polishing.

Only when the two adjacent protrusions are at a distance greater than the distance obtained by adding the minimum processing dimension to twice the thickness of the buried film, the buried film buried in the recess between the two protrusions. It is preferable that the second stopper layer is formed first.

Further, according to the present invention, a step of forming a first polysilicon layer as a first stopper layer on a surface of the convex portion of the semiconductor substrate having a concave portion and a convex portion on the surface; Forming a buried film for burying the concave portion on the substrate surface over the entire surface of the substrate, and forming a second stopper layer as a second stopper layer on the buried film surface on the concave region.
Selectively forming the polysilicon layer by anisotropic etching, and removing the buried film until the surface of the first stopper layer is exposed by mechanical polishing. .

The step of selectively forming the second polysilicon layer may further comprise the step of forming a silicon oxide film on the deposited second polysilicon layer with a thickness greater than or equal to a step difference existing in the second polysilicon layer. After the deposition, the pattern is preferably patterned together with the second polysilicon layer.

Only when the distance between two adjacent protrusions is greater than a distance obtained by adding a minimum processing dimension to twice the thickness of the buried film, the buried film buried in the recess between the two protrusions. Preferably, the second stopper layer is formed.

[0025]

After depositing a buried film on a semiconductor substrate having a convex portion and a concave portion, a stopper film for preventing excessive polishing and etching is formed in a wide concave portion. Excessive polishing that impairs the flatness does not proceed in the step of performing the etch back, and a buried film having a high flatness as a whole can be easily obtained. The relationship between the concave portions and the convex portions is applied to the cell structure and the multilayer wiring structure of the RAM. When the distance between the adjacent convex portions is equal to or less than a predetermined dimension, it is possible to prevent the stopper film from being formed thereon. The mask can be simplified.

By providing the stopper layer also on the convex portion on the semiconductor substrate, it becomes easy to control the end point of polishing or etching.

Furthermore, the combination of the materials of the first and second stopper layers (selectivity of the polishing rate with the embedding material in mechanical polishing and optimization of the film thickness) is required in the conventional flattening process. Steps such as formation of a block resist and a flattening resist, and RIE etch-back before polishing can be omitted, and a planarized structure can be realized more easily and more accurately than in the prior art.

[0028]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, a basic manufacturing process of the present invention will be described with reference to FIGS. In each figure, the same reference numerals are given to parts corresponding to the conventional example. In FIG. 1, a first stopper layer 201 is formed on the upper surface of a convex portion 103 of a semiconductor substrate 101 (FIG. 1). This first stopper layer 20
1 is formed of a material whose polishing rate is smaller than that of the embedding material so as to serve as a polishing stopper when polishing the embedding material laminated on the surface of the projection 103 on the surface of the substrate 101 in a subsequent polishing step. Is done. Embedded film 102 for embedding recess 104
Is uniformly formed over the entire surface of the uneven portion on the surface of the semiconductor substrate 101 (FIG. 2).

In the concave portion 104 having a relatively large area, a second stopper layer 301 is formed on the surface of the concave portion 105 of the buried film 102 (FIG. 3). This second stopper layer 30
1 also serves as a stopper when polishing the buried film 102 formed on the surface of the projection 103 on the surface of the substrate 101 in the subsequent polishing step. The material of the stopper layer 301 is selected so that the polishing rate is lower than the material of the buried film 102.

Next, the buried film 10 is planarized by mechanical polishing until the surface of the first stopper layer 201 is exposed.
2 is polished (FIG. 4). Subsequently, the first stopper layer 201
Then, the second stopper layer 301 is removed, and the surface of the projection 103 of the semiconductor substrate 101 is exposed. Thus, the surface of the semiconductor substrate 101 is planarized (FIG. 5).

In the above manufacturing process, for example, the buried film 1
02 is an insulating film, the concave portion 104 buried with the insulating film by the above method is an element isolation region, and the substrate surface of the convex portion 103 is an element region.
An element can be formed on this element region 103 separated by 02 by a known method.

In the above method, there is a difference in the polishing rate between the material of the second stopper layer 301 and the material of the buried film 102 by mechanical polishing.
01 is lower in polishing rate, and in order to ensure the polishing rate, the thickness of the second stopper layer 301 is smaller than the step of the unevenness on the surface of the substrate 101. Is close to the step of unevenness on the surface of the semiconductor substrate 101, and a large height difference between the surface of the convex portion 103 and the surface of the embedding material 102 embedded in the concave portion 104 having a width wider than twice the embedding film 102. It is required that there is no difference. In addition, it is desirable that the material of the first stopper layer 201 is ideally lower in mechanical polishing rate than the material of the buried film 102, similarly to the material of the second stopper material 301. This is not the case when the stopper effect due to the material of the layer 301 is large.

A specific example of the above manufacturing process will be described with reference to the drawings. FIGS. 6 to 15 are cross-sectional views for explaining steps of the first embodiment of the present invention, particularly showing a case where the present invention is applied to element isolation.

First, a P-type (100) having a specific resistance of 1-2Ω
By oxidizing the silicon semiconductor substrate 401 having a thickness of 15 cm in an oxidizing atmosphere at 1000 ° C., a silicon oxide film 402 having a thickness of 15 nm as a protective film is formed on the surface thereof. Further, a first silicon nitride film 403 having a thickness of 100 nm is deposited as a first stopper material on the silicon oxide film 402 by a CVD method (chemical vapor deposition method) (FIG. 6).

Next, a photoresist is applied on the silicon nitride film 403, and using the resist pattern 404 obtained by photolithography as a mask, the first silicon nitride film 403 and the The silicon oxide film 402 thereunder is selectively removed to expose the surface of the semiconductor substrate 401. An RIE method (reactive ion etching) which is anisotropic etching is used for this removal (FIG. 7).

Next, using the resist pattern 404 and the underlying silicon nitride film 403 as a mask, the semiconductor substrate 4
01 is further etched by the RIE method under another condition to form a groove 405 having a depth of about 0.5 μm on the surface of the semiconductor substrate 401 (FIG. 8).

Subsequently, the unnecessary resist pattern 40
4 is removed, and the exposed groove 405 of the semiconductor substrate 401 is removed.
General decontamination treatment of the surface inside. Thereafter, the substrate surface 401 is oxidized in an oxidizing atmosphere at 900 ° C., thereby forming a silicon oxide film 406 having a thickness of 10 nm as an insulating film on the surface. A convex portion 410 and a concave portion 405 are formed on the substrate surface 401 (FIG. 9).

Next, a silicon oxide film is deposited as a filling material by a low pressure CVD method, and a silicon oxide film layer 407 having a thickness of 600 nm is formed to fill the groove 405. at this point,
The inside of the groove 405 contains a silicon oxide film 406 as an insulating film and C
Completely filled with VD silicon oxide film 407 (FIG. 1)
0).

Next, a second silicon nitride film 408 as a second stopper is formed with a thickness of 150 nm by the CVD method (FIG. 11).

Next, a resist is applied to the entire surface, and is patterned by photolithography.
Using the mask 9 as a mask, the second silicon nitride film 408 on the element region 410 (projection on the substrate surface) and its periphery is selectively removed (FIG. 12).

Next, the unnecessary resist pattern 40
9 is removed, and the protruding CVD silicon oxide film 407 is polished and removed by a polishing method until the first silicon nitride film 403 is uniformly exposed from above. The polishing conditions at this time are as follows: the polishing rate is 150 nm / min for the CVD silicon oxide film 407 and the silicon nitride films 403 and 40
8 was set to 30 nm / min, and the polishing time was CV.
20% overpolishing amount for D silicon oxide film 407
5 minutes.

Therefore, the second silicon nitride film 408 exposed from the beginning of polishing is polished at the original polishing rate of the designed silicon nitride film 408, especially at a position apart from the step, so that almost all the film is removed. Thickness is reduced. However, in the vicinity of the step, the pressure at the time of polishing applied to the second silicon nitride film 408 is weakened due to the influence of the convex portion 410, and the polishing speed is decreased. (FIG. 13).

Next, as shown in FIG. 14, the exposed first silicon nitride film 403 and the remaining second silicon nitride film 408 can be removed. By performing such removal, the gettering effect can be improved.

The silicon oxide film 402 on the element region 410 (convex portion) of the semiconductor substrate 401 is etched away by a hydrofluoric acid solution (ammonium fluoride solution) for 15 seconds to a thickness of 25 nm, and the surface of the semiconductor substrate 401 is etched. Expose it. Thereafter, a MOS gate structure, a source / drain diffusion layer, an inter-wiring insulating layer, a lead electrode wiring, and the like are formed on the exposed substrate surface of the element region 410 by using a well-known method, and necessary elements are formed (FIG. 15).

In this manner, the method of the present invention makes it possible to bury a buried material in a buried element isolation region in a flat and simple manner.
In order to prevent the polishing rate of the protruding embedding material 407 from being impaired, the height of the surface of the second stopper material is smaller than the height of the protruding portion of the embedding material 407 by polishing loss. It is set low so as to be small. It is also desirable to select a material having an extremely low polishing rate for the second stopper material and to reduce its film thickness. Therefore, as an application of the embodiment, a material having high wear resistance and a lower polishing rate, such as a carbon film having a high hardness and a low mechanical polishing rate, a high melting point metal such as a tungsten (W) film and a titanium (Ti) film, etc. By selecting a film or a compound film thereof as the second stopper material, a better polished flat surface can be realized.

Furthermore, the forming position of the second stopper layer is different from the optimum position due to the relative relationship of the polishing rate with the embedding material. Such a configuration may be adopted.

FIGS. 16 to 22 are cross-sectional views of a device according to a second embodiment of the present invention, showing an example in which the present invention is applied to a multilayer wiring structure.

First, a P-type (100) having a specific resistance of 1-2Ω
cm of a silicon semiconductor substrate 401, a first silicon oxide film 411 is grown to a thickness of 800 nm by a vapor phase growth method, and a first aluminum film 412 is formed to a thickness of 600 nm by a sputtering method. A first silicon nitride film 413 is formed to a thickness of 50 nm. Next, a resist 414 is applied on the entire surface and is patterned by a photolithography method (FIG. 16).

Next, the patterned resist 41
Using the mask 4 as a mask, the first silicon nitride film 413 and the first aluminum film 412 are etched away by RIE and patterned to expose the silicon oxide film 411 (FIG. 17). After that, the resist 414 is removed.

Next, the second silicon oxide film 414 is
A thickness of 0 nm and a second silicon nitride film 415 thereon
Are sequentially deposited in a thickness of 50 nm. After this deposition,
In the recess having a relatively large area, the second silicon nitride film is also a recess.

Next, a resist is applied, and the resist is applied by photolithography to the resist pattern layer 416 corresponding to the concave portions.
Are selectively left (FIG. 18).

Then, using the resist pattern layer 416 as a mask, the second silicon nitride film 415 is etched by RIE to leave the second silicon nitride film 415 only in a wide recess. Then, the resist layer 416 is peeled off (FIG. 19).

Subsequently, using the first silicon nitride film 413 and the second silicon nitride film 415 as stoppers, the second silicon oxide film 414 is polished to flatten the whole. The polishing conditions are the same as those described with reference to FIG.

Next, the first silicon nitride film 413 and the second silicon nitride film 415 are removed by chemical dry etching, and a third silicon oxide film 416 is
Deposited by vapor deposition with a thickness of 0 nm (FIG. 2
1).

Next, aluminum is deposited on the entire surface by sputtering, and is patterned by photolithography to form a second aluminum wiring film 417 (FIG. 22).

In such a wiring structure, the upper surface of the interlayer insulating film between the multilayer wirings is placed on the first layer wiring (the aluminum film 41).
Since the second layer wiring (aluminum film 417) can be formed almost flat without being affected by the step of 2), there is no etching residue or disconnection that is likely to occur due to the step, and the reliability is improved.

As a third embodiment which is a modification of this embodiment, the first silicon nitride film 4 formed in the process of FIG.
Examples in which 13 is omitted are shown in FIGS.

FIG. 23 corresponds to the step of FIG.
Although the second silicon nitride film 415 is deposited in the wide recess, the silicon nitride film is not formed on the first aluminum film 412. In this state, polishing is performed using the second silicon nitride film 415 as a stopper, and the polishing is stopped when the surface of the first aluminum film 412 is exposed (FIG. 24). Such a first aluminum film 41
The surface 2 can be performed by monitoring the torque of the motor and detecting a large change thereof. In this case, the aluminum film 412 is always over-etched. However, since this film is only used as a wiring, there is no particular problem. Further, the aluminum film can be formed thicker from the beginning with an allowance for overetching.

In the following, the second aluminum wiring film may be formed by the same steps as those shown in FIGS.

With this method, a highly reliable wiring structure similar to that of the previous embodiment can be obtained.

FIGS. 25 to 32 are sectional views showing steps in the fourth embodiment of the present invention.

First, a P-type (100) having a specific resistance of 1-2Ω
By oxidizing the silicon semiconductor substrate 421 having a thickness of 1000 cm in an oxidizing atmosphere at 1000 ° C., a silicon oxide film 422 having a thickness of 15 nm as a protective film is formed on the surface thereof. Further, a polysilicon film 423 having a thickness of 100 nm is deposited as a first stopper material on the silicon oxide film 422 by CVD (chemical vapor deposition) (FIG. 25).

Next, a photoresist is applied on the polysilicon nitride film 423, and the photoresist film 424 obtained by photolithography is used as a mask. And the silicon oxide film 422 thereunder is selectively removed to expose the surface of the semiconductor substrate 421 (FIG. 26).

Next, using the resist pattern 424 and the polysilicon film 423 thereunder as a mask, the semiconductor substrate 4
21 is further etched by RIE under different conditions to form a groove 425 having a depth of about 0.5 μm on the surface of the semiconductor substrate 421 (FIG. 27).

Next, the unnecessary resist pattern 42
4 is removed, and the groove 425 of the exposed semiconductor substrate 421 is removed.
General decontamination treatment of the surface inside. Thereafter, the substrate surface 421 is oxidized in an oxidizing atmosphere at 900 ° C., thereby forming a 10-nm-thick silicon oxide film 426 as an insulating film on the surface. In this way, the protrusions 410 and the recesses 425 are formed on the substrate surface 421 (FIG. 28).

Next, a silicon oxide film is deposited as a filling material by a low pressure CVD method, and a silicon oxide film layer 427 having a thickness of 600 nm is formed to fill the groove 425. At this time, the inside of the groove 425 is a silicon oxide film 426 as an insulating film.
And a CVD silicon oxide film 427 (FIG. 29).

Next, a second polysilicon film 428 as a second stopper is formed with a thickness of 150 nm by the CVD method (FIG. 30).

Next, a resist is applied to the entire surface, and is patterned by photolithography to form a resist pattern 429 left in a wide recess as a mask.
The second polysilicon film 428 on and around the substrate 0 (projection on the surface of the substrate) and the periphery thereof are selectively removed by RIE (FIG.
1). At this time, a side wall 431 is formed at the step portion of the CVD silicon oxide film 427.

Next, the unnecessary resist pattern 42
9 is removed and the first polysilicon film 4 is subjected to mechanical polishing.
Polish until 23 is exposed. The polishing conditions at this time are as follows:
The polishing rate was 240 nm / cm for the CVD silicon oxide film 427.
30 nm for polysilicon films 423 and 428
/ Min, and the polishing time is set to 3 minutes so that the over-polishing amount with respect to the CVD silicon oxide film 427 becomes 20%. Further, the polysilicon film 428 partially remains for the same reason as described with reference to FIG.

Thereafter, the polysilicon films 423 and 42
8, a substantially flat surface is obtained, and the MOS gate structure, the source / drain diffusion layers, and the like are formed on the substrate surface of the element region 430 exposed by using a known method.
The required elements are formed by forming an insulating layer between wirings, lead electrode wirings, and the like. In this case, the silicon oxide film 427 becomes an element isolation region.

The third silicon oxide film 4 is further formed on the polysilicon film 428 in place of the process shown in FIG.
41 is deposited by the CVD method (FIG. 33) and is etched back by the RIE method using the patterned resist 442, and the polysilicon film 443 and the third silicon oxide film 441 are formed at the steps of the silicon oxide film 427.
Remain (FIG. 34). Thereafter, if the resist is removed and polishing is performed, the state shown in FIG. 32 is obtained.

In this embodiment, since the silicon oxide film is deposited also on the wide concave portion, the overall flatness is improved before polishing and the flatness after polishing is improved.

FIG. 35 is a plan view showing an embodiment in which the second stopper layer is not formed in the recess between the element forming regions when they are close to each other. In this example, the two element formation regions 501 and 502 are close to each other by a distance x, and a second stopper layer 510 is formed in a wide recess around them at a distance a from the element formation region. . For this stopper layer, the thickness of the silicon oxide film deposited on the element formation region is W, and the minimum processing dimension is y. (1) a> W (2) When x <2a + y, the second Two conditions for not depositing the stopper layer are defined. Under such conditions, the mask for the stopper layer can be simplified.

Such a mask is formed by a procedure as shown in FIGS. 36 and 37. First, the element formation regions 501, 5
02 is extended by the distance L1 (FIG. 36). This L1 is selected so as to satisfy the condition of L1> (2a + y) / 2. As a result, when the distance x is short, the enlarged ranges of the two element regions are combined to form a pattern 503.

Next, as shown in FIG.
03 is reduced by L2 over the entire circumference. This L2 is set to satisfy the condition of L2 <L1-a. Therefore, no second stopper layer is formed between the element forming regions.

The formation of the second stopper layer can be similarly applied to the formation of the wiring layer. FIG. 38 shows such an example. When two wiring layers are close to each other, no stopper layer is formed between them.

[0077]

As described above, in the method of manufacturing a semiconductor device according to the present invention, after a buried film is deposited on a semiconductor substrate having a convex portion and a concave portion, a stopper film for preventing excessive polishing is formed in a wide concave portion. Is formed, excessive polishing that impairs the flatness does not proceed, and a buried film having a high flatness as a whole can be easily obtained.

When the distance between adjacent protrusions is smaller than a predetermined dimension, the mask can be simplified by not forming a stopper film there.

By providing the stopper layer also on the projection on the semiconductor substrate, the end point of polishing or etching can be easily controlled.

Further, the combination of the materials of the first and second stopper layers (selectivity of the polishing rate with the embedding material in mechanical polishing and optimization of the film thickness) is required in the conventional flattening step. Steps such as formation of a block resist layer and a flattening resist layer, and RIE etchback before polishing can be omitted, and a planarized structure can be realized more easily and more accurately than in the prior art.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a basic semiconductor device manufacturing process of the present invention.

FIG. 2 is a sectional view showing a basic semiconductor device manufacturing process of the present invention.

FIG. 3 is a sectional view showing a basic semiconductor device manufacturing process of the present invention.

FIG. 4 is a sectional view showing a basic semiconductor device manufacturing process of the present invention.

FIG. 5 is a sectional view showing a basic semiconductor device manufacturing process of the present invention.

FIG. 6 is a sectional view showing a more specific semiconductor device manufacturing process according to the first embodiment of the present invention.

FIG. 7 is a cross-sectional view showing a more specific semiconductor device manufacturing process according to the first embodiment of the present invention.

FIG. 8 is a cross-sectional view showing a more specific semiconductor device manufacturing process according to the first embodiment of the present invention.

FIG. 9 is a cross-sectional view showing a more specific semiconductor device manufacturing process according to the first embodiment of the present invention.

FIG. 10 is a sectional view showing a more specific semiconductor device manufacturing process according to the first embodiment of the present invention.

FIG. 11 is a sectional view showing a more specific semiconductor device manufacturing process according to the first embodiment of the present invention.

FIG. 12 is a sectional view showing a more specific semiconductor device manufacturing process according to the first embodiment of the present invention;

FIG. 13 is a sectional view showing a more specific semiconductor device manufacturing process according to the first embodiment of the present invention.

FIG. 14 is a sectional view showing a more specific semiconductor device manufacturing process according to the first embodiment of the present invention.

FIG. 15 is a sectional view showing a more specific semiconductor device manufacturing process according to the first embodiment of the present invention.

FIG. 16 is a cross-sectional view showing a semiconductor device manufacturing process according to a second embodiment of the present invention applied to a multilayer wiring structure.

FIG. 17 is a cross-sectional view showing a semiconductor device manufacturing process according to a second embodiment of the present invention applied to a multilayer wiring structure.

FIG. 18 is a cross-sectional view showing a semiconductor device manufacturing process according to a second embodiment of the present invention applied to a multilayer wiring structure.

FIG. 19 is a cross-sectional view showing a semiconductor device manufacturing process according to a second embodiment of the present invention applied to a multilayer wiring structure.

FIG. 20 is a cross-sectional view showing a semiconductor device manufacturing process according to a second embodiment of the present invention applied to a multilayer wiring structure.

FIG. 21 is a sectional view showing a semiconductor device manufacturing process according to a second embodiment of the present invention applied to a multilayer wiring structure.

FIG. 22 is a cross-sectional view showing a semiconductor device manufacturing process according to a second embodiment of the present invention applied to a multilayer wiring structure.

FIG. 23 is a cross-sectional view showing a semiconductor device manufacturing process according to a third example of the present invention.

FIG. 24 is a cross-sectional view showing a semiconductor device manufacturing process according to a third example of the present invention.

FIG. 25 is a sectional view illustrating a semiconductor device manufacturing process according to a fourth embodiment of the present invention.

FIG. 26 is a sectional view illustrating a semiconductor device manufacturing process according to a fourth embodiment of the present invention.

FIG. 27 is a sectional view illustrating a semiconductor device manufacturing process according to a fourth embodiment of the present invention.

FIG. 28 is a cross-sectional view showing a semiconductor device manufacturing process according to a fourth embodiment of the present invention.

FIG. 29 is a cross-sectional view showing a semiconductor device manufacturing process according to the fourth embodiment of the present invention.

FIG. 30 is a cross-sectional view showing a semiconductor device manufacturing process according to a fourth embodiment of the present invention.

FIG. 31 is a cross-sectional view showing a semiconductor device manufacturing process according to a fourth embodiment of the present invention.

FIG. 32 is a sectional view illustrating a semiconductor device manufacturing process according to a fourth embodiment of the present invention;

FIG. 33 is a cross-sectional view showing a semiconductor device manufacturing process according to the fifth embodiment of the present invention.

FIG. 34 is a cross-sectional view showing a semiconductor device manufacturing process according to the fifth embodiment of the present invention.

FIG. 35 is an explanatory diagram showing a positional relationship between a convex portion and a stopper layer provided in a concave portion.

FIG. 36 is an explanatory diagram showing a method for obtaining a mask pattern of a stopper layer when two concave portions are close to each other.

FIG. 37 is an explanatory diagram showing a method for obtaining a mask pattern of a stopper layer when two concave portions are close to each other.

FIG. 38 is an explanatory diagram showing a relationship between two metal wirings and a stopper layer.

FIG. 39 is a cross-sectional view showing a conventional semiconductor device manufacturing process.

FIG. 40 is a cross-sectional view showing a conventional semiconductor device manufacturing process.

FIG. 41 is a cross-sectional view showing a conventional semiconductor device manufacturing process.

FIG. 42 is a cross-sectional view showing a conventional semiconductor device manufacturing process.

FIG. 43 is a cross-sectional view showing a conventional semiconductor device manufacturing process.

FIG. 44 is a cross-sectional view showing a conventional semiconductor device manufacturing process.

FIG. 45 is a cross-sectional view showing a conventional semiconductor device manufacturing process.

FIG. 46 is a cross-sectional view showing a conventional semiconductor device manufacturing process.

[Explanation of symbols]

Reference Signs List 101, semiconductor substrate 201 first stopper material film 103 convex portion on semiconductor substrate surface 104 concave portion on semiconductor substrate surface 105 buried film 301 second stopper material film 401, 421 semiconductor substrate 402, 411, 422 silicon oxide film 403, 423 silicon nitride film 404, 409, 414, 416, 424, 429, 4
42 resist pattern 405, 425 recess 406, 426 silicon oxide film 407, 427, 441 CVD silicon oxide film (insulating film) 408, 428 second silicon nitride film 410, 430 element region (substrate surface convex portion) 412, 417 aluminum Films 413 and 415 Silicon nitride films 431 and 443 Residual silicon nitride films 501 and 502 on sidewalls Element formation region 510

────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-63-76349 (JP, A) JP-A-5-326690 (JP, A) JP-A-5-315308 (JP, A) JP-A-5-315308 275527 (JP, A) JP-A-5-259135 (JP, A) JP-A-4-253322 (JP, A) JP-A-4-250650 (JP, A) JP-A-1-290236 (JP, A) (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/3205 H01L 21/304 622 H01L 21/3065 H01L 21/3213

Claims (15)

(57) [Claims] A step of forming a first stopper layer on a surface of the convex portion of the semiconductor substrate having a concave portion and a convex portion on the surface; and embedding the concave portion of the substrate surface over the entire surface of the semiconductor substrate. Forming a buried film; and when the two adjacent protrusions are at a distance greater than twice the thickness of the buried film plus a minimum processing dimension,
Selectively forming a second stopper layer on the surface of the buried film on the concave region between the two convex portions; and planarizing the buried film until the surface of the first stopper layer is exposed by mechanical polishing. A method of manufacturing a semiconductor device, comprising: A step of forming a first stopper layer on the surface of the projection of the semiconductor substrate having a depression and a projection on the surface; and embedding the depression on the surface of the substrate over the entire surface of the semiconductor substrate. A step of forming a buried film; a step of selectively forming a second stopper layer on the surface of the buried film on the recessed region; and a planar process until the surface of the first stopper layer is exposed by mechanical polishing. Removing the buried film, wherein the convex portion is a first metal wiring layer laminated on a semiconductor substrate via a silicon oxide film, and the concave portion is an initial surface of the semiconductor substrate. A method for manufacturing a semiconductor device, comprising: 3. A step of depositing a silicon oxide film serving as an interlayer insulating film after the first stopper layer and the second stopper layer are removed, and a second metal wiring layer on the silicon oxide film. 3. The method of manufacturing a semiconductor device according to claim 2, further comprising the step of: 4. A step of forming a buried film for burying the concave portion on a surface of a semiconductor substrate having a concave portion and a convex portion on a surface, and selecting a first stopper layer on the surface of the buried film on the concave region. Forming, and removing the buried film two-dimensionally until the surface of the convex portion is exposed by mechanical polishing, wherein two adjacent convex portions have a thickness of the buried film. When the distance is greater than the distance obtained by adding the minimum processing dimension twice,
A method of manufacturing a semiconductor device, wherein the second stopper layer is formed on a buried film buried in a concave portion between both convex portions. 5. A step of forming a first polysilicon layer as a first stopper layer on a surface of the convex portion of the semiconductor substrate having a concave portion and a convex portion on the surface, and a substrate surface on the entire surface of the semiconductor substrate. Forming a buried film for burying the concave portion, and selectively forming a second polysilicon layer as a second stopper layer on the surface of the buried film over the concave region by anisotropic etching. A method of manufacturing a semiconductor device, comprising: a step of removing the buried film until the surface of the first stopper layer is exposed by mechanical polishing. 6. The step of selectively forming the second polysilicon layer further comprises the step of forming a silicon oxide film on the deposited second polysilicon layer by a level difference greater than or equal to a level difference existing in the second polysilicon layer. 6. The method according to claim 5, further comprising patterning the semiconductor device together with the second polysilicon layer after depositing the semiconductor device with the first semiconductor layer. 7. An embedding buried in a concave portion between two convex portions only when a distance between two adjacent convex portions is greater than a distance obtained by adding a minimum processing dimension to twice the thickness of the embedded film. 6. The method according to claim 5, wherein the second stopper layer is formed on the film. 8. A step of forming a first silicon oxide film on a semiconductor substrate, forming a metal wiring layer on the first silicon oxide film, and forming a first stopper layer on the metal wiring layer; Patterning the metal wiring layer and the first stopper layer, using the remaining metal wiring layer and the region of the first stopper layer as projections, and removing the metal wiring layer And forming a recess in the region of the first stopper layer; forming an embedded film for embedding the recess in the substrate surface over the entire surface of the semiconductor substrate; and forming the embedded film on the surface of the embedded film in the recess region. A step of selectively forming a second stopper layer; a step of removing the buried film until the surface of the first stopper layer is exposed by mechanical polishing; and a step of removing the first stopper layer and the second strike. Method of manufacturing a semiconductor device characterized by comprising a step of removing the path layer. 9. A step of depositing a silicon oxide film as an intermediate insulating film after removing the first stopper layer and the second stopper layer, and a second metal wiring on the deposited silicon oxide film. The method of manufacturing a semiconductor device according to claim 8, further comprising: forming a layer. 10. A step of forming a concave region and a convex region on a surface of a semiconductor substrate, and a burying film for burying the concave portion on the surface of the semiconductor substrate having the concave region and the convex region. Forming a stopper layer on the surface of the buried film in a stopper pattern; and removing the buried film planarly until the surface of the convex region is exposed by mechanical polishing. Removing the stopper layer, wherein the stopper pattern is shorter than the distance L1 after forming a combined pattern by extending and combining the patterns of the plurality of convex regions by a distance L1 to form a combined pattern. A method for manufacturing a semiconductor device, characterized by being obtained by using a step of reducing the coupling pattern by a distance L2. 11. The method of manufacturing a semiconductor device according to claim 10, wherein L2 <L1-a, where a is the minimum value of the distance between the patterns of the convex region. 12. When a minimum value of a distance between patterns of the convex region is a and a minimum processing dimension is y, L1 <
11. The method according to claim 10, wherein (2a + y) / 2. 13. A step of forming a concave area and a convex area on a surface of a semiconductor substrate, a step of forming a first stopper layer on the semiconductor substrate in the convex area, and a step of forming the concave area and the convex section. Forming a buried film for burying the recess on the surface of the semiconductor substrate having a region; and forming a second stopper layer on the surface of the buried film by a stopper.
Forming a pattern, removing the buried film in a plane until the surface of the first stopper layer is exposed by mechanical polishing, and removing the first stopper layer. The stopper pattern is formed by expanding and combining a plurality of patterns of the convex regions by a distance L1 to form a combined pattern, and then reducing the combined pattern by a distance L2 shorter than the distance L1. And a method for manufacturing a semiconductor device. 14. The method according to claim 13, wherein L2 <L1-a, where a is the minimum value of the distance between the patterns of the convex region. 15. When a minimum value of the distance between the patterns of the convex region is a and a minimum processing size is y, L1 <
14. The method according to claim 13, wherein (2a + y) / 2.