JPS61113237A - Method for etching polysilicon - Google Patents
Method for etching polysiliconInfo
- Publication number
- JPS61113237A JPS61113237A JP23619984A JP23619984A JPS61113237A JP S61113237 A JPS61113237 A JP S61113237A JP 23619984 A JP23619984 A JP 23619984A JP 23619984 A JP23619984 A JP 23619984A JP S61113237 A JPS61113237 A JP S61113237A
- Authority
- JP
- Japan
- Prior art keywords
- polysilicon
- photoresist
- etching
- mask
- oxide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 47
- 229920005591 polysilicon Polymers 0.000 title claims abstract description 47
- 238000005530 etching Methods 0.000 title claims abstract description 23
- 238000000034 method Methods 0.000 title claims abstract description 15
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 30
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 12
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 12
- 239000004065 semiconductor Substances 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 5
- 239000011248 coating agent Substances 0.000 claims 1
- 238000000576 coating method Methods 0.000 claims 1
- 238000001312 dry etching Methods 0.000 abstract description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052710 silicon Inorganic materials 0.000 abstract description 2
- 239000010703 silicon Substances 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 3
- 239000003795 chemical substances by application Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
この発明は、集積回路等の製造プロセスに係り、特にポ
リシリコン層のエツチング方法に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application This invention relates to a manufacturing process for integrated circuits and the like, and particularly to a method for etching a polysilicon layer.
（ロ）従来技術
一般に、Ｃ−ＭＯＳデバイスのゲート電極などのポリシ
リコン層を形成する場合は、まず、半導体基板の表面に
形成されたポリシリコンの上部に直接ホトレジストを塗
布してベーキングした後、露光・現像・ドライエツチン
グ工程を経て前記ポリシリコンに所定のパターンを形成
させている。(b) Prior Art Generally, when forming a polysilicon layer such as a gate electrode of a C-MOS device, first, photoresist is applied directly to the top of the polysilicon formed on the surface of a semiconductor substrate, and then baked. A predetermined pattern is formed on the polysilicon through exposure, development, and dry etching steps.
しかしながら、前記ポリシリコンとホトレジストとの密
着性が比較的弱いのでその界面にエツチング剤が回り込
んで第２図に示すように該ポリシリコンのサイドエツチ
ングの発生が大きくなり、ひいては寸法のバラツキを生
じることとなる。つまり、゛上記従来行われていた方法
では、微細なパターンを形成するのが非常に困難なので
、歩留りの低減を招くという問題を生じる。However, since the adhesion between the polysilicon and the photoresist is relatively weak, the etching agent wraps around the interface, resulting in increased side etching of the polysilicon as shown in FIG. 2, which in turn causes dimensional variations. That will happen. In other words, with the conventional methods described above, it is very difficult to form fine patterns, resulting in a problem of reduced yield.
（ハ）目的
この発明は、ポリシリコンのサイドエツチングの発生を
最小に抑え、歩留りを向上せしめるポリシリコンのエツ
チング方法を提供することを目的としている。(C) Objective The object of the present invention is to provide a polysilicon etching method that minimizes the occurrence of side etching of polysilicon and improves yield.
（ニ）構成
この発明に係るポリシリコンのエツチング方法の特徴と
する処は、半導体基板の表面にポリシリコンを形成した
後、前記ポリシリコンおよびこれのマスクとなるホトレ
ジストにそれぞれ良好な密着性を有する層を前記ポリシ
リコンの上部に形成させる工程と、前記層の上部に前記
ポリシリコンをエツチングするためのマスクとなるホト
レジストを被着させる工程と、前記ホトレジストに所望
ノカットパターンを形成し、このホトレジストをマスク
として前記層およびポリシリコンを順次エツチングさせ
る工程とを具備したことにある。(D) Structure The polysilicon etching method according to the present invention is characterized in that after forming polysilicon on the surface of a semiconductor substrate, it has good adhesion to the polysilicon and the photoresist that serves as a mask for the polysilicon. forming a layer on top of the polysilicon; depositing a photoresist on top of the layer as a mask for etching the polysilicon; forming a desired uncut pattern in the photoresist; The method further comprises a step of sequentially etching the layer and polysilicon using the mask as a mask.
（ホ）実施例
第１図はこの発明に係るポリシリコンのエツチング方法
の一実施例を説明するための参考図であり、同図を参考
にして以下説明する。(E) Embodiment FIG. 1 is a reference diagram for explaining an embodiment of the polysilicon etching method according to the present invention, and the following description will be made with reference to the same figure.
■ シリコンウェハからなる半導体基板１０の表面にポ
リシリコン２０を形成する。(2) Forming polysilicon 20 on the surface of semiconductor substrate 10 made of a silicon wafer.
■ ポリシリコン２０とホトレジスト４０とにそれぞれ
良好な密着性を有する層として例えばシリコン酸化膜３
０を、低温酸化膜成長装置でもって前記ポリシリコン２
０の上部に約１００〜１０００人形成させる。■ For example, a silicon oxide film 3 is used as a layer having good adhesion to the polysilicon 20 and the photoresist 40, respectively.
0 to the polysilicon 2 using a low-temperature oxide film growth apparatus.
Approximately 100 to 1000 people will be formed at the top of 0.
■ 前記シリコン酸化膜３０の上部にホトレジスト４０
を塗布してベーキングする。■ Photoresist 40 is placed on top of the silicon oxide film 30.
Apply and bake.
■ 露光・現像することにより前記ホトレジスト４０に
所定のカットパターンを形成する。(2) A predetermined cut pattern is formed on the photoresist 40 by exposure and development.
■ このホトレジスト４０をマスクとしてドライエツチ
ングすることによりシリコン酸化膜３０およびホトレジ
スト４０を順次エツチングする。なお、シリコン酸化１
１ｉ３０エツチング後にはこのシリコン酸化Ｉｌ！３０
とホトレジスト４０とがポリシリコン２０のマスクとな
る。(2) The silicon oxide film 30 and the photoresist 40 are sequentially etched by dry etching using the photoresist 40 as a mask. In addition, silicon oxide 1
After 1i30 etching, this silicon oxide Il! 30
and photoresist 40 serve as a mask for polysilicon 20.
■゛以下ボリシ＋７コン２０上のシリコン酸化ｙ！３０
およびホトレジスト４０を除去させる。■ ゛Silicon oxidation on the bottom + 7 and 20 y! 30
Then, the photoresist 40 is removed.
なお、ポリシリコン２０の上部にシリコン酸化膜３０を
形成させる装置は、上記実施例のものに限定されないこ
とは勿論である。Note that the apparatus for forming the silicon oxide film 30 on the top of the polysilicon 20 is of course not limited to that of the above embodiment.
しかして、上記のようにポリシリコン２０およびホトレ
ジスト４０にそれぞれ良好な密着性を有する層としてシ
リコン酸化膜３０を用いる場合においては、前記ポリシ
リコンのサイドエツチングの発生を殆ど防止でき、これ
により歩留りを１０％程度向上させることができた。In the case where the silicon oxide film 30 is used as a layer having good adhesion to the polysilicon 20 and the photoresist 40 as described above, it is possible to almost prevent side etching of the polysilicon, thereby improving the yield. We were able to improve this by about 10%.
（へ）効果
この発明は、所定のカフドパターンが形成されるホトレ
ジストとパターンニングされるポリシリコンとの間にこ
れらとそれぞれ密着性の良好な層を介在させ、前記ホト
レジストをマスクとして前記層およびポリシリコンを順
次エツチングさせている。つまり前記層がポリシリコン
およびホトレジストにそれぞれ良好に密着しているから
、各界面へのエツチング剤の回り込みを殆どなくし、ポ
リシリコンのサイドエツチングの発生を最小に抑えた。(F) Effect This invention provides a method of interposing a layer having good adhesion between the photoresist on which a predetermined cuffed pattern is formed and the polysilicon to be patterned, and using the photoresist as a mask to connect the layer and the polysilicon. are etched sequentially. In other words, since the layer adheres well to the polysilicon and the photoresist, the etching agent hardly flows around to each interface, and the occurrence of side etching of the polysilicon is minimized.
従って、＠細なパターンの形成を可能とする結果、寸法
のバラツキを安定させると共に歩留りを向上せしめた。Therefore, it is possible to form fine patterns, thereby stabilizing dimensional variations and improving yield.
第１図はこの発明に係るポリシリコンのエツチング方法
の一実施例を説明するための参考図、第２図は従来方法
において発生したポリシリコンのサイドエツチング状態
を示す説明図であり、第１図と同一部分は同一符合を付
している。
１０・・・半導体基板、２０・・・ポリシリコン、３０
・・・シリコン酸化膜、４０・・・ホトレジスト。FIG. 1 is a reference diagram for explaining an embodiment of the polysilicon etching method according to the present invention, and FIG. 2 is an explanatory diagram showing the state of side etching of polysilicon that occurs in the conventional method. The same parts are given the same reference numerals. 10... Semiconductor substrate, 20... Polysilicon, 30
...Silicon oxide film, 40...Photoresist.
Claims (2)
前記ポリシリコンおよびこれのマスクとなるホトレジス
トにそれぞれ良好な密着性を有する層を前記ポリシリコ
ンの上部に形成させる工程と、前記層の上部に前記ポリ
シリコンをエッチングするためのマスクとなるホトレジ
ストを被着させる工程と、 前記ホトレジストに所望のカットパターンを形成し、こ
のホトレジストをマスクとして前記層およびポリシリコ
ンを順次エッチングさせる工程とを具備したことを特徴
とするポリシリコンのエッチング方法。(1) After forming polysilicon on the surface of the semiconductor substrate,
A step of forming a layer having good adhesion to the polysilicon and a photoresist serving as a mask for the polysilicon on top of the polysilicon, and coating a photoresist serving as a mask for etching the polysilicon on top of the layer. A method for etching polysilicon, comprising the steps of forming a desired cut pattern on the photoresist and sequentially etching the layer and polysilicon using the photoresist as a mask.
とを特徴とする特許請求の範囲第１項記載のポリシリコ
ンのエッチング方法。(2) The polysilicon etching method according to claim 1, wherein the layer is made of a silicon oxide film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23619984A JPS61113237A (en) | 1984-11-08 | 1984-11-08 | Method for etching polysilicon |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23619984A JPS61113237A (en) | 1984-11-08 | 1984-11-08 | Method for etching polysilicon |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61113237A true JPS61113237A (en) | 1986-05-31 |
Family
ID=16997245
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23619984A Pending JPS61113237A (en) | 1984-11-08 | 1984-11-08 | Method for etching polysilicon |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61113237A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS529353A (en) * | 1975-07-11 | 1977-01-24 | Matsushita Electric Ind Co Ltd | Solid-state oscillator |
| JPS58110044A (en) * | 1981-12-23 | 1983-06-30 | Nec Corp | Pattern formation |
-
1984
- 1984-11-08 JP JP23619984A patent/JPS61113237A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS529353A (en) * | 1975-07-11 | 1977-01-24 | Matsushita Electric Ind Co Ltd | Solid-state oscillator |
| JPS58110044A (en) * | 1981-12-23 | 1983-06-30 | Nec Corp | Pattern formation |
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