JPS5916335A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS5916335A JPS5916335A JP12641682A JP12641682A JPS5916335A JP S5916335 A JPS5916335 A JP S5916335A JP 12641682 A JP12641682 A JP 12641682A JP 12641682 A JP12641682 A JP 12641682A JP S5916335 A JPS5916335 A JP S5916335A
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- oxide film
- photo resist
- substrate
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000004065 semiconductor Substances 0.000 title claims description 8
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 29
- 238000000034 method Methods 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 15
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 15
- 238000005530 etching Methods 0.000 claims description 7
- 239000000853 adhesive Substances 0.000 claims 1
- 230000001070 adhesive effect Effects 0.000 claims 1
- 239000000178 monomer Substances 0.000 claims 1
- 238000011282 treatment Methods 0.000 abstract description 9
- 230000018109 developmental process Effects 0.000 abstract description 3
- 230000007261 regionalization Effects 0.000 abstract description 2
- 238000009792 diffusion process Methods 0.000 description 7
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 239000004020 conductor Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000008094 contradictory effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Weting (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は高周波トランジスタ等を製造する上で半導体基
板上のシリコノ酸化膜にシャープな−ＩＩ（１１壁を有
する開孔と、ゆるやかな傾斜を有する開孔とを同時に設
けることができるず導体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention provides a method for manufacturing high-frequency transistors, etc. by simultaneously providing an opening having a sharp -II (11 wall) and an opening having a gentle slope in a silicon oxide film on a semiconductor substrate. The present invention relates to a method of manufacturing a conductor device.
メツシーエミッタのような高精度な拡散を必要とする領
域は微小寸法のシャープな窓の開孔を形成し、一方、ベ
ースコンタクト拡散のように、ベース−コレクタ接合を
覆う部分の基板表面上の酸化膜が厚く、この部分の酸化
膜にはゆるやかな傾斜側壁の窓を穿設したいという相反
する要求を持つ半導体装置を高品質に製造することは困
難であった。Areas that require high-precision diffusion, such as mesh emitters, form sharp window openings with minute dimensions, while areas that require highly precise diffusion, such as base contact diffusion, are formed on the substrate surface in areas covering the base-collector junction. It has been difficult to manufacture high-quality semiconductor devices with contradictory requirements such as thick oxide films and the need to form windows with gently sloping side walls in this portion of the oxide film.
半導体装置の製造に除して半導体板上に不純物拡散のマ
スクとなるシリコノ酸化膜の不純物拡散をしようとする
部分のノリコン酸化膜を食刻法にて開孔する事はよく知
られるところである。ところで、酸化膜の窓全シャーグ
に開孔する際にノリコン酸化膜と密着力の強いフォトレ
ジスト用いられ、通常ネガティブタイプフォトレジスト
がこの用途に適しており、多く使われていた。It is well known that in the manufacture of semiconductor devices, holes are formed by etching in the silicon oxide film, which serves as a mask for impurity diffusion, on the semiconductor board in the area where the impurity is to be diffused. By the way, when opening the entire window of the oxide film, a photoresist with strong adhesion to the Noricon oxide film is used, and a negative type photoresist is usually suitable for this purpose and is often used.
ところが、７ヤーグにエツチングされると、そののちの
電極配線を施した時に電極の段切れが発生し、半導体装
置の歩留の低下や、信頼性をおとすことになる。一方、
ゆるやかな傾斜に開孔するにはシリコン酸化膜に対して
密着力の低いフォトレジストを用い、いわゆるア／ダー
カットエツチングが行なわれるようにするのが好ましい
。しかしこの場合はパターン精度が悪くなる欠点を有す
る。However, if etched to 7 years, the electrodes will break when electrode wiring is applied, resulting in lower yields and lower reliability of semiconductor devices. on the other hand,
In order to form holes with a gentle slope, it is preferable to use a photoresist that has low adhesion to the silicon oxide film and to perform so-called up/under cut etching. However, this case has the disadvantage of poor pattern accuracy.
本発明は上記欠点にかんがみなされたもので、本発明は
高精度な拡散を必要とする領域には先ず第１のネガティ
ブタイプフォトレジストを堵導体基板上のシリコン酸化
膜に塗布し、所定のパターンの描かれたマスクをこのフ
ォトレジスト被膜上に配してフォトレジスト被膜を露光
し、引きつづいて現像処理を施し、さらにフォトレジス
トに対する焼付処理をなすことによって、マスクに描か
れたパターンと同一形状の開孔をこの第１のレジスト被
膜に穿設し、そののちゆるやかな傾斜を穿設する領域に
密着力の弱い第２のフォトレジスト（例えばポジティブ
タイプフォトレジスト）をシリコン酸化膜上ならびに前
記第１の工程により形成されたパターン上に塗布し、通
常の露光、現像焼付処理を施してゆるやかな傾斜をつけ
だい領域のみのパターンをこの第２のレジスト被膜に穿
設するところに特徴がある。これによれば、通常の食刻
法にて弗酸：弗化アンモニウム混合液で７リコン酸化膜
をエツチングする事により、密着力の強い第１のレジス
ト被膜をマスクとしたところは非常にシャープな開孔を
行ない、また密着力の弱い第２のレジスト被膜をマスク
としたところ（はゆるやかな傾斜のついたシリコン酸化
膜懇の開孔を行なうことが出来電極配線を施した際にゆ
るやかな傾余（１部を帆んで′電極ｊ脅を設けることに
より、電極の段切れがなく、高精度かつ高品質の生導体
装置を製造出来る。The present invention was developed in view of the above-mentioned drawbacks, and in the present invention, a first negative type photoresist is first applied to a silicon oxide film on a conductive substrate in a region that requires highly accurate diffusion, and a predetermined pattern is applied. A mask with a pattern drawn on it is placed on the photoresist film, the photoresist film is exposed to light, then developed, and then the photoresist is subjected to a baking process to form a pattern that is identical to the pattern drawn on the mask. holes are formed in this first resist film, and then a second photoresist with weak adhesion (for example, a positive type photoresist) is applied on the silicon oxide film and in the region where the gentle slope is to be formed. The second resist film is characterized in that it is coated on the pattern formed in step 1, subjected to normal exposure, development and baking treatments to form a gentle slope, and then a pattern only in the region is punched in the second resist film. According to this, by etching the 7-licon oxide film with a hydrofluoric acid/ammonium fluoride mixture using a normal etching method, the areas where the first resist film with strong adhesion was used as a mask became very sharp. When opening holes and using the second resist film, which has weak adhesion, as a mask, it was possible to open holes in the silicon oxide film with a gentle slope, resulting in a gentle slope when wiring the electrodes. By removing the remaining part and providing an electrode, a high-precision, high-quality live conductor device can be manufactured without cutting off the electrode.
以下本発明について実施例を挙げて具体的に説明する。The present invention will be specifically described below with reference to Examples.
第１図〜第９図は本発明に係る生導体装置の製造方法を
示す工程断面図である。まず第１図で示すようにＮ型シ
リコン基板１上にシリコン酸化膜２を形成する。次いで
、第２図で示すようにシリコン酸化膜２上衝着姓の高い
ネガティブタイプフォトレジスト被膜９を形成する。な
おこのフォトレジスト９は例えば市販されている商品名
ＫＭＲ７４７である。以上の処理を経てシリコン酸化膜
２上にフォトレジスト被膜９が形成されたノリコン基板
１にプリベーク処理を施す。この処理ののち第３図で示
すように所定のパターンが描かれたマスク１０をシリコ
ン基板１土に配置したのちフォトレジスト被膜９を露光
する。次いて現像処理を施すことによりフォトレジスト
被〕摸９には第４図で示すように第１のパターンが所定
のマスクツクターンと相似形の孔が穿設される。そのの
ち焼付処理を施す。かかる処理工程を経たノリコン基板
１に対し、第２のパターンを形成するわけである。1 to 9 are process cross-sectional views showing a method for manufacturing a live conductor device according to the present invention. First, as shown in FIG. 1, a silicon oxide film 2 is formed on an N-type silicon substrate 1. Next, as shown in FIG. 2, a negative type photoresist film 9 with high adhesion is formed on the silicon oxide film 2. Note that this photoresist 9 is, for example, a commercially available product name KMR747. After the above-described processes, the Noricon substrate 1 on which the photoresist film 9 has been formed on the silicon oxide film 2 is subjected to a pre-baking process. After this treatment, as shown in FIG. 3, a mask 10 with a predetermined pattern drawn thereon is placed on the silicon substrate 1, and then the photoresist film 9 is exposed. Next, by performing a development process, holes are formed in the photoresist pattern 9 in a shape similar to the first pattern of the predetermined mask pattern, as shown in FIG. After that, a baking treatment is applied. A second pattern is formed on the Noricon substrate 1 that has undergone such processing steps.
この工程は上記説明した第１のパターン形成と同じだが
第１のパターンを施した後、第５図に示すように密着力
の弱いフォトレジスト例えば市販されているノボラック
系のポジテンプタイプの７オトレジスト１１を形成する
。次いでグリベーク処理を施し、この処理ののち第６図
に示すように所定のパターンの描かれたマスク１２をシ
リコン基板上に配したのちフォトレジスト被膜１１を露
光し、現像処ＦＪ！ ’！＜施し第７図に示すようにフ
ォトレジスト被膜１１に第２のパターンとして、所定の
マスクパターンと相似形の孔を穿設し、さらに、焼付処
理を施す。次いて第８図に示すように通常の弗酸と弗化
アンモニウムの混合液で／リコン酸化膜をエツチングす
ると密着力の強いフォトレジスト９（ネガティブタイプ
フォトレジスト）をマスクとした部分はシャープな形状
のエツチングができ、密着力の弱いフォトレジスト１１
（ポジティタイプフォトレジスト）をマスクとした部分
はゆるやかな傾斜の酸化膜の窓が同時エツチングにおい
て開孔出来る。第９図は以上の食刻処理を施したのちノ
リコン基板上のフォトレジスト被膜９゜１１を除去し、
ｐ型不純物拡散３を施した状態を示す図である。This process is the same as the first pattern formation described above, but after forming the first pattern, as shown in FIG. 11 is formed. Next, a Gribake process is performed, and after this process, a mask 12 with a predetermined pattern drawn thereon is placed on the silicon substrate as shown in FIG. '! <Processing> As shown in FIG. 7, holes similar in shape to a predetermined mask pattern are formed in the photoresist film 11 as a second pattern, and then a baking process is performed. Next, as shown in Fig. 8, when the silicon oxide film is etched with a mixture of ordinary hydrofluoric acid and ammonium fluoride, the part masked with photoresist 9 (negative type photoresist), which has strong adhesion, has a sharp shape. Photoresist 11 that can be etched and has weak adhesion
In the area using (positive type photoresist) as a mask, a gently sloped oxide film window can be opened by simultaneous etching. Figure 9 shows that after the above etching process, the photoresist film 9°11 on the Noricon substrate is removed.
FIG. 3 is a diagram showing a state in which p-type impurity diffusion 3 has been performed.
以上の様に、本実施例によれば開口部の傾斜のゆるやか
な部分と急山１な部分とを有するシリコン酸化膜を同時
形成することが可能となる。従って開口部のｌ＠、４な
部分を用いて高精度拡散を行うことが出来、また開口部
のゆるやかな部分上に形成される電極配線の段切れをな
くすことが出来る。As described above, according to this embodiment, it is possible to simultaneously form a silicon oxide film having a gently sloped opening portion and a steeply sloped portion. Therefore, high-precision diffusion can be performed using the 1@, 4 portion of the opening, and it is possible to eliminate steps in the electrode wiring formed on the gentle portion of the opening.
以上の様に、本発明によれば大規模集積回路の歩留り、
品質向上をはかることが出来る。As described above, according to the present invention, the yield of large-scale integrated circuits,
Quality can be improved.
第１図〜第９図は本発明に係る生導体装置の製造方法を
示す工程断面図である。
２・・・・・・シリコン酸化膜、９・・・・・・ネガテ
ィブフォトレジスト、１１・・・・・・ポジティブフォ
トレジスト。
代理人の氏名 弁理士 中 屋敷 男 ほか１名第１図
７図
第９図1 to 9 are process cross-sectional views showing a method for manufacturing a live conductor device according to the present invention. 2...Silicon oxide film, 9...Negative photoresist, 11...Positive photoresist. Name of agent: Patent attorney Naka Yashiki, and 1 other person Figure 1 Figure 7 Figure 9
Claims (1)
コン酸化膜上に高密着性のレジスト被膜の第１のパター
ンを形成する工程、前記シリコン酸化膜上に前記高密着
性のレジスト破膜より低密着性のレジスト被膜の第２の
パター７を形成する工程、前ＮＬ第１と第２のパターン
をマスクとして前記シリコン酸化１換の食刻を行なう工
程をそなえたことを特徴とする半導体装置の製造方法。forming a silicon oxide film on the semiconductor substrate; forming a first pattern of a highly adhesive resist film on the silicon oxide film; manufacturing a semiconductor device, comprising the steps of: forming a second pattern 7 of a photoresist film; and etching the silicon oxide monomer using the first and second NL patterns as masks. Method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12641682A JPS5916335A (en) | 1982-07-19 | 1982-07-19 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12641682A JPS5916335A (en) | 1982-07-19 | 1982-07-19 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5916335A true JPS5916335A (en) | 1984-01-27 |
Family
ID=14934623
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12641682A Pending JPS5916335A (en) | 1982-07-19 | 1982-07-19 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5916335A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH033667U (en) * | 1989-05-30 | 1991-01-16 |
-
1982
- 1982-07-19 JP JP12641682A patent/JPS5916335A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH033667U (en) * | 1989-05-30 | 1991-01-16 |
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