JPS595631A - Mesa type semiconductor device and manufacture thereof - Google Patents

Mesa type semiconductor device and manufacture thereof

Info

Publication number
JPS595631A
JPS595631A JP57114854A JP11485482A JPS595631A JP S595631 A JPS595631 A JP S595631A JP 57114854 A JP57114854 A JP 57114854A JP 11485482 A JP11485482 A JP 11485482A JP S595631 A JPS595631 A JP S595631A
Authority
JP
Japan
Prior art keywords
groove
section
semiconductor substrate
forming
coating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57114854A
Other languages
Japanese (ja)
Inventor
Tsuneo Yamaguchi
恒夫 山口
Takeshi Umegaki
梅垣 武士
Yorisada Kawakami
川上 頼貞
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp, Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electronics Corp
Priority to JP57114854A priority Critical patent/JPS595631A/en
Publication of JPS595631A publication Critical patent/JPS595631A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To eliminate an adverse effect such as an application unevenness on processes by forming the side wall section of a groove in two-stage structure and forming a porjecting coating section, around which glass fines round, into the lower groove from the surface of a substrate. CONSTITUTION:A window l2 for etching in relationship narrower than the width l1 of an opening window is formed to a groove section 4 in a corrosion-resisting film 7 on a novel oxide film 3' coating the semiconductor substrate 1 through heat treatment. A second groove 4' penetrating a P-N junction in depth deeper than the groove section 4 is formed in two-stage structure through etching through window l2. A glass coating 5 is applied and formed to the groove section 4' through an electrophoresis method. A projecting section 6 is formed at the top section of the end of the groove section of the glass coating 5 through baking treatment, but there is the projecting section in the surface of a surface region low by one stage, the section can be formed so that it is not projected to the flat surface of the semiconductor substrate 1, and it does not hinder a mask process.

Description

【発明の詳細な説明】 本発明は、メサ側壁を2段構造になしたメサ型半導体装
置及びその製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a mesa-type semiconductor device having a two-tiered mesa sidewall structure and a method for manufacturing the same.

メサ型半導体装置は衆知の如くメサエッチングによって
形成された溝部側壁にPN接合部が露呈しており通常こ
の側壁を含む溝部には表面安定化被膜が被着形成され、
これによってメサ型半導体装置の特性を安定化している
。かかる表面安定化被膜の形成方法に、硅酸ガラスの微
粉末をアルコール等の有機溶剤中へ懸濁しこれに電解液
として弗酸あるいはアンモニア水を微量添加してなる懸
濁液中でガラス微粉末を電気泳動させて半導体基板の溝
部へ被着する電気泳動法が利用される。
As is well known, in a mesa type semiconductor device, a PN junction is exposed on the sidewall of a groove formed by mesa etching, and a surface stabilizing film is usually formed on the groove including this sidewall.
This stabilizes the characteristics of the mesa semiconductor device. In a method for forming such a surface stabilizing film, fine glass powder is suspended in an organic solvent such as alcohol, and a small amount of hydrofluoric acid or aqueous ammonia is added as an electrolyte. An electrophoresis method is used in which the material is electrophoresed and deposited on the groove portion of the semiconductor substrate.

第1図はかかる電気泳動法によりガラス被膜が溝部に被
着形成された従来のメサ構造を有する半導体基板の断面
図である。
FIG. 1 is a sectional view of a conventional semiconductor substrate having a mesa structure in which a glass film is deposited in a groove by such electrophoresis.

図中、1はシリコン基板部、2は前記基板部1と内部で
PN接合を形成する表面領域、3は同半導体基板上を覆
う酸化膜(5iO2)、 4はメサエッチングにより形
成した溝、そして6は溝部に被着形成されたガラス被膜
である。
In the figure, 1 is a silicon substrate part, 2 is a surface region forming a PN junction with the substrate part 1, 3 is an oxide film (5iO2) covering the semiconductor substrate, 4 is a groove formed by mesa etching, and 6 is a glass coating formed on the groove portion.

ところで電気泳動法ではガラス微粉末被着のマスクとな
る酸化膜3の端が露呈する半導体基体面と接していると
ガラス微粉末被着のまわり込み現象が起り酸化膜3の上
にも被着し突起部6が形成される。この突起部6はその
後電極形成時のマスクとなるホトレジスト膜の塗布むら
を起こす原因となるのみならず電極パターン形成のだめ
のマスクと半導体基板の相互間隔を保持する上でもこれ
を損う原因となる、等の問題が多かった。
By the way, in the electrophoresis method, if the edge of the oxide film 3, which serves as a mask for the deposition of fine glass powder, is in contact with the exposed semiconductor substrate surface, a wrapping phenomenon of the deposition of fine glass powder occurs, causing the deposition of fine glass powder onto the oxide film 3 as well. A protrusion 6 is formed. These protrusions 6 not only cause uneven coating of the photoresist film that will serve as a mask during electrode formation, but also impair the ability to maintain the mutual distance between the mask used for electrode pattern formation and the semiconductor substrate. There were many problems such as.

本発明は、電気泳動法により溝部へガラス被膜を被着形
成するにあたりガラス微粉末被着のまわり込み現象によ
り生じる突起部がその後の工程に及ぼす塗布むら等の悪
影響を皆無にする事が出来るメサ型半導体装置及びその
製造方法を提供するものである。すなわち本発明は溝側
壁部を2段構造となしガラス微粉末のまわり込み突起被
着部を基板表面から下位の溝内部に形成するようにした
ものである。
The present invention provides a mesa that can eliminate any adverse effects such as uneven coating on subsequent processes caused by protrusions caused by the wrapping phenomenon of fine glass powder when depositing a glass film on a groove by electrophoresis. The present invention provides a type semiconductor device and a method for manufacturing the same. That is, in the present invention, the groove side wall portion has a two-stage structure, and the part where the fine glass powder wraps around and adheres to the protrusion is formed inside the groove below the substrate surface.

以下、第2図を参照して本発明のメサ型半導体装置の製
造方法を詳しく説明する。
Hereinafter, the method for manufacturing a mesa-type semiconductor device of the present invention will be explained in detail with reference to FIG.

第2図、(a)〜(C)は本発明の方法によりガラス被
膜を溝部に被着形成する主要な処理過程を示す工程図で
あり先づ半導体基板1とPN接合を形成する表面領域2
に、酸化膜3を形成し、この酸化膜3にメサエッチング
用窓4を開口し、エツチング処理を施して、前記表面領
域2に、PN接合部を貫かない程度に比較的浅い第1の
溝4、を形成する(第2図(a))。その後、酸化膜3
を除去し、ついで、衆知の熱処理にて半導体基板1を覆
う新たな酸化膜3′を形成し前記酸化膜3′上にホトレ
ジスト等の耐食性被膜7に前記開口窓幅石より狭い関係
のエツチング用窓12を前記溝部4に形成する(第2図
(1)) ) oこの窓12を通してエツチングを行な
い溝部4よりも深(PN接合部を1貫く第2の溝4′を
形成し、溝部が浅い淵を有する。いわゆる2段構造にな
るように形成する。しかるのち前述した電気泳動法によ
りガラス被膜6をこの溝部4′に被着形成する(第2図
(0) ) 、)ガラス被膜を被着形成後焼付処理を施
すと従来のようにガラス被膜5の溝部端の頂部に突起部
6が形成されているが、この部分は、一段低い表面領域
面にあり、半導体基板1の平坦な表面には突出しないよ
うにすることが可能であり、したがって、これが、その
後のマスク工程の支障になることはない。
2, (a) to (C) are process diagrams showing the main processing steps for depositing and forming a glass film in a groove by the method of the present invention. First, the surface area 2 where a PN junction is formed with the semiconductor substrate 1
Then, an oxide film 3 is formed, a mesa etching window 4 is opened in the oxide film 3, and an etching process is performed to form a relatively shallow first trench in the surface region 2 to the extent that it does not penetrate the PN junction. 4 (Fig. 2(a)). After that, oxide film 3
Then, a new oxide film 3' is formed to cover the semiconductor substrate 1 by well-known heat treatment, and a corrosion-resistant coating 7 such as photoresist is applied on the oxide film 3' to form an etching film narrower than the width of the opening window. A window 12 is formed in the groove 4 (Fig. 2 (1)) o Etching is performed through this window 12 to form a second groove 4' deeper than the groove 4 (a second groove 4' passing through the PN junction part). It has a shallow depth.It is formed to have a so-called two-stage structure.Then, the glass coating 6 is deposited on this groove 4' by the electrophoresis method described above (FIG. 2 (0)). When the baking process is performed after the adhesion is formed, a protrusion 6 is formed at the top of the groove end of the glass coating 5 as in the conventional case. It is possible that the surface does not protrude, so that this does not interfere with the subsequent masking process.

以下に第2図に示す本発明の実施態様例を説明する。表
面が酸化膜3で覆われたシリコン基板1の表面領域2上
にホトレジスト膜7を約10pmの厚みで塗布したのち
、このホトレジスト膜7に260μmの窓幅(11)を
もつエツチング用窓を形成するとともにこの窓内の酸化
膜を除去し次いで弗酸、硝酸、酢酸を容量比で1.rs
 : 7 : 1.5の割合いで混合してなるエツチン
グ液中へ半導体基板を浸漬することにより深さがPN接
合部を貫かない溝4を形成する。
An embodiment of the present invention shown in FIG. 2 will be described below. After applying a photoresist film 7 to a thickness of about 10 pm on the surface region 2 of the silicon substrate 1 whose surface is covered with an oxide film 3, an etching window having a window width (11) of 260 μm is formed on this photoresist film 7. At the same time, the oxide film inside this window was removed, and then hydrofluoric acid, nitric acid, and acetic acid were added in a volume ratio of 1. rs
By immersing the semiconductor substrate in an etching solution mixed at a ratio of: 7: 1.5, a groove 4 whose depth does not penetrate the PN junction is formed.

かかるエツチング処理を施した後、ホトレジスト膜を除
去し、さらに、酸化膜3を除去し、しかるのち熱処理を
施し半導体基板を再び、新たな酸化膜3にて覆い、さら
に、ホトレジストを16//mの厚みで塗布し前記溝部
内に180//mの窓幅(42)をもつエツチング用窓
を形成するとともにこの窓内の酸化膜を除去し次いで弗
酸、硝酸、酢酸の容量比で3:6:2の割合いで混合し
てなるエツチング液にて処理しPM接合部を貫く溝4′
を形成し、溝形状を2段構造とする。かかる処理の施さ
れた半導体基板を、酸化鉛を主成分としたガラス微粉末
をアルコール中に懸濁させるとともに塩化アルミニウム
を電解質として添加してなる処理液にて。
After performing such etching treatment, the photoresist film is removed, and then the oxide film 3 is removed, and then heat treatment is performed to cover the semiconductor substrate again with a new oxide film 3, and the photoresist is further removed by 16//m. An etching window with a window width (42) of 180//m was formed in the groove, and the oxide film within the window was removed. Grooves 4' passing through the PM joint are treated with an etching solution mixed at a ratio of 6:2.
, and the groove shape has a two-stage structure. The semiconductor substrate subjected to such treatment is treated with a treatment solution made by suspending fine glass powder mainly composed of lead oxide in alcohol and adding aluminum chloride as an electrolyte.

20Vの電圧を30秒間印加することによりガラス微粉
末に電気泳動を生じさせ、約16μmの厚さのガラス被
膜6を形成する。ガラス被膜6の被膜形成は浅い溝部で
突起部6が発生しているが平導体基板表面の酸化膜3′
から突出する迄は達していなかった。
By applying a voltage of 20 V for 30 seconds, electrophoresis is caused in the glass fine powder to form a glass coating 6 with a thickness of about 16 μm. The glass film 6 is formed with protrusions 6 in shallow grooves, but the oxide film 3' on the surface of the flat conductor substrate
It had not reached the point where it was protruding from the surface.

以上の説明から明らかなように、本発明による2段構造
の溝を有するメサ型半導体装置は電気泳動法によりガラ
ス被膜を形成する場合に問題となるガラス微粉末被着の
まわり込み現象実質的に排除出来るので、レジストの塗
布むら、マスク不良等の問題がなくなる効果を有する0
As is clear from the above description, the mesa semiconductor device having the two-stage groove structure according to the present invention substantially eliminates the wrap-around phenomenon of fine glass powder adhering, which is a problem when forming a glass film by electrophoresis. Since it can be eliminated, it has the effect of eliminating problems such as uneven resist coating and mask defects.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、従来構造の溝部に電気泳動法によりガラス被
膜の被着形成がなされた半導体基板の断面図、第2図(
a)〜(C)は、本発明の2段構造の溝に於けるガラス
被膜の形成方法を説明するための処理工程図である0 1・・・・・・半導体基板、2・・・・・・表面領域、
3.3′・・・・・・酸化膜、4.4’・・・・・・エ
ッチ溝、6・・・・・ガラス被膜、6・・・・・・突起
部、7・・・・・・ホトレジスト。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名第1
Figure 1 is a cross-sectional view of a semiconductor substrate in which a glass film has been deposited in the groove of a conventional structure by electrophoresis, and Figure 2 (
a) to (C) are processing process diagrams for explaining the method of forming a glass coating in a two-stage groove of the present invention.01...Semiconductor substrate,2...・Surface area,
3.3'...Oxide film, 4.4'...Etched groove, 6...Glass coating, 6...Protrusion, 7... ...Photoresist. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
figure

Claims (2)

【特許請求の範囲】[Claims] (1)PN接合面を有する半導体基板と、前記半導体基
板表面に前記PN接合面より浅い第1の溝部と、前記第
1の溝部内に形成されかつ前記PM接合面を貫く第2の
溝部と、前記第1の溝部から前記第2の溝部にわたって
形成されたガラス被膜とを有することを特徴とするメサ
型半導体装置。
(1) A semiconductor substrate having a PN junction surface, a first groove shallower than the PN junction surface on the surface of the semiconductor substrate, and a second groove formed in the first groove and penetrating the PM junction surface; and a glass coating formed from the first groove to the second groove.
(2)PN接合面を有する半導体基板上を覆う第1の絶
縁膜に第1の開口を形成し、前記第1の開口をマスクと
して前記PN接合面より浅い第1の溝を形成する工程と
、第2の絶縁膜を形成し、前記第1の溝内の前記第2の
絶縁膜に第2の開口を形成し、前記第2の開口を通して
前記PN接合面より深い第2の溝を形成する工程と、電
気泳動法により前記第1及び第2の溝部にガラス被膜を
形成する工程とを含むことを特徴とするメサ型半導体装
置の製造方法。
(2) forming a first opening in a first insulating film covering a semiconductor substrate having a PN junction surface, and using the first opening as a mask to form a first groove shallower than the PN junction surface; , forming a second insulating film, forming a second opening in the second insulating film within the first trench, and forming a second trench deeper than the PN junction surface through the second opening; A method for manufacturing a mesa-type semiconductor device, comprising the steps of: forming a glass film on the first and second groove portions by electrophoresis.
JP57114854A 1982-07-01 1982-07-01 Mesa type semiconductor device and manufacture thereof Pending JPS595631A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57114854A JPS595631A (en) 1982-07-01 1982-07-01 Mesa type semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57114854A JPS595631A (en) 1982-07-01 1982-07-01 Mesa type semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPS595631A true JPS595631A (en) 1984-01-12

Family

ID=14648358

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57114854A Pending JPS595631A (en) 1982-07-01 1982-07-01 Mesa type semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS595631A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009019358A (en) * 2007-07-10 2009-01-29 Hitachi Plant Technologies Ltd Automatic dust collector
JP2014175389A (en) * 2013-03-07 2014-09-22 Mitsubishi Materials Corp Method of forming alumina insulation film

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009019358A (en) * 2007-07-10 2009-01-29 Hitachi Plant Technologies Ltd Automatic dust collector
JP2014175389A (en) * 2013-03-07 2014-09-22 Mitsubishi Materials Corp Method of forming alumina insulation film

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