JPS5944832A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS5944832A JPS5944832A JP57154913A JP15491382A JPS5944832A JP S5944832 A JPS5944832 A JP S5944832A JP 57154913 A JP57154913 A JP 57154913A JP 15491382 A JP15491382 A JP 15491382A JP S5944832 A JPS5944832 A JP S5944832A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- glass
- substrate
- junction
- thermal oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、ＰＮ接合の接合端露出面をガラスパッシベー
ション膜により保護する半導体装置の製造方法に関する
。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device in which an exposed surface of a PN junction is protected by a glass passivation film.
半導体装置のＰＮ接合端露出面を保護するために、ガラ
ス微粉末懸濁液を用いて電気線＋ＩＩＩＪ法Ｖこよシ該
ガラス微粉末を１） Ｎ接合端露出面に付着σせ、パッ
シベーション膜としてのガラス絶縁膜を形成していたが
、この際、半導体基（１゛の六面を保りしている熱酸化
膜の上にもわずかながらガラス微粒子が残り、前記熱酸
化膜に電極形成のｔめの窓あけエツチングを行う場合、
前記ガ゛）ス偉粒子がマスクと２（って、このエツチン
グを妨げると（八つ欠点があった。In order to protect the exposed surface of the PN junction end of a semiconductor device, a suspension of glass fine powder is applied using an electric wire + IIIJ method. However, at this time, a small amount of glass particles remained on the thermal oxide film that maintains the six sides of the semiconductor substrate (1゛), and when electrodes were formed on the thermal oxide film, When etching the tth window,
If the gas particles interfere with this etching, there are two drawbacks.
本発明の目的は、前記のガラス微粒子による欝あけエツ
チングの障害なしに窓あけを可能とした半導体装置の製
造方法を提供するにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that enables window opening without the above-mentioned hindrance caused by the glass particles.
本発明の方法は、ＰＮ接合を有し、かつ、表面が熱酸化
膜に上り波われた半導体基板の前記熱酸化膜の上にＣＶ
Ｄ酸化膜を形成する工程と、つきに前記ＰＮ接合の接合
端を露出させこの露出面にガラス微粉末懸濁液を用いて
電気泳！！ｌＩＩ法によりガラスパッシベーション膜を
形成する工程と、つきに前記基板表面の所定部分のＣＶ
Ｄ酸化膜および熱酸化膜を除安し、この除去部分ＶＣ
＜極を形成する工程とを含む構成を有する。In the method of the present invention, CV
In the process of forming a D oxide film, the bonding end of the PN junction is exposed and electrophoresis is performed using a glass fine powder suspension on this exposed surface. ! A step of forming a glass passivation film by the II method, and a CV of a predetermined portion of the substrate surface.
D oxide film and thermal oxide film are removed, and this removed portion VC
<It has a configuration including a step of forming a pole.
本発明方法では、熱酸化膜の上にＣＶＤ酸化膜を設け、
それからガラス付着をするのでこのＣＶｌ）酸化膜の上
にガラス微粒子が付着するのである。In the method of the present invention, a CVD oxide film is provided on the thermal oxide film,
Since glass is then deposited, glass fine particles are deposited on top of this CVl) oxide film.
そして、ｃ Ｖ Ｉ−）酸化膜はシリコン熱酸化膜に比
べてかなり低温で形成することができる反面、膜の質と
しては比較的粗く、弗酸系の処理で容易にエツチングさ
れる。捷た、横方向のエツチング艙’＋＋大きい１．シ
たがって、窓あけエツチングの際に、ガラス微粒子の陰
の部分のＣＶＤ酸化膜も容易にエツチングされるので、
熱酸化膜の場合のような障害を起すことが避けられる、
つぎに本発明や一実施例により説明ずろ。Although the cVI-) oxide film can be formed at a much lower temperature than a silicon thermal oxide film, it is relatively rough in quality and is easily etched by hydrofluoric acid treatment. Cut, horizontal etching bay'++ large 1. Therefore, during window etching, the CVD oxide film in the shadow part of the glass particles is also easily etched.
Next, the present invention and an embodiment will be explained.
第１図（ａ）ないしくｄ）は本発明の一実施例の製造工
程を説明するための断面図である。まず、第１図（ａ）
のように、２県シリコン基板１の元の基板層２と、上面
側に形成されたＮ型層３とによ＃）ＰＮ接合４が形成さ
れ、さらに、表面が熱酸化膜５で被われト半導体基板の
熱酸化膜５の上に、ＣＶ Ｄ酸化＋＋ｉｉ ６を形成す
る。つぎに同図（ｂ）のように、Ｉ） Ｎ接合４の接合
端を内面ｖｃ格出させるメサ溝７をフォトエツチングに
より形成し、このメサ溝７の内面に、ガラス微粉末の懸
濁液を用いて電気泳動法によりガラス微粉末を伺着させ
、焼成を行？、ことにより、メサ溝内前に、Ｉ） Ｎ接
合端を保護するガラスパッシベーション膜８を形成する
。この除、ＣＶＤ酸化膜６の上に僅かながら伺着したガ
ラス微粉末は共に焼成されてガラス微粒子体９としてＣ
Ｖ Ｉ）酸化膜６の上に残留する。ガラスパッシベーシ
ョン膜８け酸系の処理に対して弱いので、ｆ’ｉ）７処
理などの工程が入る場合に、第１図（Ｃ）のようＶＣ、
バッジベージぢン膜を保護す、５１ζめのｃ Ｖ Ｉ−
） （−）β化１１ｇ ｌ Ｑを基板表面全体に堆積さ
せた後、同図（（Ｉ）のように、フォトエツチングによ
り市、棒形成用窓１１をあける。このとき、ＣＶ Ｄ
ｔ’ｌ化膜６のヒのガラス微粒子体９ｖ、ｃｖｕ酸化・
（１λ６の横方向のエツチング効果により共に除去され
、ガラス０イ１′Ｊ。FIGS. 1(a) to 1(d) are cross-sectional views for explaining the manufacturing process of an embodiment of the present invention. First, Figure 1(a)
As shown, a PN junction 4 is formed between the original substrate layer 2 of the silicon substrate 1 and the N-type layer 3 formed on the upper surface side, and the surface is further covered with a thermal oxide film 5. A CVD oxidation ++ii 6 is formed on the thermal oxide film 5 of the semiconductor substrate. Next, as shown in FIG. 6(b), a mesa groove 7 is formed by photo-etching to bring the joint end of the N-junction 4 onto the inner surface VC, and a suspension of fine glass powder is applied to the inner surface of the mesa groove 7. Fine glass powder is deposited by electrophoresis and fired. In some cases, a glass passivation film 8 is formed in front of the mesa groove to protect the I)N junction end. Apart from this, a small amount of the glass fine powder that has arrived on the CVD oxide film 6 is fired together and becomes a glass fine particle body 9.
VI) Remains on the oxide film 6. Glass passivation film 8 is weak against silicic acid treatment, so when steps such as f'i) 7 treatment are included, VC, as shown in Figure 1 (C),
The 51ζth c VI- protects the badge-based membrane.
) (-) After depositing β-11glQ on the entire surface of the substrate, as shown in FIG.
Glass fine particles 9v of t'l oxidation film 6, cvu oxidation
(Both are removed by the lateral etching effect of 1λ6, and the glass 0i1'J.
子による障害のｌ【い電極形成の怒あけがなされる。In order to prevent damage caused by children, the formation of electrodes is caused.
続いて電極となる金属を基板表面に蒸着法など姓７より
形成し、フォトエツチングによって酸処理を施し付着ガ
ラス８を損傷することなく、第１図（ｄ）のような１ｇ
；極１２を形成する。Next, a metal that will become an electrode is formed on the surface of the substrate using a vapor deposition method or other method, and then an acid treatment is performed by photoetching to form a 1g layer as shown in FIG. 1(d) without damaging the attached glass 8.
; form the pole 12;
この結果、ガラス微粒ぞ−Ｖこよる損傷のない電極形成
面と、酸処理の困難で、Ｉ−１つたノ（ツシベーション
ガラスイマ１の半導体素子での微細金属エツチングパタ
ーンを得ることがｉｉＪ能となる。As a result, it is possible to obtain an electrode formation surface without damage caused by fine glass particles, and to obtain a fine metal etching pattern in a semiconductor element using Tsivation Glass Imer 1, which is difficult to perform with acid treatment. becomes.
第１図（ａ）ないしくｄ）は本発明の一実施例の型造工
程を説明するための工程順の断面図である。
１・・・・・・半畳体栽板、２・・・・・・基板層、３
・・・・・・Ｎ型層、４・・・・・・ＰＮ接合、訃・・
・・・熱酸化膜、６・・・・・・ＣＶｌ）酸化膜、７・
・・・・・メサ溝、８・・・・・・ガラスノ（シベーシ
ョン膜、９・・・・・・ガラス微粒子、１０・・・・・
・ガラス保循用ＣＶ Ｊ）酸化膜。
第１ 図FIGS. 1(a) to 1(d) are sectional views showing the order of steps for explaining the molding process of an embodiment of the present invention. 1...Semi-matted planting board, 2...Substrate layer, 3
...N-type layer, 4...PN junction, end...
...Thermal oxide film, 6...CVl) Oxide film, 7.
... Mesa groove, 8 ... Glass no. (scivation film, 9 ... Glass fine particles, 10 ...
・CV for glass preservation J) Oxide film. Figure 1
Claims (1)
半導体基板の前記熱酸化膜の上にＣＶ １）酸化膜音形
成する工程と、つぎに前記Ｐ Ｎ接合の接合端を露出さ
せ、この露出面にガラス微粉末懸濁液４−用いて鴫、気
泳動法によりガラスパッシベーションｉｌ；、％を形成
す４）工程と、つぎに前記基板表面の所定部分のＣＶＤ
酸化膜および熱酸化膜を除去し、この除去部分ＶＣ，１
ｆＬ極を形成する工程とを含むことを特徴とする半導体
装置の製造方法。1) Step of forming an oxide film on the thermal oxide film of a semiconductor substrate having a PN junction and whose surface is covered with a thermal oxide film, and then exposing the bonding end of the PN junction. Step 4) of forming a glass passivation film on this exposed surface using a glass fine powder suspension 4-% by pneumophoresis, and then CVD of a predetermined portion of the substrate surface.
The oxide film and the thermal oxide film are removed, and this removed portion VC,1
A method for manufacturing a semiconductor device, comprising the step of forming an fL pole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57154913A JPS5944832A (en) | 1982-09-06 | 1982-09-06 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57154913A JPS5944832A (en) | 1982-09-06 | 1982-09-06 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5944832A true JPS5944832A (en) | 1984-03-13 |
Family
ID=15594691
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57154913A Pending JPS5944832A (en) | 1982-09-06 | 1982-09-06 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5944832A (en) |
-
1982
- 1982-09-06 JP JP57154913A patent/JPS5944832A/en active Pending
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