JPH1056060A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH1056060A
JPH1056060A JP21071596A JP21071596A JPH1056060A JP H1056060 A JPH1056060 A JP H1056060A JP 21071596 A JP21071596 A JP 21071596A JP 21071596 A JP21071596 A JP 21071596A JP H1056060 A JPH1056060 A JP H1056060A
Authority
JP
Japan
Prior art keywords
insulating film
semiconductor device
pattern
film
solution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21071596A
Other languages
Japanese (ja)
Inventor
Yuichiro Taguma
祐一郎 田熊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP21071596A priority Critical patent/JPH1056060A/en
Publication of JPH1056060A publication Critical patent/JPH1056060A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To enable a conductor film to be formed at a low cost and high in throughput in a wiring pattern forming process by the use of damascene or the like. SOLUTION: A wiring insulating film 2 formed on a substrate 1 is formed into a recessed pattern 2a corresponding to a target wiring pattern or a plug through photolithography, a thin close contact layer 3 is formed thereon, a fluidic paste/solution 4 composed of organic solvent 4a and conductor fine particles 4b of copper (Cu) or the like suspended in it is applied onto all the surface of the wiring insulating film 2 (close contact layer 3), and then the substrate 1 is backed or burned under pressure, whereby a dense conductor film 4c is formed to cover the surface of the wiring insulating film 2 and surely fills the recessed pattern 2a. Thereafter, the conductor film 4c is removed flat through a CMP method or the like so as to make the surface of the wiring insulating film 2 exposed, whereby the conductor pattern 4d is selectively left inside the recessed pattern 2a to function as a wiring pattern or a plug or the like.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体装置の製造
技術に関し、特に、ダマシン法等による配線パターンや
プラグ等の形成工程に適用して有効な技術に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology for manufacturing a semiconductor device, and more particularly to a technology effective when applied to a process of forming a wiring pattern or a plug by a damascene method or the like.

【0002】[0002]

【従来の技術】たとえば、株式会社工業調査会、平成8
年5月1日発行、「電子材料」1996年5月号P22
〜P27、等の文献にも記載されているように、金属配
線パターンの形成プロセスの一つとして、ダマシン(da
mascene)法が知られている。すなわち、予め目的の配線
パターンまたはプラグの形状に合わせて溝または穴パタ
ーンが形成された下地絶縁膜上の全面に金属薄膜を形成
して、前記溝または穴パターンの内部に金属膜を埋め込
み、さらに、CMP(Chemical Mechanical Polishing
:化学的機械的研磨)等の技術によって、下地絶縁膜
を覆っている金属膜を平坦に除去して、当該下地絶縁膜
の表面を露出させ、前記溝または穴パターンの内部に金
属膜が選択的に残存するようにして、目的の形状の金属
配線パターンやプラグを得るものである。
2. Description of the Related Art For example, Industrial Research Co., Ltd., 1996
Published on May 1, 1996, Electronic Materials, May 1996, p. 22
To P27, etc., as one of the processes for forming a metal wiring pattern, a damascene (da
mascene) method is known. That is, a metal thin film is formed on the entire surface of the underlying insulating film on which the groove or hole pattern is formed in advance according to the shape of the target wiring pattern or plug, and the metal film is embedded in the groove or hole pattern. , CMP (Chemical Mechanical Polishing)
: Chemical mechanical polishing) or the like, the metal film covering the base insulating film is removed flat to expose the surface of the base insulating film, and a metal film is selected inside the groove or hole pattern. Thus, a metal wiring pattern or a plug having a desired shape is obtained so that the metal wiring pattern and the plug remain.

【0003】この、従来のダマシン法では、下地絶縁膜
における溝内への金属膜の埋め込み方法としてスパッタ
/リフロ法あるいはCVD法が用いられていた。
In the conventional damascene method, a sputter / reflow method or a CVD method has been used as a method for embedding a metal film in a groove in a base insulating film.

【0004】[0004]

【発明が解決しようとする課題】ところで、現状のスパ
ッタ/リフロ法の場合、埋め込み特性が比較的悪く、ま
たCVD法の場合には堆積速度が低くスループットを大
きくすることが困難である、という技術的課題がある。
さらに、上記のスパッタ/リフロ法あるいはCVD法を
実現するスパッタ装置やCVD装置等の設備はともに高
価である。特に、配線パターンの素材として、現状のア
ルミニウム等に代えて、より電気抵抗値の低い銅等を用
いる場合においては、これらの技術的課題は一層顕著に
なる。
However, in the case of the current sputtering / reflow method, the embedding characteristics are relatively poor, and in the case of the CVD method, the deposition rate is low and it is difficult to increase the throughput. Issues.
Further, equipment such as a sputtering apparatus and a CVD apparatus for realizing the above-mentioned sputtering / reflow method or CVD method are both expensive. In particular, in the case where copper or the like having a lower electric resistance value is used as the material of the wiring pattern instead of the current aluminum or the like, these technical problems become more remarkable.

【0005】本発明の目的は、導体膜の形成を伴う製造
工程の所要時間を短縮してスループットを向上させるこ
とが可能な半導体装置の製造技術を提供することにあ
る。
An object of the present invention is to provide a semiconductor device manufacturing technique capable of shortening the time required for a manufacturing process involving formation of a conductive film and improving the throughput.

【0006】本発明の他の目的は、絶縁膜に形成された
凹パターン内部への導体の埋め込みを確実に行うことが
可能な半導体装置の製造技術を提供することにある。
Another object of the present invention is to provide a semiconductor device manufacturing technique capable of reliably embedding a conductor into a concave pattern formed in an insulating film.

【0007】本発明の他の目的は、低設備コストにて、
導体膜の形成を伴う製造工程を構築および運用すること
が可能な半導体装置の製造技術を提供することにある。
[0007] Another object of the present invention is to reduce the equipment cost.
An object of the present invention is to provide a semiconductor device manufacturing technique capable of constructing and operating a manufacturing process involving formation of a conductor film.

【0008】本発明の他の目的は、低コストおよび高歩
留りで高信頼度の半導体装置を得ることが可能な半導体
装置の製造技術を提供することにある。
Another object of the present invention is to provide a semiconductor device manufacturing technique capable of obtaining a highly reliable semiconductor device at a low cost and a high yield.

【0009】本発明の前記ならびにその他の目的と新規
な特徴は、本明細書の記述および添付図面から明らかに
なるであろう。
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

【0010】[0010]

【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば、
以下のとおりである。
SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

【0011】本発明の半導体装置の製造方法は、任意の
溶媒に導体微粒子を懸濁させたペーストまたは溶液を絶
縁膜の表面に塗布し、このペーストまたは溶液に対し
て、加熱処理および加圧処理の少なくとも一方を施して
焼成することにより導体膜の形成を行うものである。
According to the method of manufacturing a semiconductor device of the present invention, a paste or solution in which conductive fine particles are suspended in an arbitrary solvent is applied to the surface of an insulating film, and the paste or solution is subjected to heat treatment and pressure treatment. The conductive film is formed by applying and firing at least one of the above.

【0012】また、ダマシン法等による導体パターンの
形成プロセスにおいて、目的のパターンに対応して絶縁
膜表面に形成された凹パターンへの導体膜の形成/埋め
込みを行う方法として、任意の溶媒に導体微粒子を懸濁
させたペーストまたは溶液を絶縁膜の表面に塗布して凹
パターンに充填し、このペーストまたは溶液に対して、
加熱処理および加圧処理の少なくとも一方を施して焼成
することにより導体膜とするものである。
In a process of forming a conductor pattern by a damascene method or the like, a method of forming / embedding a conductor film in a concave pattern formed on the surface of an insulating film corresponding to a target pattern has been proposed. A paste or solution in which fine particles are suspended is applied to the surface of the insulating film and filled into a concave pattern.
The conductor film is formed by performing at least one of a heat treatment and a pressure treatment and baking.

【0013】[0013]

【発明の実施の形態】以下、本発明の実施の形態を図面
を参照しながら詳細に説明する。
Embodiments of the present invention will be described below in detail with reference to the drawings.

【0014】図1の(a)〜(d)は、本発明の一実施
の形態である半導体装置の製造方法の一例を工程順に例
示した略断面図である。
FIGS. 1A to 1D are schematic sectional views illustrating an example of a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps.

【0015】本実施の形態では、一例として、半導体装
置の製造プロセスにおける、ダマシン法による配線パタ
ーンや導体プラグ等の形成工程に適用した場合について
説明する。
In the present embodiment, as an example, a case where the present invention is applied to a process of forming a wiring pattern, a conductor plug, and the like by a damascene method in a manufacturing process of a semiconductor device will be described.

【0016】まず、半導体ウェハ等の基板1の上に、た
とえば、酸化シリコン等からなる配線絶縁膜2を、たと
えばP−CVD法等により形成した後、通常の半導体プ
ロセスで一般に用いられているホトリソグラフィプロセ
スおよびドライエッチングプロセスにより、配線絶縁膜
2に将来、配線パターンやプラグ等の配線構造等を形成
する部分に、溝や穴等からなる凹パターン2aを形成す
る。
First, a wiring insulating film 2 made of, for example, silicon oxide or the like is formed on a substrate 1 such as a semiconductor wafer by, for example, a P-CVD method or the like. By a lithography process and a dry etching process, a concave pattern 2a including a groove, a hole, and the like is formed in a portion where a wiring structure such as a wiring pattern and a plug is to be formed in the wiring insulating film 2 in the future.

【0017】次に、この凹パターン2aを形成した配線
絶縁膜2の上に将来作製する配線構造を構成する導体膜
と良好な接合性を実現する密着層3として、たとえばT
iN膜を、P−CVD法等を用いて極薄く形成する(図
1(a))。
Next, on the wiring insulating film 2 on which the concave pattern 2a is formed, as an adhesion layer 3 for realizing good bonding with a conductor film constituting a wiring structure to be produced in the future, for example, T
An iN film is formed extremely thin using a P-CVD method or the like (FIG. 1A).

【0018】さらに、たとえば還元作用のある有機溶媒
4aに、たとえば銅(Cu)等の導体微粒子4bを懸濁
させた流動性のペースト/溶液4を、配線絶縁膜2(密
着層3)の表面全体に塗布する。有機溶媒4aに対する
導体微粒子4bの混合比率は、たとえば、85〜90
(重量%)程度である。この時、ペースト/溶液4は、
配線絶縁膜2の凹パターン2aの内部に確実に充填され
る(図1(b))。
Further, for example, a fluid paste / solution 4 in which conductive fine particles 4b such as copper (Cu) are suspended in an organic solvent 4a having a reducing action is applied to the surface of the wiring insulating film 2 (adhesion layer 3). Apply to the whole. The mixing ratio of the conductive fine particles 4b to the organic solvent 4a is, for example, 85 to 90.
(% By weight). At this time, the paste / solution 4
The inside of the concave pattern 2a of the wiring insulating film 2 is reliably filled (FIG. 1B).

【0019】ここで、金属微粉末等の導体微粒子4bを
溶かした還元作用のある有機溶媒4aは導体微粒子4b
の表面に存在する酸化物を除去する作用とともに金属微
粉末等の導体微粒子4bをペースト/溶液4にして、そ
の取り扱いを容易にする作用がある。ペースト/溶液4
の塗布の方法としては、刷毛塗り、回転塗布、浸漬等の
低コストで簡便な方法を用いることができる。
Here, the organic solvent 4a having a reducing action in which the conductive fine particles 4b such as metal fine powder are dissolved is used as the conductive fine particles 4b.
In addition to the action of removing oxides present on the surface, the conductive fine particles 4b such as metal fine powder are converted into a paste / solution 4 to facilitate the handling. Paste / solution 4
As a method of coating, a low-cost and simple method such as brush coating, spin coating, and dipping can be used.

【0020】凹パターン2aの幅寸法が、たとえば0.5
μm程度の場合、導体微粒子4bの粒径は、たとえば0.
05μm程度に設定される。
The width dimension of the concave pattern 2a is, for example, 0.5.
In the case of about μm, the particle diameter of the conductive fine particles 4b is, for example, 0.
It is set to about 05 μm.

【0021】その後、配線絶縁膜2に塗布されたペース
ト/溶液4における有機溶媒4aの除去、導体微粒子4
bの表面の酸化物の還元、導体微粒子4bの集合化等を
目的として、たとえば約300℃、大気圧下でベークを
行い、さらに、この300℃のベーク後、たとえば、大
気圧以上の任意の圧力による加圧状態で約500℃に加
熱および焼成し、導体微粒子4bを熱拡散等によって相
互に結合させることにより、銅等からなる緻密な導体膜
4cを形成する(図1(c))。
Thereafter, the organic solvent 4a in the paste / solution 4 applied to the wiring insulating film 2 is removed, and the conductive fine particles 4 are removed.
For the purpose of reducing the oxide on the surface of b, assembling the conductive fine particles 4b, and the like, baking is performed, for example, at about 300 ° C. under atmospheric pressure. Heating and baking to about 500 ° C. in a pressurized state, and bonding the conductive fine particles 4b to each other by thermal diffusion or the like, forms a dense conductive film 4c made of copper or the like (FIG. 1C).

【0022】最後に、凹パターン2aの内部以外に存在
する不要な導体膜4cを、たとえばCMP法や、エッチ
バック等により、配線絶縁膜2の表面が露出するまで平
坦に除去し、たとえば配線パターンや、多層配線構造等
においてコンタクトホール/スルーホール等に充填され
る導体プラグ等として機能する導体パターン4dを形成
する(図1(d))。
Finally, the unnecessary conductive film 4c existing outside the concave pattern 2a is removed by, for example, a CMP method or an etch back until the surface of the wiring insulating film 2 is exposed. Alternatively, a conductor pattern 4d functioning as a conductor plug or the like filled in a contact hole / through hole in a multilayer wiring structure or the like is formed (FIG. 1D).

【0023】このように、本実施の形態においては、有
機溶媒4aに、たとえば銅(Cu)等の導体微粒子4b
を懸濁させたペースト/溶液4の塗布、およびベーク/
焼成を経て緻密な導体膜4cを形成するので、たとえ
ば、P−CVD法や、スパッタ/リフロ等の方法に比較
して、所望の厚さの導体膜4cを、短時間で迅速に形成
することができる。また、回転塗布や刷毛塗り、浸漬等
の安価な設備によってペースト/溶液4を簡単に配線絶
縁膜2に塗布できるので、CVD装置や、スパッタ装置
等の高価な設備を必要とせず、導体膜4cの形成を低コ
ストで行うことができる。
As described above, in the present embodiment, the conductive fine particles 4b such as copper (Cu) are added to the organic solvent 4a.
Of paste / solution 4 in which is suspended, and baking /
Since the dense conductor film 4c is formed through firing, the conductor film 4c having a desired thickness can be quickly formed in a short time as compared with a method such as a P-CVD method or a sputtering / reflow method. Can be. Further, since the paste / solution 4 can be easily applied to the wiring insulating film 2 by inexpensive equipment such as spin coating, brush coating, immersion, etc., expensive equipment such as a CVD apparatus or a sputtering apparatus is not required, and the conductor film 4c is not required. Can be formed at low cost.

【0024】また、ペースト/溶液4の流動性により、
配線絶縁膜2の表面に形成された凹パターン2aの内部
に、当該ペースト/溶液4が確実に充填されるので、配
線パターンやプラグ等として機能する導体パターン4d
におけるボイド等に起因する接続不良等の欠陥の発生を
確実に防止でき、半導体装置の歩留りが向上する。特
に、たとえば、配線パターンとプラグの形成を一括して
行う、いわゆるデュアルダマシン法では、プラグ部分で
の埋め込み深さが、配線パターンの厚さ寸法とプラグの
深さ寸法との和になって一層深くなり、通常のCVD法
やスパッタ/リフロ法では、完全な導体の埋め込みが困
難になるが、本実施の形態の場合には流動性のペースト
/溶液4を塗布するので、深さに関係なく確実に導体パ
ターン4dの埋め込みが可能になり、得られる配線構造
の信頼性は一層向上する。
Also, due to the fluidity of the paste / solution 4,
Since the paste / solution 4 is reliably filled in the concave pattern 2a formed on the surface of the wiring insulating film 2, the conductor pattern 4d functioning as a wiring pattern, a plug, or the like.
Can reliably prevent the occurrence of defects such as connection failures due to voids and the like, and improve the yield of semiconductor devices. In particular, for example, in the so-called dual damascene method in which the formation of a wiring pattern and a plug is performed at once, the embedding depth in the plug portion is further increased by the sum of the thickness of the wiring pattern and the depth of the plug. Although it becomes difficult to completely embed the conductor by the ordinary CVD method or the sputtering / reflow method, in the case of the present embodiment, since the fluid paste / solution 4 is applied, regardless of the depth, The conductor pattern 4d can be reliably embedded, and the reliability of the obtained wiring structure is further improved.

【0025】従って、配線絶縁膜2に予め形成された凹
パターン2aに対する導体膜4cの充填形成を必要とす
るダマシンプロセス等において、導体膜4cの形成所要
時間の短縮によるスループットの向上、さらには、低コ
ストの設備の使用による工程コストの低減を実現でき
る。
Therefore, in a damascene process or the like that requires the formation of the conductive film 4c in the concave pattern 2a formed in advance in the wiring insulating film 2, the throughput is improved by shortening the time required for forming the conductive film 4c. Process costs can be reduced by using low-cost equipment.

【0026】また、配線パターンの素材として、銅を用
いる場合、アルミニウム等に比較して、電気抵抗値が小
さく、マイグレーション耐性等もアルミニウムに比較し
て大きく、従って、配線パターンとして機能する導体パ
ターン4dとして、本実施の形態のように銅を用いるこ
とにより、高速動作に動作し、かつ信頼性の高い半導体
装置を製造することができる。
When copper is used as the material of the wiring pattern, the electric resistance value is lower than that of aluminum or the like, and the migration resistance is higher than that of aluminum. By using copper as in this embodiment, a semiconductor device which operates at high speed and has high reliability can be manufactured.

【0027】以上本発明者によってなされた発明を実施
の形態に基づき具体的に説明したが、本発明は前記実施
の形態に限定されるものではなく、その要旨を逸脱しな
い範囲で種々変更可能であることはいうまでもない。
Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments and can be variously modified without departing from the gist thereof. Needless to say, there is.

【0028】たとえば、導体微粒子としては銅微粉末等
に限らず、一般の導体微粉末を用いることができる。ま
た、溶媒としては、有機溶媒に限らず、導体微粉末を懸
濁可能な一般の溶媒を広く用いることができる。
For example, the conductive fine particles are not limited to copper fine powder and the like, and general conductive fine powder can be used. The solvent is not limited to an organic solvent, and a general solvent capable of suspending the conductor fine powder can be widely used.

【0029】[0029]

【発明の効果】本願において開示される発明のうち、代
表的なものによって得られる効果を簡単に説明すれば、
以下のとおりである。
Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

【0030】(1).本発明の半導体装置の製造方法によれ
ば、導体膜の形成を伴う製造工程の所要時間を短縮して
スループットを向上させることができる、という効果が
得られる。
(1) According to the method of manufacturing a semiconductor device of the present invention, there is an effect that the time required for the manufacturing process involving the formation of the conductive film can be shortened and the throughput can be improved.

【0031】(2).絶縁膜に形成された凹パターン内部へ
の導体の埋め込みを確実に行うことができる、という効
果が得られる。
(2) The effect that the conductor can be reliably embedded in the concave pattern formed in the insulating film can be obtained.

【0032】(3).低設備コストにて、導体膜の形成を伴
う製造工程を構築および運用することができる、という
効果が得られる。
(3) It is possible to construct and operate a manufacturing process involving formation of a conductor film at a low equipment cost.

【0033】(4).低コストおよび高歩留りかつ高信頼度
の半導体装置を得ることができる、という効果が得られ
る。
(4) It is possible to obtain a semiconductor device with low cost, high yield, and high reliability.

【図面の簡単な説明】[Brief description of the drawings]

【図1】(a)〜(d)は、本発明の一実施の形態であ
る半導体装置の製造方法の一例を工程順に例示した略断
面図である。
FIGS. 1A to 1D are schematic cross-sectional views illustrating an example of a method for manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps;

【符号の説明】[Explanation of symbols]

1 基板 2 配線絶縁膜 2a 凹パターン 3 密着層 4 ペースト/溶液 4a 有機溶媒 4b 導体微粒子 4c 導体膜 4d 導体パターン Reference Signs List 1 substrate 2 wiring insulating film 2a concave pattern 3 adhesion layer 4 paste / solution 4a organic solvent 4b conductive fine particles 4c conductive film 4d conductive pattern

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】 任意の溶媒に導体微粒子を懸濁させたペ
ーストまたは溶液を絶縁膜の表面に塗布し、このペース
トまたは溶液に対して、加熱処理および加圧処理の少な
くとも一方を施すことにより導体膜を形成することを特
徴とする半導体装置の製造方法。
1. A paste or solution in which conductive fine particles are suspended in an arbitrary solvent is applied to the surface of an insulating film, and the paste or solution is subjected to at least one of a heat treatment and a pressure treatment to form a conductor. A method for manufacturing a semiconductor device, comprising forming a film.
【請求項2】 絶縁膜の表面に凹パターンを形成する第
1の工程と、 前記絶縁膜の表面に任意の溶媒に導体微粒子を懸濁させ
たペーストまたは溶液を塗布して前記凹パターンの内部
に充填する第2の工程と、 前記絶縁膜に塗布された前記ペーストまたは溶液に対し
て、加圧処理および加熱処理の少なくとも一方を施すこ
とによって、当該ペーストまたは溶液を導体膜にする第
3の工程と、 前記絶縁膜の表面が露出するまで前記導体膜を除去し、
前記凹パターンの内部に前記導体膜を選択的に残存させ
る第4の工程と、 を含むことを特徴とする半導体装置の製造方法。
2. A first step of forming a concave pattern on the surface of the insulating film, and applying a paste or a solution in which conductive fine particles are suspended in an arbitrary solvent to the surface of the insulating film to form an inner surface of the concave pattern. A second step of filling the paste or solution applied to the insulating film with a pressure treatment and / or a heat treatment to form a third conductive film from the paste or solution. Removing the conductive film until the surface of the insulating film is exposed,
A fourth step of selectively leaving the conductive film inside the concave pattern.
【請求項3】 請求項2記載の半導体装置の製造方法に
おいて、前記第4の工程では、化学的機械的研磨処理
(CMP)により、前記凹パターン内部以外の前記導体
膜を平坦に除去することを特徴とする半導体装置の製造
方法。
3. The method for manufacturing a semiconductor device according to claim 2, wherein, in the fourth step, the conductive film other than the inside of the concave pattern is flatly removed by a chemical mechanical polishing process (CMP). A method for manufacturing a semiconductor device, comprising:
【請求項4】 請求項2記載の半導体装置の製造方法に
おいて、前記第3の工程では、大気圧下で所定の第1の
温度によるベークを行った後、加圧状態の下で第2の温
度で加熱する処理を行うことを特徴とする半導体装置の
製造方法。
4. The method of manufacturing a semiconductor device according to claim 2, wherein in the third step, after performing a bake at a predetermined first temperature under an atmospheric pressure, the second step is performed under a pressurized state. A method for manufacturing a semiconductor device, comprising performing a heating process at a temperature.
【請求項5】 請求項2記載の半導体装置の製造方法に
おいて、前記第1の温度は約300℃であり、前記第2
の温度は約500℃であることを特徴とする半導体装置
の製造方法。
5. The method according to claim 2, wherein the first temperature is about 300 ° C., and the second temperature is about 300 ° C.
The temperature of the semiconductor device is about 500 ° C.
【請求項6】 請求項2記載の半導体装置の製造方法に
おいて、前記導体微粒子は銅(Cu)からなり、前記溶
媒は有機溶媒からなることを特徴とする半導体装置の製
造方法。
6. The method of manufacturing a semiconductor device according to claim 2, wherein said conductive fine particles are made of copper (Cu), and said solvent is made of an organic solvent.
JP21071596A 1996-08-09 1996-08-09 Manufacture of semiconductor device Pending JPH1056060A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21071596A JPH1056060A (en) 1996-08-09 1996-08-09 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21071596A JPH1056060A (en) 1996-08-09 1996-08-09 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH1056060A true JPH1056060A (en) 1998-02-24

Family

ID=16593910

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21071596A Pending JPH1056060A (en) 1996-08-09 1996-08-09 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH1056060A (en)

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0980094A1 (en) * 1998-08-10 2000-02-16 Vacuum Metallurgical Co. Ltd. Method for forming Cu-thin film
JP2000124157A (en) * 1998-08-10 2000-04-28 Vacuum Metallurgical Co Ltd FORMATION OF Cu THIN FILM
JP2000306912A (en) * 1999-04-23 2000-11-02 Ulvac Japan Ltd Metal thin-film forming method
WO2001029283A1 (en) * 1999-10-19 2001-04-26 Ebara Corporation Plating method, wiring forming method and devices therefor
US6235624B1 (en) 1998-06-01 2001-05-22 Kabushiki Kaisha Toshiba Paste connection plug, burying method, and semiconductor device manufacturing method
EP0980097A3 (en) * 1998-08-10 2002-03-20 Vacuum Metallurgical Co. Ltd. Dispersion containing Cu ultrafine particles individually dispersed therein
WO2005122230A1 (en) * 2004-06-07 2005-12-22 Kyushu Institute Of Technology Method for processing copper surface, method for forming copper pattern wiring and semiconductor device manufactured using such method
KR100744601B1 (en) * 2001-12-29 2007-08-01 매그나칩 반도체 유한회사 Method for forming copper line in semiconductor device
WO2012128139A1 (en) 2011-03-24 2012-09-27 富士フイルム株式会社 Method for forming copper wiring, method for manufacturing wiring substrate, and wiring substrate
CN102738069A (en) * 2011-03-30 2012-10-17 东京毅力科创株式会社 Method for manufacturing semiconductor device
JPWO2015064682A1 (en) * 2013-10-30 2017-03-09 京セラ株式会社 Sapphire structure with metal body, method for manufacturing sapphire structure with metal body, electronic device, and exterior body
US10276515B2 (en) 2015-09-25 2019-04-30 Dai Nippon Printing Co., Ltd. Mounting component, wiring substrate, electronic device and manufacturing method thereof

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6235624B1 (en) 1998-06-01 2001-05-22 Kabushiki Kaisha Toshiba Paste connection plug, burying method, and semiconductor device manufacturing method
US6657306B1 (en) 1998-06-01 2003-12-02 Kabushiki Kaisha Toshiba Paste including a mixture of powders, connection plug, burying method, and semiconductor device manufacturing method
US7049223B2 (en) 1998-06-01 2006-05-23 Kabushiki Kaisha Toshiba Paste including a mixture of powders, connection plug, burying method, and semiconductor device manufacturing method
JP2000124157A (en) * 1998-08-10 2000-04-28 Vacuum Metallurgical Co Ltd FORMATION OF Cu THIN FILM
EP0980097A3 (en) * 1998-08-10 2002-03-20 Vacuum Metallurgical Co. Ltd. Dispersion containing Cu ultrafine particles individually dispersed therein
EP0980094A1 (en) * 1998-08-10 2000-02-16 Vacuum Metallurgical Co. Ltd. Method for forming Cu-thin film
JP2000306912A (en) * 1999-04-23 2000-11-02 Ulvac Japan Ltd Metal thin-film forming method
WO2001029283A1 (en) * 1999-10-19 2001-04-26 Ebara Corporation Plating method, wiring forming method and devices therefor
US6709555B1 (en) 1999-10-19 2004-03-23 Ebara Corporation Plating method, interconnection forming method, and apparatus for carrying out those methods
KR100744601B1 (en) * 2001-12-29 2007-08-01 매그나칩 반도체 유한회사 Method for forming copper line in semiconductor device
WO2005122230A1 (en) * 2004-06-07 2005-12-22 Kyushu Institute Of Technology Method for processing copper surface, method for forming copper pattern wiring and semiconductor device manufactured using such method
US7825026B2 (en) 2004-06-07 2010-11-02 Kyushu Institute Of Technology Method for processing copper surface, method for forming copper pattern wiring and semiconductor device manufactured using such method
WO2012128139A1 (en) 2011-03-24 2012-09-27 富士フイルム株式会社 Method for forming copper wiring, method for manufacturing wiring substrate, and wiring substrate
CN102738069A (en) * 2011-03-30 2012-10-17 东京毅力科创株式会社 Method for manufacturing semiconductor device
JPWO2015064682A1 (en) * 2013-10-30 2017-03-09 京セラ株式会社 Sapphire structure with metal body, method for manufacturing sapphire structure with metal body, electronic device, and exterior body
US10276515B2 (en) 2015-09-25 2019-04-30 Dai Nippon Printing Co., Ltd. Mounting component, wiring substrate, electronic device and manufacturing method thereof
US10672722B2 (en) 2015-09-25 2020-06-02 Dai Nippon Printing Co., Ltd. Mounting component and electronic device

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