JP3328430B2 - Method for forming multilayer wiring of semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a multilayer wiring of a semiconductor device, and more particularly to the application of SOG (spin on glass) to a semiconductor device.

[0002]

2. Description of the Related Art Conventionally, techniques in such a field include:
For example, there are the following.

FIG. 3 is a view showing a conventional method for forming a multilayer wiring of a semiconductor device.

First, as shown in FIG. 3A, a first layer wiring 2 is formed on a semiconductor substrate 1 on which transistors and the like have already been formed.
To form

Next, as shown in FIG. 3B, a first insulating film 3 is formed as necessary.

Next, as shown in FIG. 3C, SOG 4 is applied on the first insulating film 3 a plurality of times to fill the steps of the first layer wiring 2 and to flatten it.

Next, as shown in FIG.
Baking (curing at about 400 ° C.) for desorbing moisture therein is performed, and then a second insulating film 6 is formed. Although not shown, the first insulating film 3
Through holes are opened through the SOG 4 and the second insulating film 6, and finally, a second layer wiring is formed.

[0008] In addition to the above, SOG is used as a sacrificial film for etch back.

As shown in FIG. 4A, the semiconductor substrate 11 on which the first layer wiring 12 and the interlayer insulating film 13 have already been formed.
As shown in FIG. 4B, the SOG 14 is applied once or a plurality of times, and is planarized.
Baking (curing at about 400 ° C.) for desorbing moisture in the OG 14 is performed.

Then, as shown in FIG. 4C, a flat interlayer insulating film 15 is obtained by etching back the entire surface. Thereafter, although not shown, the first layer wiring 12 is formed.
Through holes are opened in necessary upper portions through the interlayer insulating film 13, and finally a second-layer wiring is formed.

[0011]

However, in the multilayer wiring structure according to the above-described conventional forming method, SOG is applied thickly at a portion where the wiring interval is small and at a contact portion connecting the semiconductor element and the first layer wiring. Then, the SOG itself shrinks in the subsequent firing, so that an SOG crack 5 is generated as shown in FIG. The SOG crack 5 cannot fill the crack itself when the second insulating film 6 is formed, and the SOG crack 5 remains as shown in FIG.

Generally, SO used for burying planarization is used.
G has a large thermal shrinkage (approximately 24%) in firing (heating to 400 ° C.), so that cracks occur when SOG is thick and applied in a large amount.

FIG. 5B is a sectional view of a semiconductor device having such a multilayer wiring structure. A first insulating film 22 is formed on a semiconductor substrate 21, and a first insulating film 22 is formed on the first insulating film 22. SOG in which a crack 24A is formed in a concave portion between layer wirings 23
24, a second insulating film 25, a third insulating film 26, and a protective film 27 are sequentially stacked thereon.

As shown in FIG. 5B, the surface of the second insulating film 25 formed on the SOG crack 24A has
[In FIG. 3D, this is shown as the second insulating film 6] There are irregularities, and when a second layer wiring is formed there, poor coverage with the wiring, poor etching, etc. are caused.

Similarly, the SOG used as a sacrificial film for the etch-back, as shown in FIG.
Is thickened in the portion 34A, and when SOG is baked,
An OG crack 35 occurs. 31 is a semiconductor substrate,
32 is a first layer wiring, and 33 is an interlayer insulating film.

In this state, when the entire surface is etched, as shown in FIG.
OG crack 35A remains. That is, unevenness remains on the surface, and a flat interlayer insulating film cannot be formed. Thereafter, when forming the second-layer wiring, a coverage defect, an etching defect, or the like is caused.

The present invention has been made in order to solve the above problems.
Provided is a method for forming a multi-layer wiring of a semiconductor element by forming a smooth insulating film by eliminating SOG cracks generated in a concave portion of a lower wiring portion and not causing a coverage defect or an etching defect when forming the upper wiring. The purpose is to do.

[0018]

According to the present invention, there is provided a method for forming a multilayer wiring of a semiconductor device, in which SOG for planarizing the lower wiring is applied a plurality of times. the recess by applying a number of applications of SOG as often as little once the predetermined number of times, and calcined forming a SOG thickness 0.5 [mu] m, the SOG of thickness 0.5 [mu] m, the thickness
Generating a crack in the 0.5 μm SOG;
It was coated in SOG SOG thin top <br/> later than the thickness at the coating of the thickness of 0.5 [mu] m, forming a SOG thinner buried the crack, and a step of firing the SOG of the diluted Is applied.

(2) In a method of forming a multilayer wiring of a semiconductor device, in which a sacrificial film of SOG is etched back to flatten the interlayer insulating film, the number of times of applying SOG on the interlayer insulating film having irregularities formed on the lower wiring is determined. An SO film having a thickness of 0.5 μm is applied between lower wirings by applying the coating only once less than a predetermined number.
Forming a G, firing the SOG of thickness 0.5 [mu] m, a step of generating a crack in the SOG of the thickness of 0.5 [mu] m, the thickness at the coating of the SOG of the thickness of 0.5 [mu] m
Performed thinner final SOG coating of, forming a SOG thinner buried the cracks, S of the thin
And a step of firing OG.

[0020]

According to the present invention, as described above, in the step of forming a multi-layered wiring of a semiconductor element, a thick SOG is formed by applying a plurality of times to a concave portion of a lower wiring portion, and cracks due to firing are prevented. Forming the SOG with a thickness of 0.5 μm in the concave portion of the lower wiring portion by applying the SOG one time less than the predetermined number of times.
The SOG thickness 0.5μm was firing, the thickness of 0.5μ
generating a crack in the SOG having a thickness of
The last SO thinner than the thickness at the time of applying the SOG of 0.5 μm
G is applied and the cracks are embedded and thin SOG
And the step of baking this thin SOG are performed, so that SOG cracks can be eliminated and a smooth insulating film can be formed. In addition, etching defects and the like do not occur.

Further, when the sacrificial film of the SOG is etched back to planarize the interlayer insulating film, it is possible to eliminate a step and an etching defect in metal etching thereover.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a sectional view showing a step of forming a multilayer wiring of a semiconductor device according to a first embodiment of the present invention.

(1) As shown in FIG. 1A, a first layer wiring 42 is formed on a semiconductor substrate 41 on which transistors and the like have already been formed.

(2) Next, as shown in FIG. 1B, a first insulating film 43 is formed as necessary. Thereafter, the SOG 44 is applied up to one time before the desired number of SOG applications (or up to two applications if three applications are desired).

(3) At this point, firing (heat treatment at 400 ° C.) is performed. By firing at this time, places with narrow wiring intervals,
As shown in FIG. 1 (c), the SOG crack 4
5 occurs. Here, in the case of inorganic SOG,
When the thickness is about 0.5 μm and the thickness of about 1 μm in the case of organic SOG, when firing, SOG cracks occur.

(4) Thereafter, as shown in FIG.
The last SOG coating is performed, and the inside of the SOG crack 45 is S
Fill with OG44A.

(5) Thereafter, as shown in FIG.
Perform firing again. In the firing at this time, the last SOG
Since the amount of SOG applied in the application is small, no crack occurs in the baked SOG 44B.

(6) Thereafter, as shown in FIG.
A second insulating film 46 is formed.

With this configuration, cracks do not occur in the SOG, a smooth insulating film is formed, and defects such as poor coverage and poor etching when forming the second-layer wiring are prevented. .

FIG. 2 is a sectional view showing a step of forming a multilayer wiring of a semiconductor device according to a second embodiment of the present invention. In this embodiment, a case where SOG is used as a sacrificial film for etch back will be described.

(1) First, as shown in FIG. 2A, when SOG is used as a sacrificial film for etch back, a first layer wiring 52 is formed on a semiconductor substrate 51 on which transistors and the like have already been formed. Further, an interlayer insulating film 53 is formed on the first layer wiring 52.

(2) Next, as shown in FIG. 2B, the SOG 54 is applied up to one time before the desired SOG application number. For example, if three coats of SOG are desired, the coat is applied up to two coats.

(3) Next, firing is performed at this point. In the firing at this time, the portion where the SOG 54 is thickly applied is shown in FIG.
As shown in (c), the SOG crack 55 occurs.

(4) Thereafter, as shown in FIG.
The final SOG 54A is applied, and the SOG crack 55
The inside is filled with SOG54A. After that, firing is performed again.

In the firing at this time, as in the first embodiment, no crack occurs because the amount of SOG applied at the time of final SOG application is small.

In the above embodiment, an example is shown in which the first insulating film is formed on the first layer wiring.
In the case where the insulating film is omitted and SOG is applied to the concave portion between the first layer wirings, the same operation and effect as described above can be obtained.

Further, the present invention is not limited to the above embodiment, and various modifications can be made based on the gist of the present invention, and they are not excluded from the scope of the present invention.

[0039]

As described above, according to the present invention, the following effects can be obtained.

(1) It is possible to eliminate a SOG crack generated in a concave portion of a lower wiring portion and to form a smooth insulating film.
It is possible to form a highly reliable multi-layer wiring of a semiconductor element without causing a coverage defect, an etching defect, or the like when forming the upper wiring.

(2) When the sacrificial film of the SOG is etched back and the interlayer insulating film is planarized, steps and etching defects in the metal etching thereover can be eliminated.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a step of forming a multilayer wiring of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing a step of forming a multilayer wiring of a semiconductor device according to a second embodiment of the present invention.

FIG. 3 is a diagram illustrating a conventional method for forming a multilayer wiring of a semiconductor device.

FIG. 4 is a view showing a conventional method for forming a multilayer wiring of a semiconductor element in which SOG is formed as a sacrificial film for etch back.

FIG. 5 is an explanatory diagram of a first problem of the related art.

FIG. 6 is an explanatory diagram of a second problem of the related art.

[Explanation of symbols]

 41, 51 Semiconductor substrate 42, 52 First layer wiring 43 First insulating film 44, 44A, 44B, 54, 54A SOG 45, 55 SOG crack 46 Second insulating film 53 Interlayer insulating film

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int. Cl. ⁷ , DB name) H01L 21/3205 H01L 21/321 H01L 21/3213 H01L 21/768

Claims (2)

(57) [Claims] 1. A method of forming a multilayer wiring of a semiconductor element, in which SOG for planarizing a lower wiring portion is applied a plurality of times, comprising: (a) reducing the number of times of applying SOG to a concave portion of the lower wiring portion by one less than a predetermined number of times; Only 0.5μm thick
Forming a SOG, firing the SOG of (b) the thickness of 0.5 [mu] m, the thickness of 0.
A step of generating cracks in the 5 μm SOG; and (c) a step of applying the 0.5 μm thick SOG when applied.
Thin last was coated in SOG, forming a SOG thinner buried the cracks, (d) a multilayer wiring formation method of a semiconductor device characterized by performing the step of firing the thin of SOG. 2. A method for forming a multilayer wiring of a semiconductor device, in which a sacrificial film of an SOG is etched back to flatten an interlayer insulating film, comprising: (a) applying SOG to an interlayer insulating film having irregularities formed on a lower wiring; forming a SOG thickness 0.5 [mu] m between the lower layer wiring by coating a number of times as often as little once the predetermined number of times, and baking an SOG (b), the thickness of 0.5 [mu] m, the thickness 0 .
A step of generating cracks in the 5 μm SOG; and (c) a step of applying the 0.5 μm thick SOG when applied.
Thin last was coated in SOG, forming a SOG thinner buried the cracks, (d) a multilayer wiring formation method of a semiconductor device characterized by performing the step of firing the SOG Me thin.