JPH01192137A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the gas from SOG in case of coating the second layer metallic wiring material from dissipating by a method wherein insulating films are left on the sidewall surfaces of communicating holes by selectively performing reactive ion etching process. CONSTITUTION:An n-channel transistor is formed on a P type substrate 1, the patterns of the first layer Al-Si wiring are formed to deposit the first insulating film 8. Successively, the whole surface is coated with a SOG film 9 to be set and after flattening process, the second insulating film 8' is deposited. Next, communicating holes 10 reaching the Al-Si alloy wiring 7 are made by reactive ion etching process using photoresist mask patterns to remove the photoresist comprising mask material by oxygen ashing process. Then, the third insulating films 10 are deposited on the newly formed semiconductor substrate and then etched away by reactive ion etching process to reach the first layer Al-Si alloy wiring 7. At this time, the third insulating films 10 are left on the sidewall surfaces of the communicating holes 10. Finally, the whole surface is coated with the second layer Al-Si alloy and then the second layer Al-Si alloy wiring 12 patterns are etched away by reactive ion etching process using chlorine based gas as well as photoresist mask patterns.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a semiconductor device using AQ multilayer wiring technology.

(Prior Art) Conventionally, as semiconductor devices become more highly integrated, the size of the devices has been reduced. Further, in forming metal electrode wiring, for example, aluminum wiring, multilayer wiring having two or more layers has been used. In multilayer wiring, in order to accurately form the second layer of metal wiring, a planarization technique is required to flatten the insulating film between it and the first layer of metal wiring. Generally, two methods are known as planarization techniques. One method is to flatten the unevenness produced on the semiconductor substrate after forming the first layer metal wiring pattern and covering the first layer of interlayer insulation by spin-coating a photoresist or the like, and then etching the surface. This is a resist etch-back method in which only the convex portions of the interlayer insulating film are etched, and the concave portions are flattened by protecting them from Etk. The other method is the SOG method, in which SOG is applied on the uneven surface of the semiconductor substrate after the interlayer insulating film has been coated, and the interlayer insulating film on the rear side 2 is coated to achieve flatness.

The problems with these conventional planarization methods are that the resist etch-back method described above has difficulty controlling the etching of convex portions, and the SOG method described later is effective at flattening convex and convex portions; When opening a communication hole connecting the metal wiring of the first layer and the metal wiring of the first layer, and depositing the metal wiring material of the second layer, gas released from the SOG film damages the side wall surface of the communication hole, especially in the 800th layer. A problem arose in that the metal wiring material was thinly deposited in some areas.

(Problem to be Solved by the Invention) As described above, in the conventional technology, when depositing the second layer metal wiring material, the metal wiring material is thinly deposited due to gas release from the SOG film, which reduces the reliability of the semiconductor device. There was a problem with the decline.

The present invention has been made in consideration of the above problems, and its purpose is to provide a manufacturing method that can improve the reliability of a semiconductor device having a two-layer metal wiring structure using the SOG method. be.

[Structure of the invention]

(Means for Solving the Problems) The present invention involves forming an insulating film on the rear part 1 on which a first-layer metal wiring pattern for connecting elements formed on a semiconductor substrate is formed, applying SOG, and then applying a second-layer insulating film. After forming the insulating film,
A communication hole communicating with the first layer metal wiring pattern is opened through the second insulating film, the SOG film, and the first insulating film. The purpose is to form this insulating film on the rear part 3 and selectively perform reactive ion etching to leave a third insulating film on the side wall surface of the communicating hole.

(Function) According to the present invention, by leaving an insulating film on the side wall surface of the communication hole, S is reduced when depositing the second layer of metal wiring material.

Gas released from G can be prevented, a uniform metal wiring material can be deposited, and a highly reliable metal wiring pattern can be formed.

(Example) The details of the present invention will be explained below using illustrated embodiments.

FIG. 1(a) shows a cross-sectional view of the process up to the communication hole connecting the second layer metal wiring and the first layer metal wiring using a semiconductor device manufacturing method similar to the conventional method. a) is formed through the steps shown below.

That is, an n-channel transistor is formed on a P-type substrate 1, and the first layer is Al1-8i (Si content 1.5%).
A pattern of alloy wiring 7 is provided, and a first insulating film 8 is deposited with a silicon oxide film to a thickness of 0.5 kon by plasma CVD. Subsequently, the SOG film 9 is coated on the entire surface to a thickness of 0.3° and cured, and the flattened insulating film 8' on the rear part 2 is coated to a thickness of 0.5° by the same plasma CVD method as the first insulating film 8. accumulate. Subsequently, using a photoresist mask pattern, Affi-
A communication hole 10 reaching above the 7 patterns of 8i alloy wiring is opened by a reactive ion etching method using Freon gas.
The photoresist mask material is removed by oxygen ashing. Through the above steps, the structure shown in FIG. 1(a) is formed.

FIGS. 1(b) and 1(c) show cross-sectional views of steps related to the present invention.

FIG. 1(b) is formed through the steps shown below.

That is, a third insulating film was deposited on the semiconductor substrate formed in FIG. . Etching was performed by reactive ion etching to reach the first layer AJ-8i alloy wiring 7. This hourly hole 10
The third insulating film 10 remained on the side wall surface.

The structure shown in FIG. 1(c) is formed through the following steps.

That is, the second layer of AQ-8i (Sit deposition amount: 1.5%) alloy was deposited with a thickness of 0.5p, and the second layer of 12 patterns of Al1-5i alloy wiring was covered with chlorine gas using a photoresist mask pattern. Etching was performed using a reactive ion etching method.

〔Effect of the invention〕

The AQ-8i alloy wiring pattern obtained as above was able to obtain a uniform pattern without becoming thin on the side wall surface of the communication hole.

Although the present invention has been described in detail using Examples above, the application of the present invention is not limited to these Examples in any way. The effect of the present invention was obtained even when the structure was formed.

[Brief explanation of the drawing]

FIG. 1 is a diagram of an embodiment, and FIG. 2 is a diagram for explaining the effect. In fig. ■... When this example is used ■... When the conventional technology is used Agent Patent attorney Noriyuki Chika Yudo Mitsuyuki Matsuyama @ Figure 1

Claims (3)

[Claims] (1) A step of forming a first layer aluminum wiring pattern on an element formed on the surface of a semiconductor substrate, a step of forming a first insulating film on the surface, a step of applying SOG, and a step of forming a first layer of aluminum wiring pattern on the element formed on the surface of the semiconductor substrate. a step of forming an insulating film; a step of opening a communication hole that communicates the second insulating film with the SOG and the first insulating film and connects to the first layer aluminum wiring pattern;
It is characterized by comprising the step of selectively forming a third insulating film on the side wall surface of the communication hole, and then depositing a second layer of aluminum film on the entire surface to form a desired metal wiring pattern. A method for manufacturing a semiconductor device. (2) Manufacturing the semiconductor device according to claim 1, wherein the thickness of the insulating film selectively formed on the side wall surface of the communication hole is 1/5 or less of the short side or diameter of the communication hole. Method. (3) The method of manufacturing a semiconductor device according to claim 1, wherein the first, second, and third insulating films are silicon oxide films or silicon nitride films formed by plasma CVD.